Re: [PATCH v11 2/6] perf mem: Add support for printing PERF_MEM_LVLNUM_L0

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] perf: L0 cache hits are silently dropped in perf c2c statistics
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commit f3eb05aaf438922225a25a217c33e99b8e7d269e
Author: Dapeng Mi <dapeng1.mi@linux.intel.com>

    perf mem: Add support for printing PERF_MEM_LVLNUM_L0
    
    Add support for printing PERF_MEM_LVLNUM_L0 in perf mem report.
    
    The L0 cache is newly added a small piece of cache which is
    the closest, lowest-latency memory cache tied directly to the
    execution pipeline.
    
    The table "Table 9-4. Data Source Field Encodings for Panther
    Cove and Coyote Cove Microarchitectures" in the ISE doc chapter
    "9.2.1 Panther Cove and Coyote Cove Microarchitectures Memory
    Auxiliary Field Layout"[1] indicates the code "01H" means the
    "L0 Hit - Minimal latency core cache hit. This request was
    satisfied by the L0 data cache."

> diff --git a/tools/perf/util/mem-events.c b/tools/perf/util/mem-events.c
> index 4e490f9cd3488..4fd48fd200552 100644
> --- a/tools/perf/util/mem-events.c
> +++ b/tools/perf/util/mem-events.c
> @@ -391,6 +391,7 @@ static const char * const mem_lvlnum[] = {
>  	[PERF_MEM_LVLNUM_L4] = "L4",
>  	[PERF_MEM_LVLNUM_L2_MHB] = "L2 MHB",
>  	[PERF_MEM_LVLNUM_MSC] = "Memory-side Cache",
> +	[PERF_MEM_LVLNUM_L0] = "L0",

[Severity: Medium]
This is a pre-existing issue, but does sort__lvl_cmp() in tools/perf/util/sort.c
incorrectly merge histogram entries for L0 cache hits with other unmatched cache
hierarchies?

Because sort__lvl_cmp() exclusively compares the deprecated mem_lvl bitmask
when determining the sort order:

	return (int64_t)(data_src_r.mem_lvl - data_src_l.mem_lvl);

Since PERF_MEM_LVLNUM_L0 and other new levels are only defined in mem_lvl_num,
their mem_lvl evaluates to 0. This causes them to be incorrectly grouped
together with other unrecognized hierarchies like CXL or PMEM in perf report.

[Severity: Medium]
Will L0 cache hits be silently dropped in perf c2c statistics since they are
not accounted for in c2c_decode_stats() in tools/perf/util/mem-events.c?

c2c_decode_stats() populates c2c_stats by checking the deprecated mem_lvl
bitmask:

			if (lvl & P(LVL, L1 )) stats->ld_l1hit++;
			if (lvl & P(LVL, L2)) {

Since PERF_MEM_LVLNUM_L0 is encoded in the new mem_lvl_num field, L0 cache
hits will bypass these cache depth checks entirely. In addition, the c2c_stats
structure lacks an ld_l0hit counter to track them.

>  	[PERF_MEM_LVLNUM_UNC] = "Uncached",
>  	[PERF_MEM_LVLNUM_CXL] = "CXL",
>  	[PERF_MEM_LVLNUM_IO] = "I/O",

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Sashiko AI review · https://sashiko.dev/#/patchset/20260923155703.34814-1-thomas.falcon@intel.com?part=2