* [PATCH v3] perf/arm_cspmu: Add Arm system PMU
@ 2026-10-05 14:11 Robin Murphy
2026-10-05 14:24 ` sashiko-bot
2026-10-08 4:47 ` Ilkka Koskinen
0 siblings, 2 replies; 3+ messages in thread
From: Robin Murphy @ 2026-10-05 14:11 UTC (permalink / raw)
To: will; +Cc: mark.rutland, linux-perf-users, linux-arm-kernel
Arm's latest Compute Subsystems and SoCs are using a common PMU block
in various places which can mostly just be driven as a generic 64-bit
CoreSight PMU, but does have an IMP-DEF register for additional
filtering. The details of event and filter encodings depend on the
particular PMU instance, so are left to the higher level Arm Telemetry
Solution tooling.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
v3: Fix 32-bit COMPILE_TEST to match arm_cspmu.c
drivers/perf/arm_cspmu/Kconfig | 7 +++
drivers/perf/arm_cspmu/Makefile | 1 +
drivers/perf/arm_cspmu/arm_cspmu.c | 7 +++
drivers/perf/arm_cspmu/arm_cspmu.h | 1 +
drivers/perf/arm_cspmu/arm_syspmu.c | 67 +++++++++++++++++++++++++++++
5 files changed, 83 insertions(+)
create mode 100644 drivers/perf/arm_cspmu/arm_syspmu.c
diff --git a/drivers/perf/arm_cspmu/Kconfig b/drivers/perf/arm_cspmu/Kconfig
index 6f4e28fc84a2..25bd55f036a4 100644
--- a/drivers/perf/arm_cspmu/Kconfig
+++ b/drivers/perf/arm_cspmu/Kconfig
@@ -27,3 +27,10 @@ config AMPERE_CORESIGHT_PMU_ARCH_SYSTEM_PMU
In the first phase, the driver enables support on MCU PMU used in
AmpereOne SoC family.
+
+config ARM_SYSTEM_PMU
+ tristate "Arm System PMU"
+ depends on ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU
+ help
+ Support additional event filtering attributes for the CoreSight-based
+ PMU blocks found in various parts of Arm Compute Subsystems and SoCs.
diff --git a/drivers/perf/arm_cspmu/Makefile b/drivers/perf/arm_cspmu/Makefile
index 220a734efd54..90c3cd710157 100644
--- a/drivers/perf/arm_cspmu/Makefile
+++ b/drivers/perf/arm_cspmu/Makefile
@@ -8,3 +8,4 @@ arm_cspmu_module-y := arm_cspmu.o
obj-$(CONFIG_NVIDIA_CORESIGHT_PMU_ARCH_SYSTEM_PMU) += nvidia_cspmu.o
obj-$(CONFIG_AMPERE_CORESIGHT_PMU_ARCH_SYSTEM_PMU) += ampere_cspmu.o
+obj-$(CONFIG_ARM_SYSTEM_PMU) += arm_syspmu.o
diff --git a/drivers/perf/arm_cspmu/arm_cspmu.c b/drivers/perf/arm_cspmu/arm_cspmu.c
index 912f03ce3ef5..9f298ea1a974 100644
--- a/drivers/perf/arm_cspmu/arm_cspmu.c
+++ b/drivers/perf/arm_cspmu/arm_cspmu.c
@@ -358,6 +358,13 @@ static struct arm_cspmu_impl_match impl_match[] = {
.module = NULL,
.impl_init_ops = NULL,
},
+ {
+ .module_name = "arm_syspmu",
+ .pmiidr_val = ARM_CSPMU_IMPL_ID_ARM,
+ .pmiidr_mask = PMIIDR_IMPLEMENTER,
+ .module = NULL,
+ .impl_init_ops = NULL,
+ },
{
.module_name = "ampere_cspmu",
.pmiidr_val = ARM_CSPMU_IMPL_ID_AMPERE,
diff --git a/drivers/perf/arm_cspmu/arm_cspmu.h b/drivers/perf/arm_cspmu/arm_cspmu.h
index c4058d602477..03e34692a965 100644
--- a/drivers/perf/arm_cspmu/arm_cspmu.h
+++ b/drivers/perf/arm_cspmu/arm_cspmu.h
@@ -149,6 +149,7 @@
/* JEDEC-assigned JEP106 identification code */
#define ARM_CSPMU_IMPL_ID_NVIDIA 0x36B
+#define ARM_CSPMU_IMPL_ID_ARM 0x43B
#define ARM_CSPMU_IMPL_ID_AMPERE 0xA16
/* PMDEVARCH */
diff --git a/drivers/perf/arm_cspmu/arm_syspmu.c b/drivers/perf/arm_cspmu/arm_syspmu.c
new file mode 100644
index 000000000000..2f5ceda5c4d1
--- /dev/null
+++ b/drivers/perf/arm_cspmu/arm_syspmu.c
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <linux/io-64-nonatomic-lo-hi.h>
+#include <linux/module.h>
+
+#include "arm_cspmu.h"
+
+#define PMEVFILT3R 0x200
+
+static struct attribute *arm_syspmu_format_attrs[] = {
+ ARM_CSPMU_FORMAT_EVENT_ATTR,
+ ARM_CSPMU_FORMAT_FILTER_ATTR,
+ ARM_CSPMU_FORMAT_FILTER2_ATTR,
+ ARM_CSPMU_FORMAT_ATTR(filter3, "config3:0-63"),
+ NULL,
+};
+
+static struct attribute **arm_syspmu_get_format_attrs(const struct arm_cspmu *cspmu)
+{
+ return devm_kmemdup(cspmu->dev, arm_syspmu_format_attrs,
+ sizeof(arm_syspmu_format_attrs), GFP_KERNEL);
+}
+
+static void arm_syspmu_set_ev_filter(struct arm_cspmu *cspmu,
+ const struct perf_event *event)
+{
+ u32 offset = 8 * event->hw.idx;
+
+ writeq(event->attr.config1, cspmu->base0 + PMEVFILTR + offset);
+ writeq(event->attr.config2, cspmu->base0 + PMEVFILT2R + offset);
+ writeq(event->attr.config3, cspmu->base0 + PMEVFILT3R + offset);
+}
+
+static int arm_syspmu_init_ops(struct arm_cspmu *cspmu)
+{
+ switch (FIELD_GET(PMIIDR_PRODUCTID, cspmu->impl.pmiidr)) {
+ case 0x9c3:
+ cspmu->impl.ops.set_ev_filter = arm_syspmu_set_ev_filter;
+ cspmu->impl.ops.get_format_attrs = arm_syspmu_get_format_attrs;
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static const struct arm_cspmu_impl_match arm_syspmu_param = {
+ .pmiidr_val = ARM_CSPMU_IMPL_ID_ARM,
+ .module = THIS_MODULE,
+ .impl_init_ops = arm_syspmu_init_ops
+};
+
+static int __init arm_syspmu_init(void)
+{
+ return arm_cspmu_impl_register(&arm_syspmu_param);
+}
+
+static void __exit arm_syspmu_exit(void)
+{
+ arm_cspmu_impl_unregister(&arm_syspmu_param);
+}
+
+module_init(arm_syspmu_init);
+module_exit(arm_syspmu_exit);
+
+MODULE_DESCRIPTION("Arm System PMU Driver");
+MODULE_LICENSE("GPL");
--
2.54.0.dirty
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v3] perf/arm_cspmu: Add Arm system PMU
2026-10-05 14:11 [PATCH v3] perf/arm_cspmu: Add Arm system PMU Robin Murphy
@ 2026-10-05 14:24 ` sashiko-bot
2026-10-08 4:47 ` Ilkka Koskinen
1 sibling, 0 replies; 3+ messages in thread
From: sashiko-bot @ 2026-10-05 14:24 UTC (permalink / raw)
To: Robin Murphy; +Cc: linux-perf-users
> Arm's latest Compute Subsystems and SoCs are using a common PMU block
> in various places which can mostly just be driven as a generic 64-bit
> CoreSight PMU, but does have an IMP-DEF register for additional
> filtering. The details of event and filter encodings depend on the
> particular PMU instance, so are left to the higher level Arm Telemetry
> Solution tooling.
>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Sashiko has reviewed this patch and found no issues. It looks great!
--
Sashiko AI review · https://sashiko.dev/#/patchset/222d98feab5ca2836fdef69fee9113f6f860167d.1791209460.git.robin.murphy@arm.com?part=1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v3] perf/arm_cspmu: Add Arm system PMU
2026-10-05 14:11 [PATCH v3] perf/arm_cspmu: Add Arm system PMU Robin Murphy
2026-10-05 14:24 ` sashiko-bot
@ 2026-10-08 4:47 ` Ilkka Koskinen
1 sibling, 0 replies; 3+ messages in thread
From: Ilkka Koskinen @ 2026-10-08 4:47 UTC (permalink / raw)
To: Robin Murphy; +Cc: will, mark.rutland, linux-perf-users, linux-arm-kernel
On Mon, 5 Oct 2026, Robin Murphy wrote:
> Arm's latest Compute Subsystems and SoCs are using a common PMU block
> in various places which can mostly just be driven as a generic 64-bit
> CoreSight PMU, but does have an IMP-DEF register for additional
> filtering. The details of event and filter encodings depend on the
> particular PMU instance, so are left to the higher level Arm Telemetry
> Solution tooling.
>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Looks good to me,
Reviewed-by: Ilkka Koskinen <ilkka@os.amperecomputing.com>
> ---
>
> v3: Fix 32-bit COMPILE_TEST to match arm_cspmu.c
>
> drivers/perf/arm_cspmu/Kconfig | 7 +++
> drivers/perf/arm_cspmu/Makefile | 1 +
> drivers/perf/arm_cspmu/arm_cspmu.c | 7 +++
> drivers/perf/arm_cspmu/arm_cspmu.h | 1 +
> drivers/perf/arm_cspmu/arm_syspmu.c | 67 +++++++++++++++++++++++++++++
> 5 files changed, 83 insertions(+)
> create mode 100644 drivers/perf/arm_cspmu/arm_syspmu.c
>
> diff --git a/drivers/perf/arm_cspmu/Kconfig b/drivers/perf/arm_cspmu/Kconfig
> index 6f4e28fc84a2..25bd55f036a4 100644
> --- a/drivers/perf/arm_cspmu/Kconfig
> +++ b/drivers/perf/arm_cspmu/Kconfig
> @@ -27,3 +27,10 @@ config AMPERE_CORESIGHT_PMU_ARCH_SYSTEM_PMU
>
> In the first phase, the driver enables support on MCU PMU used in
> AmpereOne SoC family.
> +
> +config ARM_SYSTEM_PMU
> + tristate "Arm System PMU"
> + depends on ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU
> + help
> + Support additional event filtering attributes for the CoreSight-based
> + PMU blocks found in various parts of Arm Compute Subsystems and SoCs.
> diff --git a/drivers/perf/arm_cspmu/Makefile b/drivers/perf/arm_cspmu/Makefile
> index 220a734efd54..90c3cd710157 100644
> --- a/drivers/perf/arm_cspmu/Makefile
> +++ b/drivers/perf/arm_cspmu/Makefile
> @@ -8,3 +8,4 @@ arm_cspmu_module-y := arm_cspmu.o
>
> obj-$(CONFIG_NVIDIA_CORESIGHT_PMU_ARCH_SYSTEM_PMU) += nvidia_cspmu.o
> obj-$(CONFIG_AMPERE_CORESIGHT_PMU_ARCH_SYSTEM_PMU) += ampere_cspmu.o
> +obj-$(CONFIG_ARM_SYSTEM_PMU) += arm_syspmu.o
> diff --git a/drivers/perf/arm_cspmu/arm_cspmu.c b/drivers/perf/arm_cspmu/arm_cspmu.c
> index 912f03ce3ef5..9f298ea1a974 100644
> --- a/drivers/perf/arm_cspmu/arm_cspmu.c
> +++ b/drivers/perf/arm_cspmu/arm_cspmu.c
> @@ -358,6 +358,13 @@ static struct arm_cspmu_impl_match impl_match[] = {
> .module = NULL,
> .impl_init_ops = NULL,
> },
> + {
> + .module_name = "arm_syspmu",
> + .pmiidr_val = ARM_CSPMU_IMPL_ID_ARM,
> + .pmiidr_mask = PMIIDR_IMPLEMENTER,
> + .module = NULL,
> + .impl_init_ops = NULL,
> + },
> {
> .module_name = "ampere_cspmu",
> .pmiidr_val = ARM_CSPMU_IMPL_ID_AMPERE,
> diff --git a/drivers/perf/arm_cspmu/arm_cspmu.h b/drivers/perf/arm_cspmu/arm_cspmu.h
> index c4058d602477..03e34692a965 100644
> --- a/drivers/perf/arm_cspmu/arm_cspmu.h
> +++ b/drivers/perf/arm_cspmu/arm_cspmu.h
> @@ -149,6 +149,7 @@
>
> /* JEDEC-assigned JEP106 identification code */
> #define ARM_CSPMU_IMPL_ID_NVIDIA 0x36B
> +#define ARM_CSPMU_IMPL_ID_ARM 0x43B
> #define ARM_CSPMU_IMPL_ID_AMPERE 0xA16
>
> /* PMDEVARCH */
> diff --git a/drivers/perf/arm_cspmu/arm_syspmu.c b/drivers/perf/arm_cspmu/arm_syspmu.c
> new file mode 100644
> index 000000000000..2f5ceda5c4d1
> --- /dev/null
> +++ b/drivers/perf/arm_cspmu/arm_syspmu.c
> @@ -0,0 +1,67 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +#include <linux/io-64-nonatomic-lo-hi.h>
> +#include <linux/module.h>
> +
> +#include "arm_cspmu.h"
> +
> +#define PMEVFILT3R 0x200
> +
> +static struct attribute *arm_syspmu_format_attrs[] = {
> + ARM_CSPMU_FORMAT_EVENT_ATTR,
> + ARM_CSPMU_FORMAT_FILTER_ATTR,
> + ARM_CSPMU_FORMAT_FILTER2_ATTR,
> + ARM_CSPMU_FORMAT_ATTR(filter3, "config3:0-63"),
> + NULL,
> +};
> +
> +static struct attribute **arm_syspmu_get_format_attrs(const struct arm_cspmu *cspmu)
> +{
> + return devm_kmemdup(cspmu->dev, arm_syspmu_format_attrs,
> + sizeof(arm_syspmu_format_attrs), GFP_KERNEL);
> +}
> +
> +static void arm_syspmu_set_ev_filter(struct arm_cspmu *cspmu,
> + const struct perf_event *event)
> +{
> + u32 offset = 8 * event->hw.idx;
> +
> + writeq(event->attr.config1, cspmu->base0 + PMEVFILTR + offset);
> + writeq(event->attr.config2, cspmu->base0 + PMEVFILT2R + offset);
> + writeq(event->attr.config3, cspmu->base0 + PMEVFILT3R + offset);
> +}
> +
> +static int arm_syspmu_init_ops(struct arm_cspmu *cspmu)
> +{
> + switch (FIELD_GET(PMIIDR_PRODUCTID, cspmu->impl.pmiidr)) {
> + case 0x9c3:
> + cspmu->impl.ops.set_ev_filter = arm_syspmu_set_ev_filter;
> + cspmu->impl.ops.get_format_attrs = arm_syspmu_get_format_attrs;
> + break;
> + default:
> + break;
> + }
> + return 0;
> +}
> +
> +static const struct arm_cspmu_impl_match arm_syspmu_param = {
> + .pmiidr_val = ARM_CSPMU_IMPL_ID_ARM,
> + .module = THIS_MODULE,
> + .impl_init_ops = arm_syspmu_init_ops
> +};
> +
> +static int __init arm_syspmu_init(void)
> +{
> + return arm_cspmu_impl_register(&arm_syspmu_param);
> +}
> +
> +static void __exit arm_syspmu_exit(void)
> +{
> + arm_cspmu_impl_unregister(&arm_syspmu_param);
> +}
> +
> +module_init(arm_syspmu_init);
> +module_exit(arm_syspmu_exit);
> +
> +MODULE_DESCRIPTION("Arm System PMU Driver");
> +MODULE_LICENSE("GPL");
> --
> 2.54.0.dirty
>
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2026-10-05 14:11 [PATCH v3] perf/arm_cspmu: Add Arm system PMU Robin Murphy
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