From: "Chen, Zide" <zide.chen@intel.com>
To: "Mi, Dapeng" <dapeng1.mi@linux.intel.com>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Andi Kleen <ak@linux.intel.com>,
Eranian Stephane <eranian@google.com>
Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org
Subject: Re: [PATCH 7/7] perf/x86/intel/uncore: Implement lazy setup for MSR/MMIO PMU
Date: Wed, 13 May 2026 09:47:46 -0700 [thread overview]
Message-ID: <ad31475e-e04f-4bef-91df-34215d5133a7@intel.com> (raw)
In-Reply-To: <607f0708-e437-4835-bc3d-169fe45e8320@linux.intel.com>
On 5/13/2026 2:03 AM, Mi, Dapeng wrote:
>
> On 5/13/2026 7:30 AM, Zide Chen wrote:
>> MSR and MMIO uncore PMUs are currently registered at module init time
>> and appear in sysfs even when no PMU boxes are functional.
>>
>> Apply the same lazy registration model used by PCI uncore PMUs: the
>> PMU is registered when the first box is successfully initialized, and
>> unregistered when the last box exits. If a box fails to initialize on
>> a subsequent die, the PMU is marked broken but remains registered to
>> avoid disrupting any in-flight perf events.
>>
>> Box allocation and free remain at module init/exit time to avoid
>> repeated kfree/alloc cycles across CPU offline/online events.
>>
>> Signed-off-by: Zide Chen <zide.chen@intel.com>
>> ---
>> arch/x86/events/intel/uncore.c | 72 ++++++----------------------------
>> 1 file changed, 12 insertions(+), 60 deletions(-)
>>
>> diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c
>> index 399f434e1a7d..2aaac0b49bb6 100644
>> --- a/arch/x86/events/intel/uncore.c
>> +++ b/arch/x86/events/intel/uncore.c
>> @@ -1564,8 +1564,11 @@ static void uncore_box_unref(struct intel_uncore_type **types, int die)
>> for (i = 0; i < type->num_boxes; i++, pmu++) {
>> box = pmu->boxes[die];
>> if (box && box->cpu >= 0 &&
>> - atomic_dec_return(&box->cpu_refcnt) == 0)
>> + atomic_dec_return(&box->cpu_refcnt) == 0) {
>> + if (atomic_dec_return(&pmu->die_refcnt) == 0)
>> + uncore_pmu_unregister(pmu);
>> uncore_box_exit(box);
>> + }
>> }
>> }
>> }
>> @@ -1659,7 +1662,7 @@ static int uncore_box_ref(struct intel_uncore_type **types,
>> box = pmu->boxes[die];
>> if (box && box->cpu >= 0 &&
>> atomic_inc_return(&box->cpu_refcnt) == 1)
>> - uncore_box_init(box);
>> + uncore_box_setup(pmu, box);
>> }
>> }
>> return 0;
>> @@ -1690,67 +1693,16 @@ static int uncore_event_cpu_online(unsigned int cpu)
>> return 0;
>> }
>>
>> -static int __init type_pmu_register(struct intel_uncore_type *type)
>> +static int __init uncore_cpu_mmio_init(struct intel_uncore_type **types)
>
> The name seems a little bit weird, could we name it to a more generic name?
> maybe uncore_pmu_types_init() or something similar? Thanks.
Sure, I may pick uncore_pmu_types_init().
prev parent reply other threads:[~2026-05-13 16:47 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-12 23:30 [PATCH 0/7] perf/x86/intel/uncore: PMU setup robustness fixes Zide Chen
2026-05-12 23:30 ` [PATCH 1/7] perf/x86/intel/uncore: Rename refcount fields and other cleanups Zide Chen
2026-05-13 0:26 ` Ian Rogers
2026-05-12 23:30 ` [PATCH 2/7] perf/x86/intel/uncore: Let init_box() callback report failures Zide Chen
2026-05-13 0:23 ` Ian Rogers
2026-05-12 23:30 ` [PATCH 3/7] perf/x86/intel/uncore: Keep PCI PMUs working when MMIO/MSR setup fails Zide Chen
2026-05-13 0:30 ` Ian Rogers
2026-05-12 23:30 ` [PATCH 4/7] perf/x86/intel/uncore: Factor out box setup code Zide Chen
2026-05-13 0:27 ` Ian Rogers
2026-05-12 23:30 ` [PATCH 5/7] perf/x86/intel/uncore: Introduce PMU flags and broken state Zide Chen
2026-05-13 0:28 ` Ian Rogers
2026-05-12 23:30 ` [PATCH 6/7] perf/x86/intel/uncore: Fix uncore_box ref/unref ordering on CPU hotplug Zide Chen
2026-05-13 0:32 ` Ian Rogers
2026-05-13 8:59 ` Mi, Dapeng
2026-05-13 18:43 ` Chen, Zide
2026-05-12 23:30 ` [PATCH 7/7] perf/x86/intel/uncore: Implement lazy setup for MSR/MMIO PMU Zide Chen
2026-05-13 0:34 ` Ian Rogers
2026-05-13 9:03 ` Mi, Dapeng
2026-05-13 16:47 ` Chen, Zide [this message]
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