Re: [PATCH 3/3] perf/amd/ibs: Simplify event state handling with IBS_CAPS_DIS

[Ravi Bangoria <ravi.bangoria@amd.com>]

>> +     if (ibs_caps & IBS_CAPS_DIS) {
>> +             /*
>> +              *      IBS HW                     SW
>> +              *
>> +              *  o Capture sample       o ->stop()
>> +              *  o Set VAL bit            CTL2[Dis] = 1
>> +              *  o Raise NMI --.        o ...
>> +              *                 \       o ->start()
>> +              *                  \        wrmsr(IBS_{FETCH|OP}_CTL, new value);
>> +              *                   \       (wrmsr clears the VAL bit)
>> +              *                    `--> o Receives delayed NMI
>> +              *                           (Unknown NMI since VAL bit is cleared)
>> +              *
>> +              * Handle this with induced delay.
>> +              */
>> +             rdmsrq(hwc->config_base, ctl);
>> +             while ((ctl & perf_ibs->valid_mask) && delay--) {
>> +                     udelay(1);
>> +                     rdmsrq(hwc->config_base, ctl);
>> +             }
> 
> [Severity: High]
> What happens if the delayed NMI takes longer than 50us to arrive, for
> example due to hypervisor scheduling, nested virtualization, or SMIs?
> 
> If this delay loop expires, the code proceeds to call
> perf_ibs_enable_event() which clears the VAL and CTL2[Dis] bits. When the
> delayed NMI eventually arrives, it appears it will be treated as an
> unhandled NMI.

A delay exceeding 50us is highly unlikely in practice, and even if it
occurs, the consequence is "Unknown NMI", which is not fatal.

Thanks,
Ravi