[PATCH] perf: marvell: Fix DDR PMU polling period unit

[PATCH] perf: marvell: Fix DDR PMU polling period unit

[Yingjie Wang]

The poll_period_sec parameter specifies the overflow polling interval in
seconds, but cn10k_ddr_pmu_timer_period() multiplies it by USEC_PER_SEC
before passing it to ms_to_ktime(). This makes the interval 1000 times
longer than requested: the default of 100 seconds becomes 100,000 seconds.

The driver relies on polling to handle counter overflows. Delaying those
checks can leave programmable counters frozen at their maximum value and
lose events until they are restarted.

Use MSEC_PER_SEC to convert the parameter to milliseconds for
ms_to_ktime(). This corrects both the initial timer expiry and subsequent
polling intervals.

Fixes: 35a43326a9e3 ("perf/marvell: cn10k DDR perfmon event overflow handling")
Cc: stable@vger.kernel.org
Signed-off-by: Yingjie Wang <1075151112@qq.com>
---
Built drivers/perf/marvell_cn10k_ddr_pmu.o with W=1 for ARM64 and
x86-64 (COMPILE_TEST). No Marvell hardware testing.

 drivers/perf/marvell_cn10k_ddr_pmu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/perf/marvell_cn10k_ddr_pmu.c b/drivers/perf/marvell_cn10k_ddr_pmu.c
index 9b68d6c1c31cd..31641a21e3792 100644
--- a/drivers/perf/marvell_cn10k_ddr_pmu.c
+++ b/drivers/perf/marvell_cn10k_ddr_pmu.c
@@ -516,7 +516,7 @@ module_param_named(poll_period_sec, cn10k_ddr_pmu_poll_period_sec, ulong, 0644);
 
 static ktime_t cn10k_ddr_pmu_timer_period(void)
 {
-	return ms_to_ktime((u64)cn10k_ddr_pmu_poll_period_sec * USEC_PER_SEC);
+	return ms_to_ktime((u64)cn10k_ddr_pmu_poll_period_sec * MSEC_PER_SEC);
 }
 
 static int ddr_perf_get_event_bitmap(int eventid, u64 *event_bitmap,

base-commit: 652ab8ee0d27f21a5f402a0b6ac227c8bbfdd64c

Re: [PATCH] perf: marvell: Fix DDR PMU polling period unit

[sashiko-bot]

> The poll_period_sec parameter specifies the overflow polling interval in
> seconds, but cn10k_ddr_pmu_timer_period() multiplies it by USEC_PER_SEC
> before passing it to ms_to_ktime(). This makes the interval 1000 times
> longer than requested: the default of 100 seconds becomes 100,000 seconds.
> 
> The driver relies on polling to handle counter overflows. Delaying those
> checks can leave programmable counters frozen at their maximum value and
> lose events until they are restarted.
> 
> Use MSEC_PER_SEC to convert the parameter to milliseconds for
> ms_to_ktime(). This corrects both the initial timer expiry and subsequent
> polling intervals.
> 
> Fixes: 35a43326a9e3 ("perf/marvell: cn10k DDR perfmon event overflow handling")
> Cc: stable@vger.kernel.org
> Signed-off-by: Yingjie Wang <1075151112@qq.com>

Sashiko has reviewed this patch and found no issues.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/tencent_592E3D2D89322E934E28FE593E67826AAC09@qq.com?part=1

RE: [EXTERNAL] [PATCH] perf: marvell: Fix DDR PMU polling period unit

[Geethasowjanya Akula]

>-----Original Message-----
>From: Yingjie Wang <1075151112@qq.com>
>Sent: Tuesday, October 27, 2026 8:53 AM
>To: will@kernel.org; mark.rutland@arm.com
>Cc: linux-arm-kernel@lists.infradead.org; linux-perf-users@vger.kernel.org;
>linux-kernel@vger.kernel.org; Bharat Bhushan <bbhushan2@marvell.com>;
>Geethasowjanya Akula <gakula@marvell.com>; Gowthami Thiagarajan
><gthiagarajan@marvell.com>; stable@vger.kernel.org
>Subject: [EXTERNAL] [PATCH] perf: marvell: Fix DDR PMU polling period unit
>
>The poll_period_sec parameter specifies the overflow polling interval in
>seconds, but cn10k_ddr_pmu_timer_period() multiplies it by USEC_PER_SEC
>before passing it to ms_to_ktime(). This makes the interval 1000 times longer
>than requested: the default of 100 seconds becomes 100,000 seconds.
>
>The driver relies on polling to handle counter overflows. Delaying those checks
>can leave programmable counters frozen at their maximum value and lose
>events until they are restarted.
>
>Use MSEC_PER_SEC to convert the parameter to milliseconds for
>ms_to_ktime(). This corrects both the initial timer expiry and subsequent
>polling intervals.
>
>Fixes: 35a43326a9e3 ("perf/marvell: cn10k DDR perfmon event overflow
>handling")
>Cc: stable@vger.kernel.org
>Signed-off-by: Yingjie Wang <1075151112@qq.com>
>---
>Built drivers/perf/marvell_cn10k_ddr_pmu.o with W=1 for ARM64 and
>x86-64 (COMPILE_TEST). No Marvell hardware testing.
>
> drivers/perf/marvell_cn10k_ddr_pmu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>diff --git a/drivers/perf/marvell_cn10k_ddr_pmu.c
>b/drivers/perf/marvell_cn10k_ddr_pmu.c
>index 9b68d6c1c31cd..31641a21e3792 100644
>--- a/drivers/perf/marvell_cn10k_ddr_pmu.c
>+++ b/drivers/perf/marvell_cn10k_ddr_pmu.c
>@@ -516,7 +516,7 @@ module_param_named(poll_period_sec,
>cn10k_ddr_pmu_poll_period_sec, ulong, 0644);
>
> static ktime_t cn10k_ddr_pmu_timer_period(void)  {
>-	return ms_to_ktime((u64)cn10k_ddr_pmu_poll_period_sec *
>USEC_PER_SEC);
>+	return ms_to_ktime((u64)cn10k_ddr_pmu_poll_period_sec *
>MSEC_PER_SEC);
> }
>
> static int ddr_perf_get_event_bitmap(int eventid, u64 *event_bitmap,
>
>base-commit: 652ab8ee0d27f21a5f402a0b6ac227c8bbfdd64c

Thanks for the pacth.
Reviewed-by: Geetha sowjanya <gakula@marvell.com>