Re: [Patch v5 01/18] perf/x86: Disable LBR if x86_pmu.lbr_nr exceeds MAX_LBR_ENTRIES

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] perf/x86/intel: incomplete Arch LBR disablement in intel_pmu_init()
- [Medium] perf/x86/amd: amd_pmu_lbr_init() returns 0 when LBR is disabled
--

commit 03c28823478ca7f089145cd93c93be2824eab310
Author: Dapeng Mi <dapeng1.mi@linux.intel.com>

perf/x86: Disable LBR if x86_pmu.lbr_nr exceeds MAX_LBR_ENTRIES

This commit adds a sanity check on x86_pmu.lbr_nr during AMD and Intel PMU
initialization to disable LBR if the hardware reports more entries than
MAX_LBR_ENTRIES.

> diff --git a/arch/x86/events/amd/lbr.c b/arch/x86/events/amd/lbr.c
> index a55646fcb8465..96c5b5e56053b 100644
> --- a/arch/x86/events/amd/lbr.c
> +++ b/arch/x86/events/amd/lbr.c
> @@ -433,7 +433,13 @@ __init int amd_pmu_lbr_init(void)
>  	ebx.full = cpuid_ebx(EXT_PERFMON_DEBUG_FEATURES);
>  	x86_pmu.lbr_nr = ebx.split.lbr_v2_stack_sz;
>  
> -	pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr);
> +	if (x86_pmu.lbr_nr > MAX_LBR_ENTRIES) {
> +		pr_warn("LBR entries %d exceeds max %d, disable LBR.\n",
> +			x86_pmu.lbr_nr, MAX_LBR_ENTRIES);
> +		x86_pmu.lbr_nr = 0;
> +	} else {
> +		pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr);
> +	}
>  
>  	return 0;
>  }

[Severity: Medium]
Should amd_pmu_lbr_init() return an error code such as -EOPNOTSUPP when
x86_pmu.lbr_nr exceeds MAX_LBR_ENTRIES?

Because amd_pmu_lbr_init() still returns 0 after setting x86_pmu.lbr_nr = 0,
its caller in arch/x86/events/amd/core.c treats LBR initialization as
successful and installs the LBR callbacks:

arch/x86/events/amd/core.c:amd_core_pmu_init() {
	...
	/* LBR and BRS are mutually exclusive features */
	if (!amd_pmu_lbr_init()) {
		/* LBR requires flushing on context switch */
		x86_pmu.sched_task = amd_pmu_lbr_sched_task;
		static_call_update(amd_pmu_branch_hw_config, amd_pmu_lbr_hw_config);
		static_call_update(amd_pmu_branch_reset, amd_pmu_lbr_reset);
		static_call_update(amd_pmu_branch_add, amd_pmu_lbr_add);
		static_call_update(amd_pmu_branch_del, amd_pmu_lbr_del);

		/* Only support branch_stack snapshot on perfmon v2 */
		if (x86_pmu.handle_irq == amd_pmu_v2_handle_irq)
			static_call_update(perf_snapshot_branch_stack, amd_pmu_v2_snapshot_branch_stack);
	}
	...
}

If perf_snapshot_branch_stack is later invoked (for example via
bpf_get_branch_snapshot()), amd_pmu_v2_snapshot_branch_stack() runs without
checking x86_pmu.lbr_nr and touches MSR_AMD64_PERF_CNTR_GLOBAL_CTL,
MSR_AMD_DBG_EXTN_CFG, and MSR_IA32_DEBUGCTLMSR:

arch/x86/events/amd/core.c:amd_pmu_v2_snapshot_branch_stack() {
	...
	local_irq_save(flags);
	amd_pmu_core_disable_all();
	__amd_pmu_lbr_disable();

	cpuc = this_cpu_ptr(&cpu_hw_events);

	amd_pmu_lbr_read();
	cnt = min(cnt, x86_pmu.lbr_nr);
	memcpy(entries, cpuc->lbr_entries, sizeof(struct perf_branch_entry) * cnt);

	amd_pmu_v2_enable_all(0);
	local_irq_restore(flags);
	...
}

> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index 0a34d674df590..10c694db85ea3 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -9023,6 +9023,13 @@ __init int intel_pmu_init(void)
>  	 */
>  	if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL))
>  		x86_pmu.lbr_nr = 0;
> +
> +	if (x86_pmu.lbr_nr > MAX_LBR_ENTRIES) {
> +		pr_warn("LBR entries %d exceeds max %d, disable LBR.\n",
> +			x86_pmu.lbr_nr, MAX_LBR_ENTRIES);
> +		x86_pmu.lbr_nr = 0;
> +	}

[Severity: Medium]
When X86_FEATURE_ARCH_LBR is enabled and CPUID leaf 28 enumerates a depth
greater than MAX_LBR_ENTRIES, does zeroing x86_pmu.lbr_nr here leave
Architectural LBR partially initialized and leak x86_pmu.task_ctx_cache and
per-CPU cpuc->lbr_xsave buffers?

In intel_pmu_init(), intel_pmu_arch_lbr_init() and
intel_pmu_check_event_constraints_all() are called before this check:

arch/x86/events/intel/core.c:intel_pmu_init() {
	...
	if (boot_cpu_has(X86_FEATURE_ARCH_LBR))
		intel_pmu_arch_lbr_init();

	intel_pmu_check_event_constraints_all(NULL);
	...
}

Inside arch/x86/events/intel/lbr.c:intel_pmu_arch_lbr_init(), lbr_nr is
computed as fls(eax.split.lbr_depth_mask) * 8. Because it does not bail out to
clear_arch_lbr when lbr_nr > MAX_LBR_ENTRIES, it already:

- writes lbr_nr to MSR_ARCH_LBR_DEPTH
- allocates x86_pmu.task_ctx_cache
- enables the x86_lbr_mispred, x86_lbr_cycles, and x86_lbr_type static
  branches
- sets x86_pmu.lbr_ctl_map (which keeps x86_pmu_has_lbr_callstack() true)
- sets PMU_FL_BR_CNTR and PMU_FL_DYN_CONSTRAINT in x86_pmu.flags
- leaves X86_FEATURE_ARCH_LBR set

As a result, when any hardware perf event is later opened,
reserve_lbr_buffers() still allocates cpuc->lbr_xsave across all possible CPUs
from task_ctx_cache:

arch/x86/events/intel/lbr.c:reserve_lbr_buffers() {
	...
	if (!cpu_feature_enabled(X86_FEATURE_ARCH_LBR))
		return;

	for_each_possible_cpu(cpu) {
		cpuc = per_cpu_ptr(&cpu_hw_events, cpu);
		kmem_cache = x86_get_pmu(cpu)->task_ctx_cache;
		if (!kmem_cache || cpuc->lbr_xsave)
			continue;

		cpuc->lbr_xsave = kmem_cache_alloc_node(kmem_cache,
							GFP_KERNEL | __GFP_ZERO,
							cpu_to_node(cpu));
	}
}

In addition, lbr_is_visible() in arch/x86/events/intel/core.c still exposes
branch_counter_nr and branch_counter_width in sysfs because PMU_FL_BR_CNTR
remains set, and attach_perf_ctx_data() can still allocate task->perf_ctx_data
for events with PERF_SAMPLE_READ and PERF_SAMPLE_BRANCH_CALL_STACK.

Should intel_pmu_arch_lbr_init() check lbr_nr > MAX_LBR_ENTRIES before writing
MSR_ARCH_LBR_DEPTH and jump to clear_arch_lbr so X86_FEATURE_ARCH_LBR is
cleared cleanly?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261029043914.1395147-1-dapeng1.mi@linux.intel.com?part=1