[PATCH 0/2] perf jevents: Add IOMMU PTW & device entry metrics

[PATCH 0/2] perf jevents: Add IOMMU PTW & device entry metrics

[Jacob Lefkowitz via B4 Relay]

Adds AMD specific metrics for the IOMMU with respect to page table
walks and device table entires. The metrics cover ratios, rates, and
percentages with respect to any event which might be triggered during
a page table walk or device table entry lookup.

The metrics target Zen 2+ processors and use the standard amd_iommu
PMU events. They have been tested with a benchmark C program that
purposefully thrashed the TLB as well as with 'sleep 10'; both of
which work as expected.

The changes are split into two patches:
1. perf jevents: add iommu page table walk metrics
2. perf jevents: add amd specific device table entry metrics

The specific metris added are:
- lpm_iommu_dte_miss_rate
- lpm_iommu_dte_lookups
- lpm_iommu_ptw_reads_per_tlb_miss
- lpm_iommu_ptw_nested_read_ratio
- lpm_iommu_ptw_guest_read_ratio
- lpm_iommu_trans_per_sec

Signed-off-by: Jacob Lefkowitz <jlefkowi@akamai.com>
---
Jacob Lefkowitz (2):
      perf jevents: add iommu page table walk metrics
      perf jevents: add amd specific device table entry metrics

 tools/perf/pmu-events/amd_metrics.py | 81 +++++++++++++++++++++++++++++++++++-
 1 file changed, 80 insertions(+), 1 deletion(-)
---
base-commit: 1c90f0a3c8a1c4e38f9edd97af9e20848805a7fb
change-id: 20261028-perf-tools-next-8fd1d433316a

Best regards,
-- 
Jacob Lefkowitz <jlefkowi@akamai.com>

[PATCH 1/2] perf jevents: add iommu page table walk metrics

[Jacob Lefkowitz via B4 Relay]

From: Jacob Lefkowitz <jlefkowi@akamai.com>

Adds page table walk metrics specfically to perf jevents for AMD
platforms to enhance observability into IOMMU overhead. The metrics
are supported on Zen 2 and neweer processors. They are implemented
using the amd_iommu PMU events.

The list of metrics added here are:
- lpm_iommu_ptw_reads_per_tlb_miss
- lpm_iommu_ptw_nested_read_ratio
- lpm_iommu_ptw_guest_read_ratio
- lpm_iommu_trans_per_sec

The changes here have been tested with 'sleep 10' as the workload:

perf stat -M iommuptw --per-socket --metric-only -j -a -- sleep 10
{"socket" : "S0", "counters" : 8,
"reads/tlb_miss lpm_iommu_ptw_reads_per_tlb_miss" : "0.5",
"%  lpm_iommu_ptw_nested_read_ratio" : "100.0",
"%  lpm_iommu_ptw_guest_read_ratio" : "0.0",
"trans/s  lpm_iommu_trans_per_sec" : "971.5"}
{"socket" : "S1", "counters" : 0,
"reads/tlb_miss  lpm_iommu_ptw_reads_per_tlb_miss" : "none",
"%  lpm_iommu_ptw_nested_read_ratio" : "100.0",
"%  lpm_iommu_ptw_guest_read_ratio" : "100.0",
"trans/s  lpm_iommu_trans_per_sec" : "none"}

Signed-off-by: Jacob Lefkowitz <jlefkowi@akamai.com>
---
 tools/perf/pmu-events/amd_metrics.py | 49 +++++++++++++++++++++++++++++++++++-
 1 file changed, 48 insertions(+), 1 deletion(-)

diff --git a/tools/perf/pmu-events/amd_metrics.py b/tools/perf/pmu-events/amd_metrics.py
index 42569b9153f4..dcffd6e268fa 100755
--- a/tools/perf/pmu-events/amd_metrics.py
+++ b/tools/perf/pmu-events/amd_metrics.py
@@ -5,7 +5,7 @@ import math
 import os
 from typing import Optional, Union
 from common_metrics import Cycles
-from metric import (d_ratio, has_event, max, Event, JsonEncodeMetric,
+from metric import (d_ratio, has_event, max, min, Event, JsonEncodeMetric,
                     JsonEncodeMetricGroupDescriptions, Literal, LoadEvents,
                     Metric, MetricGroup, Select)
 
@@ -318,6 +318,52 @@ def AmdIotlb() -> Optional[MetricGroup]:
     )
 
 
+def AmdIommuptw() -> Optional[MetricGroup]:
+    global _zen_model
+
+    if _zen_model < 2:
+        return None
+
+    walks = Event("amd_iommu/mem_iommu_tlb_pte_mis/") + Event(
+        "amd_iommu/mem_iommu_tlb_pde_mis/"
+    )
+    pt_rd = Event("amd_iommu/page_tbl_read_tot/")
+    pt_rd_nst = Event("amd_iommu/page_tbl_read_nst/")
+    pt_rd_gst = Event("amd_iommu/page_tbl_read_gst/")
+    trans = Event("amd_iommu/mem_trans_total/")
+
+    return MetricGroup(
+        "iommuptw",
+        [
+            Metric(
+                "lpm_iommu_ptw_reads_per_tlb_miss",
+                "Average IOMMU page table reads per IOTLB miss",
+                d_ratio(pt_rd, walks),
+                "reads/tlb_miss"
+            ),
+            Metric(
+                "lpm_iommu_ptw_nested_read_ratio",
+                "Share of IOMMU page table reads from nested (host) tables", # 0 without nested translation
+                min(d_ratio(pt_rd_nst, pt_rd), 1),
+                "100%"
+            ),
+            Metric(
+                "lpm_iommu_ptw_guest_read_ratio",
+                "Share of IOMMU page table reads from guest tables", # 0 without nested translation
+                min(d_ratio(pt_rd_gst, pt_rd), 1),
+                "100%"
+            ),
+            Metric(
+                "lpm_iommu_trans_per_sec",
+                "IOMMU translation requests per second",
+                d_ratio(trans, interval_sec),
+                "trans/s"
+            )
+        ],
+        description="IOMMU page table walk metrics"
+    )
+
+
 def AmdItlb():
     l2h = Event("bp_l1_tlb_miss_l2_tlb_hit", "bp_l1_tlb_miss_l2_hit")
     l2m = Event("bp_l1_tlb_miss_l2_tlb_miss.all", "l2_itlb_misses",)
@@ -526,6 +572,7 @@ def main() -> None:
         AmdCtxSw(),
         AmdDtlb(),
         AmdIotlb(),
+        AmdIommuptw(),
         AmdItlb(),
         AmdLdSt(),
         AmdUpc(),

-- 
2.53.0

Re: [PATCH 1/2] perf jevents: add iommu page table walk metrics

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] perf jevents: unnecessary global in AmdIommuptw() breaks pylint W0602 build
- [Medium] perf jevents: min() in AmdIommuptw() turns NaN into 100% on uncounted sockets
--

commit 421e4310ee31d5eae1bdf50f6ef3739f62cf56c1
Author: Jacob Lefkowitz <jlefkowi@akamai.com>

perf jevents: add iommu page table walk metrics

This commit adds an iommuptw metric group to tools/perf/pmu-events/amd_metrics.py
for Zen 2 and newer AMD processors using amd_iommu PMU events.

> diff --git a/tools/perf/pmu-events/amd_metrics.py b/tools/perf/pmu-events/amd_metrics.py
> index 42569b9153f45..dcffd6e268fad 100755
> --- a/tools/perf/pmu-events/amd_metrics.py
> +++ b/tools/perf/pmu-events/amd_metrics.py

[ ... ]

> @@ -318,6 +318,52 @@ def AmdIotlb() -> Optional[MetricGroup]:
>      )
>  
>  
> +def AmdIommuptw() -> Optional[MetricGroup]:
> +    global _zen_model
> +
> +    if _zen_model < 2:
> +        return None

[Severity: Medium]
Does declaring global _zen_model in AmdIommuptw() break the perf build when
pylint (>= 2.16.0) is installed on the host?

In tools/perf/Makefile.perf, pylint is enabled by default when present:

    override PYLINT := PYTHONPATH=$(srctree)/tools/perf/python:$(srctree)/tools/perf/pmu-events \
      $(PYLINT) --disable=all --enable=E,W --disable=W0123,W0311,W0511,W0603,W0622,W0718 \
      --ignored-modules=perf,textual,setproctitle

And tools/perf/pmu-events/Build fails the build if pylint returns non-zero:

    $(OUTPUT)%.pylint_log: %
    	$(call rule_mkdir)
    	$(Q)$(call echo-cmd,test)$(PYLINT) "$<" > $@ || (cat $@ && rm $@ && false)

Because AmdIommuptw() only reads _zen_model and never assigns to it, pylint
emits W0602 (global-variable-not-assigned), which is not in the disabled list.
Other functions in tools/perf/pmu-events/amd_metrics.py such as AmdDtlb(),
AmdIotlb(), and AmdItlb() had global _zen_model removed in commit db5a60750133
("perf pmu-events: Clean up mypy and pylint issues") to avoid this warning.
Should global _zen_model be omitted here as well?

> +
> +    walks = Event("amd_iommu/mem_iommu_tlb_pte_mis/") + Event(
> +        "amd_iommu/mem_iommu_tlb_pde_mis/"
> +    )
> +    pt_rd = Event("amd_iommu/page_tbl_read_tot/")
> +    pt_rd_nst = Event("amd_iommu/page_tbl_read_nst/")
> +    pt_rd_gst = Event("amd_iommu/page_tbl_read_gst/")
> +    trans = Event("amd_iommu/mem_trans_total/")
> +
> +    return MetricGroup(
> +        "iommuptw",
> +        [
> +            Metric(
> +                "lpm_iommu_ptw_reads_per_tlb_miss",
> +                "Average IOMMU page table reads per IOTLB miss",
> +                d_ratio(pt_rd, walks),
> +                "reads/tlb_miss"
> +            ),
> +            Metric(
> +                "lpm_iommu_ptw_nested_read_ratio",
> +                "Share of IOMMU page table reads from nested (host) tables", # 0 without nested translation
> +                min(d_ratio(pt_rd_nst, pt_rd), 1),
> +                "100%"
> +            ),
> +            Metric(
> +                "lpm_iommu_ptw_guest_read_ratio",
> +                "Share of IOMMU page table reads from guest tables", # 0 without nested translation
> +                min(d_ratio(pt_rd_gst, pt_rd), 1),
> +                "100%"
> +            ),

[Severity: Medium]
Why do lpm_iommu_ptw_nested_read_ratio and lpm_iommu_ptw_guest_read_ratio both
evaluate to 100.0% on Socket S1 in the commit message example where 0 counters
ran?

The amd_iommu PMU driver registers its cpumask on CPU 0 only, so under
--per-socket aggregation, sockets without CPU 0 have aggr->counts.run == 0.
In tools/perf/util/stat-shadow.c:prepare_metric(), uncounted events are
assigned NAN:

    if (aggr->counts.run == 0) {
    	val = NAN;
    	source_count = 0;
    	aggr_nr = 0;
    }

While d_ratio(pt_rd_nst, pt_rd) and d_ratio(pt_rd_gst, pt_rd) evaluate to NAN,
wrapping them in min(..., 1) hits the MIN rule in tools/perf/util/expr.y:

    | MIN '(' expr ',' expr ')'
    {
    	if (!compute_ids) {
    		$$.val = $3.val < $5.val ? $3.val : $5.val;
    		$$.ids = NULL;
    	} else {
    		$$ = union_expr($3, $5);
    	}
    }

Because NAN < 1.0 is false in IEEE 754 floating-point arithmetic, min(NAN, 1)
returns 1.0 (100.0%) instead of propagating NAN ("none") like the other two
metrics in AmdIommuptw() do. Could min(..., 1) be dropped or replaced with a
construct that preserves NAN when the events were not counted?

Also, on lpm_iommu_ptw_nested_read_ratio, is the comment "# 0 without nested
translation" inverted? Without nested (guest) translation, all IOMMU page
table reads come from the host page tables (page_tbl_read_nst), which matches
the 100.0% value shown on Socket S0 in the commit message.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261029-perf-tools-next-v1-0-a75a2b64a15e@akamai.com?part=1

[PATCH 2/2] perf jevents: add amd specific device table entry metrics

[Jacob Lefkowitz via B4 Relay]

From: Jacob Lefkowitz <jlefkowi@akamai.com>

Adds AMD specific device table entry metrics to perf jevents.
These metrics are only allowed on Zen 2+ processors and are
implemented using the 'amd_iommu' PMU events.

The list of metrics added are:
- lpm_iommu_dte_miss_rate
- lpm_iommu_dte_lookups

The metrics were tested with the standard 'sleep' workload:

perf stat -M iommudte --per-socket --metric-only -j -a -- sleep 10
{"socket" : "S0", "counters" : 8,
"lookups/s  lpm_iommu_dte_lookups" : "4117.3",
"%  lpm_iommu_dte_miss_rate" : "0.0"}
{"socket" : "S1", "counters" : 0,
"lookups/s  lpm_iommu_dte_lookups" : "none",
"%  lpm_iommu_dte_miss_rate" : "100.0"}

Signed-off-by: Jacob Lefkowitz <jlefkowi@akamai.com>
---
 tools/perf/pmu-events/amd_metrics.py | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/tools/perf/pmu-events/amd_metrics.py b/tools/perf/pmu-events/amd_metrics.py
index dcffd6e268fa..912bceb57d67 100755
--- a/tools/perf/pmu-events/amd_metrics.py
+++ b/tools/perf/pmu-events/amd_metrics.py
@@ -318,6 +318,37 @@ def AmdIotlb() -> Optional[MetricGroup]:
     )
 
 
+def AmdIommudte() -> Optional[MetricGroup]:
+    global _zen_model
+
+    if _zen_model < 2:
+        return None
+
+    dte_hit = Event("amd_iommu/mem_dte_hit/")
+    dte_mis = Event("amd_iommu/mem_dte_mis/")
+    lookups = dte_hit + dte_mis
+
+    return MetricGroup(
+        "iommudte",
+        [
+            Metric(
+                "lpm_iommu_dte_miss_rate",
+                "IOMMU device table cache miss rate",
+                min(d_ratio(dte_mis, lookups), 1),
+                "100%"
+            ),
+            Metric(
+                "lpm_iommu_dte_lookups",
+                "IOMMU device table cache miss rate",
+                d_ratio(lookups, interval_sec),
+                "lookups/s"
+            )
+        ],
+        description="IOMMU Device Table Cache Metrics"
+    )
+
+
+
 def AmdIommuptw() -> Optional[MetricGroup]:
     global _zen_model
 
@@ -572,6 +603,7 @@ def main() -> None:
         AmdCtxSw(),
         AmdDtlb(),
         AmdIotlb(),
+        AmdIommudte(),
         AmdIommuptw(),
         AmdItlb(),
         AmdLdSt(),

-- 
2.53.0

Re: [PATCH 2/2] perf jevents: add amd specific device table entry metrics

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] perf jevents: min() in AmdIommudte() and AmdIommuptw() turns NaN into 100%
- [Low] perf jevents: wrong description for lpm_iommu_dte_lookups in AmdIommudte()
--

commit da475f803a7d9ff1e625186fc6cc682762bf1c80
Author: Jacob Lefkowitz <jlefkowi@akamai.com>

perf jevents: add amd specific device table entry metrics

This commit adds the iommudte metric group (lpm_iommu_dte_miss_rate and
lpm_iommu_dte_lookups) for AMD Zen 2+ processors using amd_iommu PMU events.

> diff --git a/tools/perf/pmu-events/amd_metrics.py b/tools/perf/pmu-events/amd_metrics.py
> index dcffd6e268fad..912bceb57d67b 100755
> --- a/tools/perf/pmu-events/amd_metrics.py
> +++ b/tools/perf/pmu-events/amd_metrics.py
> @@ -318,6 +318,37 @@ def AmdIotlb() -> Optional[MetricGroup]:
>      )
>  
>  
> +def AmdIommudte() -> Optional[MetricGroup]:
> +    global _zen_model
> +
> +    if _zen_model < 2:
> +        return None
> +
> +    dte_hit = Event("amd_iommu/mem_dte_hit/")
> +    dte_mis = Event("amd_iommu/mem_dte_mis/")
> +    lookups = dte_hit + dte_mis
> +
> +    return MetricGroup(
> +        "iommudte",
> +        [
> +            Metric(
> +                "lpm_iommu_dte_miss_rate",
> +                "IOMMU device table cache miss rate",
> +                min(d_ratio(dte_mis, lookups), 1),
> +                "100%"
> +            ),

[Severity: Medium]
In AmdIommudte(), does wrapping d_ratio(dte_mis, lookups) in min(..., 1)
cause lpm_iommu_dte_miss_rate to report 100.0% instead of "none" on sockets
where no amd_iommu counters are scheduled?

Because the amd_iommu PMU exposes a cpumask containing only CPU 0, running
perf stat with --per-socket schedules 0 counters on other sockets (such as
S1 in the commit message's test output), causing dte_hit, dte_mis, and
d_ratio(dte_mis, lookups) to evaluate to NAN.

In tools/perf/util/expr.y, MIN evaluates:

    | MIN '(' expr ',' expr ')'
    {
            if (!compute_ids) {
                    $$.val = $3.val < $5.val ? $3.val : $5.val;
                    $$.ids = NULL;
            } else {
                    $$ = union_expr($3, $5);
            }
    }

Since NAN < 1 is false in IEEE 754 floating-point arithmetic, min(NAN, 1)
returns 1.0 (100.0%) instead of propagating NAN, as seen in the commit
message's output for S1:

    {"socket" : "S1", "counters" : 0,
    "lookups/s  lpm_iommu_dte_lookups" : "none",
    "%  lpm_iommu_dte_miss_rate" : "100.0"}

Since lookups is dte_hit + dte_mis, d_ratio(dte_mis, lookups) cannot exceed
1.0 for valid counter readings. Should lpm_iommu_dte_miss_rate in
AmdIommudte() (as well as lpm_iommu_ptw_nested_read_ratio and
lpm_iommu_ptw_guest_read_ratio in AmdIommuptw()) use d_ratio() directly
without min(..., 1), matching AmdIotlb()?

> +            Metric(
> +                "lpm_iommu_dte_lookups",
> +                "IOMMU device table cache miss rate",
> +                d_ratio(lookups, interval_sec),
> +                "lookups/s"
> +            )

[Severity: Low]
In AmdIommudte(), is the description for lpm_iommu_dte_lookups copy-pasted
from lpm_iommu_dte_miss_rate? It currently says "IOMMU device table cache
miss rate" instead of describing IOMMU device table cache lookups.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261029-perf-tools-next-v1-0-a75a2b64a15e@akamai.com?part=2

Re: [PATCH 0/2] perf jevents: Add IOMMU PTW & device entry metrics

[Ian Rogers]

On Thu, Oct 29, 2026 at 12:06 PM Jacob Lefkowitz via B4 Relay
<devnull+jlefkowi.akamai.com@kernel.org> wrote:
>
> Adds AMD specific metrics for the IOMMU with respect to page table
> walks and device table entires. The metrics cover ratios, rates, and
> percentages with respect to any event which might be triggered during
> a page table walk or device table entry lookup.
>
> The metrics target Zen 2+ processors and use the standard amd_iommu
> PMU events. They have been tested with a benchmark C program that
> purposefully thrashed the TLB as well as with 'sleep 10'; both of
> which work as expected.

Cool, perhaps consider contributing them as test workloads:
https://web.git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/tools/perf/tests/workloads

> The changes are split into two patches:
> 1. perf jevents: add iommu page table walk metrics
> 2. perf jevents: add amd specific device table entry metrics
>
> The specific metris added are:
> - lpm_iommu_dte_miss_rate
> - lpm_iommu_dte_lookups
> - lpm_iommu_ptw_reads_per_tlb_miss
> - lpm_iommu_ptw_nested_read_ratio
> - lpm_iommu_ptw_guest_read_ratio
> - lpm_iommu_trans_per_sec

This is great! +Ravi Bangoria who may know of errata around the PMU,
etc. There were some Sashiko nits, but I expect to add reviewed-by
once those are addressed.

Thanks,
Ian

> Signed-off-by: Jacob Lefkowitz <jlefkowi@akamai.com>
> ---
> Jacob Lefkowitz (2):
>       perf jevents: add iommu page table walk metrics
>       perf jevents: add amd specific device table entry metrics
>
>  tools/perf/pmu-events/amd_metrics.py | 81 +++++++++++++++++++++++++++++++++++-
>  1 file changed, 80 insertions(+), 1 deletion(-)
> ---
> base-commit: 1c90f0a3c8a1c4e38f9edd97af9e20848805a7fb
> change-id: 20261028-perf-tools-next-8fd1d433316a
>
> Best regards,
> --
> Jacob Lefkowitz <jlefkowi@akamai.com>
>
>