* [PATCH v2 1/8] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the QCS8300 QMP PCIe PHY Gen4 x2
2024-11-28 8:10 [PATCH v2 0/8] pci: qcom: Add QCS8300 PCIe support Ziyue Zhang
@ 2024-11-28 8:10 ` Ziyue Zhang
2024-11-28 10:17 ` Krzysztof Kozlowski
2024-11-28 8:10 ` [PATCH v2 2/8] phy: qcom-qmp-pcie: add dual lane PHY support for QCS8300 Ziyue Zhang
` (8 subsequent siblings)
9 siblings, 1 reply; 17+ messages in thread
From: Ziyue Zhang @ 2024-11-28 8:10 UTC (permalink / raw)
To: vkoul, kishon, robh+dt, manivannan.sadhasivam, bhelgaas, kw,
lpieralisi, quic_qianyu, conor+dt, neil.armstrong, andersson,
konradybcio
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas, quic_tingweiz,
quic_aiquny, kernel, linux-arm-msm, devicetree, linux-kernel,
linux-phy, Ziyue Zhang
Document the QMP PCIe PHY on the QCS8300 platform.
Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
---
.../devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
index dcf4fa55fbba..6eeeee64338e 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
@@ -16,6 +16,7 @@ description:
properties:
compatible:
enum:
+ - qcom,qcs8300-qmp-gen4x2-pcie-phy
- qcom,sa8775p-qmp-gen4x2-pcie-phy
- qcom,sa8775p-qmp-gen4x4-pcie-phy
- qcom,sc8180x-qmp-pcie-phy
@@ -184,6 +185,7 @@ allOf:
compatible:
contains:
enum:
+ - qcom,qcs8300-qmp-gen4x2-pcie-phy
- qcom,sa8775p-qmp-gen4x2-pcie-phy
- qcom,sa8775p-qmp-gen4x4-pcie-phy
then:
--
2.34.1
--
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^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v2 1/8] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the QCS8300 QMP PCIe PHY Gen4 x2
2024-11-28 8:10 ` [PATCH v2 1/8] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the QCS8300 QMP PCIe PHY Gen4 x2 Ziyue Zhang
@ 2024-11-28 10:17 ` Krzysztof Kozlowski
0 siblings, 0 replies; 17+ messages in thread
From: Krzysztof Kozlowski @ 2024-11-28 10:17 UTC (permalink / raw)
To: Ziyue Zhang, vkoul, kishon, robh+dt, manivannan.sadhasivam,
bhelgaas, kw, lpieralisi, quic_qianyu, conor+dt, neil.armstrong,
andersson, konradybcio
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas, quic_tingweiz,
quic_aiquny, kernel, linux-arm-msm, devicetree, linux-kernel,
linux-phy
On 28/11/2024 09:10, Ziyue Zhang wrote:
> Document the QMP PCIe PHY on the QCS8300 platform.
>
> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
> ---
You did not Cc me, even though maintainers script asks you to do that,
but you Cc-ed several folks from Qualcomm not really necessary.
Weird, but sure, I will not review your patch.
However note that just ignored existing review and tags.
<form letter>
This is a friendly reminder during the review process.
It looks like you received a tag and forgot to add it.
If you do not know the process, here is a short explanation:
Please add Acked-by/Reviewed-by/Tested-by tags when posting new
versions, under or above your Signed-off-by tag. Tag is "received", when
provided in a message replied to you on the mailing list. Tools like b4
can help here. However, there's no need to repost patches *only* to add
the tags. The upstream maintainer will do that for tags received on the
version they apply.
https://elixir.bootlin.com/linux/v6.5-rc3/source/Documentation/process/submitting-patches.rst#L577
If a tag was not added on purpose, please state why and what changed.
</form letter>
Best regards,
Krzysztof
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^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 2/8] phy: qcom-qmp-pcie: add dual lane PHY support for QCS8300
2024-11-28 8:10 [PATCH v2 0/8] pci: qcom: Add QCS8300 PCIe support Ziyue Zhang
2024-11-28 8:10 ` [PATCH v2 1/8] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the QCS8300 QMP PCIe PHY Gen4 x2 Ziyue Zhang
@ 2024-11-28 8:10 ` Ziyue Zhang
2024-11-28 13:22 ` Dmitry Baryshkov
2024-11-28 8:10 ` [PATCH v2 3/8] dt-bindings: PCI: qcom,pcie-sa8775p: document qcs8300 Ziyue Zhang
` (7 subsequent siblings)
9 siblings, 1 reply; 17+ messages in thread
From: Ziyue Zhang @ 2024-11-28 8:10 UTC (permalink / raw)
To: vkoul, kishon, robh+dt, manivannan.sadhasivam, bhelgaas, kw,
lpieralisi, quic_qianyu, conor+dt, neil.armstrong, andersson,
konradybcio
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas, quic_tingweiz,
quic_aiquny, kernel, linux-arm-msm, devicetree, linux-kernel,
linux-phy, Ziyue Zhang
The PCIe Gen4x2 PHY for qcs8300 has a lot of difference with sa8775p.
So the qcs8300_qmp_gen4x2_pcie_rx_alt_tbl for qcs8300 is added.
Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 89 ++++++++++++++++++++++++
1 file changed, 89 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index f71787fb4d7e..b7d4f37024cf 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -726,6 +726,58 @@ static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_pcs_misc_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
};
+static const struct qmp_phy_init_tbl qcs8300_qmp_gen4x2_pcie_rx_alt_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x9b),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0xd2),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x20),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9b),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xfb),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xd2),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xec),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xf3),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf8),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xec),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xd6),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x83),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xf5),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x5e),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x7c),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
+};
+
static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
@@ -3114,6 +3166,40 @@ static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
.skip_start_delay = true,
};
+static const struct qmp_phy_cfg qcs8300_qmp_gen4x2_pciephy_cfg = {
+ .lanes = 2,
+ .offsets = &qmp_pcie_offsets_v5_20,
+
+ .tbls = {
+ .serdes = sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl,
+ .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl),
+ .tx = sa8775p_qmp_gen4_pcie_tx_tbl,
+ .tx_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl),
+ .rx = qcs8300_qmp_gen4x2_pcie_rx_alt_tbl,
+ .rx_num = ARRAY_SIZE(qcs8300_qmp_gen4x2_pcie_rx_alt_tbl),
+ .pcs = sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl,
+ .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl),
+ .pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl,
+ .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl),
+ },
+
+ .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
+ .serdes = sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl,
+ .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl),
+ .pcs_misc = sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl,
+ .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl),
+ },
+
+ .reset_list = sdm845_pciephy_reset_l,
+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+ .regs = pciephy_v5_20_regs_layout,
+
+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+ .phy_status = PHYSTATUS_4_20,
+};
+
static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
.lanes = 2,
@@ -4400,6 +4486,9 @@ static const struct of_device_id qmp_pcie_of_match_table[] = {
}, {
.compatible = "qcom,msm8998-qmp-pcie-phy",
.data = &msm8998_pciephy_cfg,
+ }, {
+ .compatible = "qcom,qcs8300-qmp-gen4x2-pcie-phy",
+ .data = &qcs8300_qmp_gen4x2_pciephy_cfg,
}, {
.compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy",
.data = &sa8775p_qmp_gen4x2_pciephy_cfg,
--
2.34.1
--
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^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v2 2/8] phy: qcom-qmp-pcie: add dual lane PHY support for QCS8300
2024-11-28 8:10 ` [PATCH v2 2/8] phy: qcom-qmp-pcie: add dual lane PHY support for QCS8300 Ziyue Zhang
@ 2024-11-28 13:22 ` Dmitry Baryshkov
0 siblings, 0 replies; 17+ messages in thread
From: Dmitry Baryshkov @ 2024-11-28 13:22 UTC (permalink / raw)
To: Ziyue Zhang
Cc: vkoul, kishon, robh+dt, manivannan.sadhasivam, bhelgaas, kw,
lpieralisi, quic_qianyu, conor+dt, neil.armstrong, andersson,
konradybcio, quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas,
quic_tingweiz, quic_aiquny, kernel, linux-arm-msm, devicetree,
linux-kernel, linux-phy
On Thu, Nov 28, 2024 at 04:10:50PM +0800, Ziyue Zhang wrote:
> The PCIe Gen4x2 PHY for qcs8300 has a lot of difference with sa8775p.
> So the qcs8300_qmp_gen4x2_pcie_rx_alt_tbl for qcs8300 is added.
>
> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 89 ++++++++++++++++++++++++
> 1 file changed, 89 insertions(+)
v1 was already reviewed and got a tag which you've ignored. Please fix
your process to use b4 tool. While doing so, please collect all the tags
from v1.
--
With best wishes
Dmitry
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^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 3/8] dt-bindings: PCI: qcom,pcie-sa8775p: document qcs8300
2024-11-28 8:10 [PATCH v2 0/8] pci: qcom: Add QCS8300 PCIe support Ziyue Zhang
2024-11-28 8:10 ` [PATCH v2 1/8] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the QCS8300 QMP PCIe PHY Gen4 x2 Ziyue Zhang
2024-11-28 8:10 ` [PATCH v2 2/8] phy: qcom-qmp-pcie: add dual lane PHY support for QCS8300 Ziyue Zhang
@ 2024-11-28 8:10 ` Ziyue Zhang
2024-11-28 8:10 ` [PATCH v2 4/8] PCI: qcom: Add QCS8300 PCIe support Ziyue Zhang
` (6 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Ziyue Zhang @ 2024-11-28 8:10 UTC (permalink / raw)
To: vkoul, kishon, robh+dt, manivannan.sadhasivam, bhelgaas, kw,
lpieralisi, quic_qianyu, conor+dt, neil.armstrong, andersson,
konradybcio
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas, quic_tingweiz,
quic_aiquny, kernel, linux-arm-msm, devicetree, linux-kernel,
linux-phy, Ziyue Zhang
Add compatible for qcs8300 platform.
Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
---
.../devicetree/bindings/pci/qcom,pcie-sa8775p.yaml | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml
index efde49d1bef8..19e3ee1b380d 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml
@@ -16,7 +16,12 @@ description:
properties:
compatible:
- const: qcom,pcie-sa8775p
+ oneOf:
+ - const: qcom,pcie-sa8775p
+ - items:
+ - enum:
+ - qcom,pcie-qcs8300
+ - const: qcom,pcie-sa8775p
reg:
minItems: 6
--
2.34.1
--
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^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v2 4/8] PCI: qcom: Add QCS8300 PCIe support
2024-11-28 8:10 [PATCH v2 0/8] pci: qcom: Add QCS8300 PCIe support Ziyue Zhang
` (2 preceding siblings ...)
2024-11-28 8:10 ` [PATCH v2 3/8] dt-bindings: PCI: qcom,pcie-sa8775p: document qcs8300 Ziyue Zhang
@ 2024-11-28 8:10 ` Ziyue Zhang
2024-11-29 19:08 ` Bjorn Helgaas
2024-11-28 8:10 ` [PATCH v2 5/8] arm64: dts: qcom: qcs8300: enable pcie0 for qcs8300 platform Ziyue Zhang
` (5 subsequent siblings)
9 siblings, 1 reply; 17+ messages in thread
From: Ziyue Zhang @ 2024-11-28 8:10 UTC (permalink / raw)
To: vkoul, kishon, robh+dt, manivannan.sadhasivam, bhelgaas, kw,
lpieralisi, quic_qianyu, conor+dt, neil.armstrong, andersson,
konradybcio
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas, quic_tingweiz,
quic_aiquny, kernel, linux-arm-msm, devicetree, linux-kernel,
linux-phy, Ziyue Zhang
Add support for QCS8300 SoC that uses controller version 5.90
reusing the 1.9.0 config.
Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
---
drivers/pci/controller/dwc/pcie-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index ef44a82be058..5932b228aa17 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1830,6 +1830,7 @@ static const struct of_device_id qcom_pcie_match[] = {
{ .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
{ .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
{ .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
+ { .compatible = "qcom,pcie-qcs8300", .data = &cfg_1_9_0 },
{ .compatible = "qcom,pcie-sa8540p", .data = &cfg_sc8280xp },
{ .compatible = "qcom,pcie-sa8775p", .data = &cfg_1_34_0},
{ .compatible = "qcom,pcie-sc7280", .data = &cfg_1_9_0 },
--
2.34.1
--
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^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v2 4/8] PCI: qcom: Add QCS8300 PCIe support
2024-11-28 8:10 ` [PATCH v2 4/8] PCI: qcom: Add QCS8300 PCIe support Ziyue Zhang
@ 2024-11-29 19:08 ` Bjorn Helgaas
0 siblings, 0 replies; 17+ messages in thread
From: Bjorn Helgaas @ 2024-11-29 19:08 UTC (permalink / raw)
To: Ziyue Zhang
Cc: vkoul, kishon, robh+dt, manivannan.sadhasivam, bhelgaas, kw,
lpieralisi, quic_qianyu, conor+dt, neil.armstrong, andersson,
konradybcio, quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas,
quic_tingweiz, quic_aiquny, kernel, linux-arm-msm, devicetree,
linux-kernel, linux-phy, linux-pci
[+cc linux-pci]
On Thu, Nov 28, 2024 at 04:10:52PM +0800, Ziyue Zhang wrote:
> Add support for QCS8300 SoC that uses controller version 5.90
> reusing the 1.9.0 config.
>
> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
> ---
> drivers/pci/controller/dwc/pcie-qcom.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index ef44a82be058..5932b228aa17 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -1830,6 +1830,7 @@ static const struct of_device_id qcom_pcie_match[] = {
> { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
> { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
> { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
> + { .compatible = "qcom,pcie-qcs8300", .data = &cfg_1_9_0 },
> { .compatible = "qcom,pcie-sa8540p", .data = &cfg_sc8280xp },
> { .compatible = "qcom,pcie-sa8775p", .data = &cfg_1_34_0},
> { .compatible = "qcom,pcie-sc7280", .data = &cfg_1_9_0 },
> --
> 2.34.1
>
>
--
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 5/8] arm64: dts: qcom: qcs8300: enable pcie0 for qcs8300 platform
2024-11-28 8:10 [PATCH v2 0/8] pci: qcom: Add QCS8300 PCIe support Ziyue Zhang
` (3 preceding siblings ...)
2024-11-28 8:10 ` [PATCH v2 4/8] PCI: qcom: Add QCS8300 PCIe support Ziyue Zhang
@ 2024-11-28 8:10 ` Ziyue Zhang
2024-11-28 13:22 ` Dmitry Baryshkov
2024-11-28 8:10 ` [PATCH v2 6/8] arm64: dts: qcom: qcs8300: enable pcie0 for qcs8300 soc Ziyue Zhang
` (4 subsequent siblings)
9 siblings, 1 reply; 17+ messages in thread
From: Ziyue Zhang @ 2024-11-28 8:10 UTC (permalink / raw)
To: vkoul, kishon, robh+dt, manivannan.sadhasivam, bhelgaas, kw,
lpieralisi, quic_qianyu, conor+dt, neil.armstrong, andersson,
konradybcio
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas, quic_tingweiz,
quic_aiquny, kernel, linux-arm-msm, devicetree, linux-kernel,
linux-phy, Ziyue Zhang
Add configurations in devicetree for PCIe0, board related gpios,
PMIC regulators, etc.
Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
---
arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 44 ++++++++++++++++++++++-
1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
index 7eed19a694c3..7f97f771c44a 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
+++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
@@ -213,7 +213,7 @@ vreg_l9c: ldo9 {
&gcc {
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>,
- <0>,
+ <&pcie0_phy>,
<0>,
<0>,
<0>,
@@ -223,6 +223,23 @@ &gcc {
<0>;
};
+&pcie0 {
+ perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l6a>;
+ vdda-pll-supply = <&vreg_l5a>;
+
+ status = "okay";
+};
+
&qupv3_id_0 {
status = "okay";
};
@@ -247,6 +264,31 @@ &rpmhcc {
clock-names = "xo";
};
+&tlmm {
+ pcie0_default_state: pcie0-default-state {
+ clkreq-pins {
+ pins = "gpio1";
+ function = "pcie0_clkreq";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-pins {
+ pins = "gpio2";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ wake-pins {
+ pins = "gpio0";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+};
+
&uart7 {
status = "okay";
};
--
2.34.1
--
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v2 5/8] arm64: dts: qcom: qcs8300: enable pcie0 for qcs8300 platform
2024-11-28 8:10 ` [PATCH v2 5/8] arm64: dts: qcom: qcs8300: enable pcie0 for qcs8300 platform Ziyue Zhang
@ 2024-11-28 13:22 ` Dmitry Baryshkov
0 siblings, 0 replies; 17+ messages in thread
From: Dmitry Baryshkov @ 2024-11-28 13:22 UTC (permalink / raw)
To: Ziyue Zhang
Cc: vkoul, kishon, robh+dt, manivannan.sadhasivam, bhelgaas, kw,
lpieralisi, quic_qianyu, conor+dt, neil.armstrong, andersson,
konradybcio, quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas,
quic_tingweiz, quic_aiquny, kernel, linux-arm-msm, devicetree,
linux-kernel, linux-phy
On Thu, Nov 28, 2024 at 04:10:53PM +0800, Ziyue Zhang wrote:
> Add configurations in devicetree for PCIe0, board related gpios,
> PMIC regulators, etc.
>
> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 44 ++++++++++++++++++++++-
> 1 file changed, 43 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
> index 7eed19a694c3..7f97f771c44a 100644
> --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
> +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
> @@ -213,7 +213,7 @@ vreg_l9c: ldo9 {
> &gcc {
> clocks = <&rpmhcc RPMH_CXO_CLK>,
> <&sleep_clk>,
> - <0>,
> + <&pcie0_phy>,
Review comment was ignored, NAK.
> <0>,
> <0>,
> <0>,
> @@ -223,6 +223,23 @@ &gcc {
> <0>;
> };
>
> +&pcie0 {
> + perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
> +
> + pinctrl-0 = <&pcie0_default_state>;
> + pinctrl-names = "default";
> +
> + status = "okay";
> +};
> +
> +&pcie0_phy {
> + vdda-phy-supply = <&vreg_l6a>;
> + vdda-pll-supply = <&vreg_l5a>;
> +
> + status = "okay";
> +};
> +
> &qupv3_id_0 {
> status = "okay";
> };
> @@ -247,6 +264,31 @@ &rpmhcc {
> clock-names = "xo";
> };
>
> +&tlmm {
> + pcie0_default_state: pcie0-default-state {
> + clkreq-pins {
> + pins = "gpio1";
> + function = "pcie0_clkreq";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + perst-pins {
> + pins = "gpio2";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + wake-pins {
> + pins = "gpio0";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +};
> +
> &uart7 {
> status = "okay";
> };
> --
> 2.34.1
>
--
With best wishes
Dmitry
--
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^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 6/8] arm64: dts: qcom: qcs8300: enable pcie0 for qcs8300 soc
2024-11-28 8:10 [PATCH v2 0/8] pci: qcom: Add QCS8300 PCIe support Ziyue Zhang
` (4 preceding siblings ...)
2024-11-28 8:10 ` [PATCH v2 5/8] arm64: dts: qcom: qcs8300: enable pcie0 for qcs8300 platform Ziyue Zhang
@ 2024-11-28 8:10 ` Ziyue Zhang
2024-12-05 17:40 ` Konrad Dybcio
2024-11-28 8:10 ` [PATCH v2 7/8] arm64: dts: qcom: qcs8300: enable pcie1 " Ziyue Zhang
` (3 subsequent siblings)
9 siblings, 1 reply; 17+ messages in thread
From: Ziyue Zhang @ 2024-11-28 8:10 UTC (permalink / raw)
To: vkoul, kishon, robh+dt, manivannan.sadhasivam, bhelgaas, kw,
lpieralisi, quic_qianyu, conor+dt, neil.armstrong, andersson,
konradybcio
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas, quic_tingweiz,
quic_aiquny, kernel, linux-arm-msm, devicetree, linux-kernel,
linux-phy, Ziyue Zhang
Add configurations in devicetree for PCIe0, including registers, clocks,
interrupts and phy setting sequence.
Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
---
arch/arm64/boot/dts/qcom/qcs8300.dtsi | 175 ++++++++++++++++++++++++++
1 file changed, 175 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
index 2c35f96c3f28..952a84b065c3 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
@@ -637,6 +637,181 @@ mmss_noc: interconnect@17a0000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ pcie0: pci@1c00000 {
+ device_type = "pci";
+ compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p";
+ reg = <0x0 0x01c00000 0x0 0x3000>,
+ <0x0 0x40000000 0x0 0xf20>,
+ <0x0 0x40000f20 0x0 0xa8>,
+ <0x0 0x40001000 0x0 0x4000>,
+ <0x0 0x40100000 0x0 0x100000>,
+ <0x0 0x01c03000 0x0 0x1000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config",
+ "mhi";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
+ <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
+ bus-range = <0x00 0xff>;
+
+ dma-coherent;
+
+ linux,pci-domain = <0>;
+ num-lanes = <2>;
+
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "global";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
+
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a";
+
+ assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ interconnects = <&pcie_anoc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
+ <0x100 &pcie_smmu 0x0001 0x1>;
+
+ resets = <&gcc GCC_PCIE_0_BCR>;
+ reset-names = "pci";
+ power-domains = <&gcc GCC_PCIE_0_GDSC>;
+
+ phys = <&pcie0_phy>;
+ phy-names = "pciephy";
+
+ status = "disabled";
+
+ pcie3_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ /* GEN 1 x1 */
+ opp-2500000 {
+ opp-hz = /bits/ 64 <2500000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ opp-peak-kBps = <250000 1>;
+ };
+
+ /* GEN 1 x2 and GEN 2 x1 */
+ opp-5000000 {
+ opp-hz = /bits/ 64 <5000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ opp-peak-kBps = <500000 1>;
+ };
+
+ /* GEN 2 x2 */
+ opp-10000000 {
+ opp-hz = /bits/ 64 <10000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ opp-peak-kBps = <1000000 1>;
+ };
+
+ /* GEN 3 x1 */
+ opp-8000000 {
+ opp-hz = /bits/ 64 <8000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ opp-peak-kBps = <984500 1>;
+ };
+
+ /* GEN 3 x2 and GEN 4 x1 */
+ opp-16000000 {
+ opp-hz = /bits/ 64 <16000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <1969000 1>;
+ };
+
+ /* GEN 4 x2 */
+ opp-32000000 {
+ opp-hz = /bits/ 64 <32000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <3938000 1>;
+ };
+ };
+
+ pcieport0: pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ bus-range = <0x01 0xff>;
+ };
+ };
+
+ pcie0_phy: phy@1c04000 {
+ compatible = "qcom,qcs8300-qmp-gen4x2-pcie-phy";
+ reg = <0x0 0x1c04000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_CLKREF_EN>,
+ <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_0_PIPE_CLK>,
+ <&gcc GCC_PCIE_0_PIPEDIV2_CLK>,
+ <&gcc GCC_PCIE_0_PHY_AUX_CLK>;
+
+ clock-names = "cfg_ahb",
+ "ref",
+ "rchng",
+ "pipe",
+ "pipediv2",
+ "phy_aux";
+
+ assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ resets = <&gcc GCC_PCIE_0_PHY_BCR>;
+ reset-names = "phy";
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie_0_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
ufs_mem_hc: ufs@1d84000 {
compatible = "qcom,qcs8300-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
reg = <0x0 0x01d84000 0x0 0x3000>;
--
2.34.1
--
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^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v2 6/8] arm64: dts: qcom: qcs8300: enable pcie0 for qcs8300 soc
2024-11-28 8:10 ` [PATCH v2 6/8] arm64: dts: qcom: qcs8300: enable pcie0 for qcs8300 soc Ziyue Zhang
@ 2024-12-05 17:40 ` Konrad Dybcio
0 siblings, 0 replies; 17+ messages in thread
From: Konrad Dybcio @ 2024-12-05 17:40 UTC (permalink / raw)
To: Ziyue Zhang, vkoul, kishon, robh+dt, manivannan.sadhasivam,
bhelgaas, kw, lpieralisi, quic_qianyu, conor+dt, neil.armstrong,
andersson, konradybcio
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas, quic_tingweiz,
quic_aiquny, kernel, linux-arm-msm, devicetree, linux-kernel,
linux-phy
On 28.11.2024 9:10 AM, Ziyue Zhang wrote:
> Add configurations in devicetree for PCIe0, including registers, clocks,
> interrupts and phy setting sequence.
>
> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 175 ++++++++++++++++++++++++++
> 1 file changed, 175 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> index 2c35f96c3f28..952a84b065c3 100644
> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> @@ -637,6 +637,181 @@ mmss_noc: interconnect@17a0000 {
> qcom,bcm-voters = <&apps_bcm_voter>;
> };
>
> + pcie0: pci@1c00000 {
> + device_type = "pci";
> + compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p";
> + reg = <0x0 0x01c00000 0x0 0x3000>,
> + <0x0 0x40000000 0x0 0xf20>,
> + <0x0 0x40000f20 0x0 0xa8>,
> + <0x0 0x40001000 0x0 0x4000>,
> + <0x0 0x40100000 0x0 0x100000>,
> + <0x0 0x01c03000 0x0 0x1000>;
> + reg-names = "parf",
> + "dbi",
> + "elbi",
> + "atu",
> + "config",
> + "mhi";
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
> + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
> + bus-range = <0x00 0xff>;
> +
> + dma-coherent;
> +
> + linux,pci-domain = <0>;
> + num-lanes = <2>;
> +
> + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
Weird indent
> +
Stray newline
> + interrupt-names = "msi0",
> + "msi1",
> + "msi2",
> + "msi3",
> + "msi4",
> + "msi5",
> + "msi6",
> + "msi7",
> + "global";
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
> + <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
> + <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
> + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
> +
Ditto
> + clock-names = "aux",
> + "cfg",
> + "bus_master",
> + "bus_slave",
> + "slave_q2a";
> +
> + assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
> + assigned-clock-rates = <19200000>;
> +
> + interconnects = <&pcie_anoc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> + &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>;
QCOM_ICC_TAG_ACTIVE_ONLY for the cpu-pcie path, both endpoints
> + interconnect-names = "pcie-mem", "cpu-pcie";
[...]
> + pcie0_phy: phy@1c04000 {
> + compatible = "qcom,qcs8300-qmp-gen4x2-pcie-phy";
> + reg = <0x0 0x1c04000 0x0 0x2000>;
Please pad the address part to 8 hex digits with leading zeroes
> +
> + clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_CLKREF_EN>,
> + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
> + <&gcc GCC_PCIE_0_PIPE_CLK>,
> + <&gcc GCC_PCIE_0_PIPEDIV2_CLK>,
> + <&gcc GCC_PCIE_0_PHY_AUX_CLK>;
> +
Ditto
> + clock-names = "cfg_ahb",
> + "ref",
> + "rchng",
> + "pipe",
> + "pipediv2",
> +
The same for pcie1
Konrad
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^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 7/8] arm64: dts: qcom: qcs8300: enable pcie1 for qcs8300 soc
2024-11-28 8:10 [PATCH v2 0/8] pci: qcom: Add QCS8300 PCIe support Ziyue Zhang
` (5 preceding siblings ...)
2024-11-28 8:10 ` [PATCH v2 6/8] arm64: dts: qcom: qcs8300: enable pcie0 for qcs8300 soc Ziyue Zhang
@ 2024-11-28 8:10 ` Ziyue Zhang
2024-11-28 8:10 ` [PATCH v2 8/8] arm64: dts: qcom: qcs8300: enable pcie1 for qcs8300 platform Ziyue Zhang
` (2 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Ziyue Zhang @ 2024-11-28 8:10 UTC (permalink / raw)
To: vkoul, kishon, robh+dt, manivannan.sadhasivam, bhelgaas, kw,
lpieralisi, quic_qianyu, conor+dt, neil.armstrong, andersson,
konradybcio
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas, quic_tingweiz,
quic_aiquny, kernel, linux-arm-msm, devicetree, linux-kernel,
linux-phy, Ziyue Zhang
Add configurations in devicetree for PCIe1, including registers, clocks,
interrupts and phy setting sequence.
Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
---
arch/arm64/boot/dts/qcom/qcs8300.dtsi | 177 ++++++++++++++++++++++++++
1 file changed, 177 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
index 952a84b065c3..5ad5eb0d5c9b 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
@@ -812,6 +812,183 @@ pcie0_phy: phy@1c04000 {
status = "disabled";
};
+ pcie1: pci@1c10000 {
+ device_type = "pci";
+ compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p";
+ reg = <0x0 0x01c10000 0x0 0x3000>,
+ <0x0 0x60000000 0x0 0xf20>,
+ <0x0 0x60000f20 0x0 0xa8>,
+ <0x0 0x60001000 0x0 0x4000>,
+ <0x0 0x60100000 0x0 0x100000>,
+ <0x0 0x01c13000 0x0 0x1000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config",
+ "mhi";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>;
+ bus-range = <0x00 0xff>;
+
+ dma-coherent;
+
+ linux,pci-domain = <1>;
+ num-lanes = <4>;
+
+ interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "global";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
+ <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a";
+
+ assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ interconnects = <&pcie_anoc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_PCIE_1 0>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ iommu-map = <0x0 &pcie_smmu 0x0080 0x1>,
+ <0x100 &pcie_smmu 0x0081 0x1>;
+
+ resets = <&gcc GCC_PCIE_1_BCR>;
+ reset-names = "pci";
+ power-domains = <&gcc GCC_PCIE_1_GDSC>;
+
+ phys = <&pcie1_phy>;
+ phy-names = "pciephy";
+
+ status = "disabled";
+
+ pcie3_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ /* GEN 1 x1 */
+ opp-2500000 {
+ opp-hz = /bits/ 64 <2500000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ opp-peak-kBps = <250000 1>;
+ };
+
+ /* GEN 1 x2 and GEN 2 x1 */
+ opp-5000000 {
+ opp-hz = /bits/ 64 <5000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ opp-peak-kBps = <500000 1>;
+ };
+
+ /* GEN 1 x4 and GEN 2 x2 */
+ opp-10000000 {
+ opp-hz = /bits/ 64 <10000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ opp-peak-kBps = <1000000 1>;
+ };
+
+ /* GEN 2 x4 */
+ opp-20000000 {
+ opp-hz = /bits/ 64 <20000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <2000000 1>;
+ };
+
+ /* GEN 3 x1 */
+ opp-8000000 {
+ opp-hz = /bits/ 64 <8000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ opp-peak-kBps = <984500 1>;
+ };
+
+ /* GEN 3 x2 and GEN 4 x1 */
+ opp-16000000 {
+ opp-hz = /bits/ 64 <16000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <1969000 1>;
+ };
+
+ /* GEN 3 x4 and GEN 4 x2 */
+ opp-32000000 {
+ opp-hz = /bits/ 64 <32000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <3938000 1>;
+ };
+
+ /* GEN 4 x4 */
+ opp-64000000 {
+ opp-hz = /bits/ 64 <64000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <7876000 1>;
+ };
+ };
+ };
+
+ pcie1_phy: phy@1c14000 {
+ compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
+ reg = <0x0 0x1c14000 0x0 0x4000>;
+
+ clocks = <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_CLKREF_EN>,
+ <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_1_PIPE_CLK>,
+ <&gcc GCC_PCIE_1_PIPEDIV2_CLK>,
+ <&gcc GCC_PCIE_1_PHY_AUX_CLK>;
+
+ clock-names = "cfg_ahb",
+ "ref",
+ "rchng",
+ "pipe",
+ "pipediv2",
+ "phy_aux";
+
+ assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ resets = <&gcc GCC_PCIE_1_PHY_BCR>;
+ reset-names = "phy";
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie_1_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
ufs_mem_hc: ufs@1d84000 {
compatible = "qcom,qcs8300-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
reg = <0x0 0x01d84000 0x0 0x3000>;
--
2.34.1
--
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^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v2 8/8] arm64: dts: qcom: qcs8300: enable pcie1 for qcs8300 platform
2024-11-28 8:10 [PATCH v2 0/8] pci: qcom: Add QCS8300 PCIe support Ziyue Zhang
` (6 preceding siblings ...)
2024-11-28 8:10 ` [PATCH v2 7/8] arm64: dts: qcom: qcs8300: enable pcie1 " Ziyue Zhang
@ 2024-11-28 8:10 ` Ziyue Zhang
2024-12-05 17:41 ` Konrad Dybcio
2024-11-29 19:30 ` [PATCH v2 0/8] pci: qcom: Add QCS8300 PCIe support Bjorn Helgaas
2024-11-29 19:33 ` Bjorn Helgaas
9 siblings, 1 reply; 17+ messages in thread
From: Ziyue Zhang @ 2024-11-28 8:10 UTC (permalink / raw)
To: vkoul, kishon, robh+dt, manivannan.sadhasivam, bhelgaas, kw,
lpieralisi, quic_qianyu, conor+dt, neil.armstrong, andersson,
konradybcio
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas, quic_tingweiz,
quic_aiquny, kernel, linux-arm-msm, devicetree, linux-kernel,
linux-phy, Ziyue Zhang
Add configurations in devicetree for PCIe1, board related gpios,
PMIC regulators, etc.
Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
---
arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 42 ++++++++++++++++++++++-
1 file changed, 41 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
index 7f97f771c44a..a83faba0252e 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
+++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
@@ -214,7 +214,7 @@ &gcc {
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>,
<&pcie0_phy>,
- <0>,
+ <&pcie1_phy>,
<0>,
<0>,
<0>,
@@ -240,6 +240,23 @@ &pcie0_phy {
status = "okay";
};
+&pcie1 {
+ perst-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&pcie1_default_state>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie1_phy {
+ vdda-phy-supply = <&vreg_l6a>;
+ vdda-pll-supply = <&vreg_l5a>;
+
+ status = "okay";
+};
+
&qupv3_id_0 {
status = "okay";
};
@@ -287,6 +304,29 @@ wake-pins {
bias-pull-up;
};
};
+
+ pcie1_default_state: pcie1-default-state {
+ clkreq-pins {
+ pins = "gpio22";
+ function = "pcie1_clkreq";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-pins {
+ pins = "gpio23";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ wake-pins {
+ pins = "gpio21";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
};
&uart7 {
--
2.34.1
--
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^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v2 8/8] arm64: dts: qcom: qcs8300: enable pcie1 for qcs8300 platform
2024-11-28 8:10 ` [PATCH v2 8/8] arm64: dts: qcom: qcs8300: enable pcie1 for qcs8300 platform Ziyue Zhang
@ 2024-12-05 17:41 ` Konrad Dybcio
0 siblings, 0 replies; 17+ messages in thread
From: Konrad Dybcio @ 2024-12-05 17:41 UTC (permalink / raw)
To: Ziyue Zhang, vkoul, kishon, robh+dt, manivannan.sadhasivam,
bhelgaas, kw, lpieralisi, quic_qianyu, conor+dt, neil.armstrong,
andersson, konradybcio
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas, quic_tingweiz,
quic_aiquny, kernel, linux-arm-msm, devicetree, linux-kernel,
linux-phy
On 28.11.2024 9:10 AM, Ziyue Zhang wrote:
> Add configurations in devicetree for PCIe1, board related gpios,
> PMIC regulators, etc.
>
> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 42 ++++++++++++++++++++++-
> 1 file changed, 41 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
> index 7f97f771c44a..a83faba0252e 100644
> --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
> +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
> @@ -214,7 +214,7 @@ &gcc {
> clocks = <&rpmhcc RPMH_CXO_CLK>,
> <&sleep_clk>,
> <&pcie0_phy>,
> - <0>,
> + <&pcie1_phy>,
> <0>,
> <0>,
> <0>,
This should be in the previous patch
Otherwise lgtm
Konrad
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^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 0/8] pci: qcom: Add QCS8300 PCIe support
2024-11-28 8:10 [PATCH v2 0/8] pci: qcom: Add QCS8300 PCIe support Ziyue Zhang
` (7 preceding siblings ...)
2024-11-28 8:10 ` [PATCH v2 8/8] arm64: dts: qcom: qcs8300: enable pcie1 for qcs8300 platform Ziyue Zhang
@ 2024-11-29 19:30 ` Bjorn Helgaas
2024-11-29 19:33 ` Bjorn Helgaas
9 siblings, 0 replies; 17+ messages in thread
From: Bjorn Helgaas @ 2024-11-29 19:30 UTC (permalink / raw)
To: Ziyue Zhang
Cc: vkoul, kishon, robh+dt, manivannan.sadhasivam, bhelgaas, kw,
lpieralisi, quic_qianyu, conor+dt, neil.armstrong, andersson,
konradybcio, quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas,
quic_tingweiz, quic_aiquny, kernel, linux-arm-msm, devicetree,
linux-kernel, linux-phy, Krishna chaitanya chundru, linux-pci
[+cc linux-pci; odd to have a series labeled "pci: ..." but without
copying linux-pci]
On Thu, Nov 28, 2024 at 04:10:48PM +0800, Ziyue Zhang wrote:
> This series adds document, phy, configs support for PCIe in QCS8300.
> The series depend on the following devicetree.
>
> Base DT:
> https://lore.kernel.org/all/20240925-qcs8300_initial_dtsi-v2-0-494c40fa2a42@quicinc.com/
>
> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
> ---
> Have follwing changes:
> - Document the QMP PCIe PHY on the QCS8300 platform.
> - Add dedicated schema for the PCIe controllers found on QCS8300.
> - Add compatible for qcs8300 platform.
> - Add configurations in devicetree for PCIe0, including registers, clocks, interrupts and phy setting sequence.
> - Add configurations in devicetree for PCIe1, including registers, clocks, interrupts and phy setting sequence.
>
> Changes in v2:
> - Fix some format comments
> - Add global interrupt for PCIe0 and PCIe1
> - split the soc dtsi and the platform dts into two changes
> - Link to v1: https://lore.kernel.org/all/20241114095409.2682558-1-quic_ziyuzhan@quicinc.com/
>
> Ziyue Zhang (8):
> dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the QCS8300 QMP
> PCIe PHY Gen4 x2
> phy: qcom-qmp-pcie: add dual lane PHY support for QCS8300
> dt-bindings: PCI: qcom,pcie-sa8775p: document qcs8300
> PCI: qcom: Add QCS8300 PCIe support
> arm64: dts: qcom: qcs8300: enable pcie0 for qcs8300 platform
> arm64: dts: qcom: qcs8300: enable pcie0 for qcs8300 soc
> arm64: dts: qcom: qcs8300: enable pcie1 for qcs8300 soc
> arm64: dts: qcom: qcs8300: enable pcie1 for qcs8300 platform
>
> .../bindings/pci/qcom,pcie-sa8775p.yaml | 7 +-
> .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 2 +
> arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 86 ++++-
> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 352 ++++++++++++++++++
> drivers/pci/controller/dwc/pcie-qcom.c | 1 +
> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 89 +++++
> 6 files changed, 534 insertions(+), 3 deletions(-)
>
>
> base-commit: eb6a0b56032c62351a59a12915a89428bce68d1d
> --
> 2.34.1
>
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^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v2 0/8] pci: qcom: Add QCS8300 PCIe support
2024-11-28 8:10 [PATCH v2 0/8] pci: qcom: Add QCS8300 PCIe support Ziyue Zhang
` (8 preceding siblings ...)
2024-11-29 19:30 ` [PATCH v2 0/8] pci: qcom: Add QCS8300 PCIe support Bjorn Helgaas
@ 2024-11-29 19:33 ` Bjorn Helgaas
9 siblings, 0 replies; 17+ messages in thread
From: Bjorn Helgaas @ 2024-11-29 19:33 UTC (permalink / raw)
To: Ziyue Zhang
Cc: vkoul, kishon, robh+dt, manivannan.sadhasivam, bhelgaas, kw,
lpieralisi, quic_qianyu, conor+dt, neil.armstrong, andersson,
konradybcio, quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas,
quic_tingweiz, quic_aiquny, kernel, linux-arm-msm, devicetree,
linux-kernel, linux-phy, Krishna chaitanya chundru, linux-pci
On Thu, Nov 28, 2024 at 04:10:48PM +0800, Ziyue Zhang wrote:
> This series adds document, phy, configs support for PCIe in QCS8300.
> The series depend on the following devicetree.
> base-commit: eb6a0b56032c62351a59a12915a89428bce68d1d
Also, this commit doesn't appear in upstream or linux-next, so we need
some hint about where to get it. The most recent -rc1 tag is a good
default unless the series depends on something not included there.
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^ permalink raw reply [flat|nested] 17+ messages in thread