[PATCH v2 0/2] phy: renesas: r8a779f0-ether-serdes: driver enhancement

[PATCH v2 0/2] phy: renesas: r8a779f0-ether-serdes: driver enhancement

[Michael Dege]

Hi,

This patch set adds the following to the r8a779f0-ether-serdes driver:

 * USXGMII mode support for 2.5GBit/s ethernet Phys
 * A new configuration step suggested by the latest R-Car S4-8 users
   manual V. 1.20.

Changes from v1:
 - Modify this driver for the R-Car S4-8 only
 - So, this patch set drops the followings:
 -- any dt doc modification
 -- X5H support.
 -- 5GBASER support
 -- Registers' macros

Thanks,

Michael

Signed-off-by: Michael Dege <michael.dege@renesas.com>
---
Michael Dege (2):
      phy: renesas: r8a779f0-ether-serdes: add USXGMII mode
      phy: renesas: r8a779f0-ether-serdes: add new step added to latest datasheet

 drivers/phy/renesas/r8a779f0-ether-serdes.c | 97 +++++++++++++++++++++++++----
 1 file changed, 85 insertions(+), 12 deletions(-)
---
base-commit: a5806cd506af5a7c19bcd596e4708b5c464bfd21
change-id: 20250523-renesas-serdes-update-3ec462f16ff4

Best regards,
-- 
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[PATCH v2 1/2] phy: renesas: r8a779f0-ether-serdes: add USXGMII mode

[Michael Dege]

The initial driver implementation was limited to SGMII and 1GBit/s. The
new mode allows speeds up to 2.5GBit/s on R-Car S4-8 SOCs.

Signed-off-by: Michael Dege <michael.dege@renesas.com>
---
 drivers/phy/renesas/r8a779f0-ether-serdes.c | 69 ++++++++++++++++++++++++-----
 1 file changed, 57 insertions(+), 12 deletions(-)

diff --git a/drivers/phy/renesas/r8a779f0-ether-serdes.c b/drivers/phy/renesas/r8a779f0-ether-serdes.c
index 3b2d8cef75e52c939fcc8806961e172dbafb8008..ed83c46f6d00c255852cc5af867c89ab0d0db02a 100644
--- a/drivers/phy/renesas/r8a779f0-ether-serdes.c
+++ b/drivers/phy/renesas/r8a779f0-ether-serdes.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 /* Renesas Ethernet SERDES device driver
  *
- * Copyright (C) 2022 Renesas Electronics Corporation
+ * Copyright (C) 2022-2025 Renesas Electronics Corporation
  */
 
 #include <linux/delay.h>
@@ -92,17 +92,18 @@ r8a779f0_eth_serdes_common_setting(struct r8a779f0_eth_serdes_channel *channel)
 {
 	struct r8a779f0_eth_serdes_drv_data *dd = channel->dd;
 
-	switch (channel->phy_interface) {
-	case PHY_INTERFACE_MODE_SGMII:
-		r8a779f0_eth_serdes_write32(dd->addr, 0x0244, 0x180, 0x0097);
-		r8a779f0_eth_serdes_write32(dd->addr, 0x01d0, 0x180, 0x0060);
-		r8a779f0_eth_serdes_write32(dd->addr, 0x01d8, 0x180, 0x2200);
-		r8a779f0_eth_serdes_write32(dd->addr, 0x01d4, 0x180, 0x0000);
-		r8a779f0_eth_serdes_write32(dd->addr, 0x01e0, 0x180, 0x003d);
-		return 0;
-	default:
-		return -EOPNOTSUPP;
-	}
+	/* Set combination mode */
+	r8a779f0_eth_serdes_write32(dd->addr, 0x0244, 0x180, 0x00d7);
+	r8a779f0_eth_serdes_write32(dd->addr, 0x01cc, 0x180, 0xc200);
+	r8a779f0_eth_serdes_write32(dd->addr, 0x01c4, 0x180, 0x0042);
+	r8a779f0_eth_serdes_write32(dd->addr, 0x01c8, 0x180, 0x0000);
+	r8a779f0_eth_serdes_write32(dd->addr, 0x01dc, 0x180, 0x002f);
+	r8a779f0_eth_serdes_write32(dd->addr, 0x01d0, 0x180, 0x0060);
+	r8a779f0_eth_serdes_write32(dd->addr, 0x01d8, 0x180, 0x2200);
+	r8a779f0_eth_serdes_write32(dd->addr, 0x01d4, 0x180, 0x0000);
+	r8a779f0_eth_serdes_write32(dd->addr, 0x01e0, 0x180, 0x003d);
+
+	return 0;
 }
 
 static int
@@ -155,6 +156,42 @@ r8a779f0_eth_serdes_chan_setting(struct r8a779f0_eth_serdes_channel *channel)
 		r8a779f0_eth_serdes_write32(channel->addr, 0x0028, 0x1f80, 0x07a1);
 		r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x1f80, 0x0208);
 		break;
+
+	case PHY_INTERFACE_MODE_USXGMII:
+		r8a779f0_eth_serdes_write32(channel->addr, 0x001c, 0x300, 0x0000);
+		r8a779f0_eth_serdes_write32(channel->addr, 0x0014, 0x380, 0x0050);
+		r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x380, 0x2200);
+		r8a779f0_eth_serdes_write32(channel->addr, 0x001c, 0x380, 0x0400);
+		r8a779f0_eth_serdes_write32(channel->addr, 0x01c0, 0x180, 0x0001);
+		r8a779f0_eth_serdes_write32(channel->addr, 0x0248, 0x180, 0x056a);
+		r8a779f0_eth_serdes_write32(channel->addr, 0x0258, 0x180, 0x0015);
+		r8a779f0_eth_serdes_write32(channel->addr, 0x0144, 0x180, 0x1100);
+		r8a779f0_eth_serdes_write32(channel->addr, 0x01a0, 0x180, 0x0001);
+		r8a779f0_eth_serdes_write32(channel->addr, 0x00d0, 0x180, 0x0001);
+		r8a779f0_eth_serdes_write32(channel->addr, 0x0150, 0x180, 0x0001);
+		r8a779f0_eth_serdes_write32(channel->addr, 0x00c8, 0x180, 0x0300);
+		r8a779f0_eth_serdes_write32(channel->addr, 0x0148, 0x180, 0x0300);
+		r8a779f0_eth_serdes_write32(channel->addr, 0x0174, 0x180, 0x0000);
+		r8a779f0_eth_serdes_write32(channel->addr, 0x0160, 0x180, 0x0004);
+		r8a779f0_eth_serdes_write32(channel->addr, 0x01ac, 0x180, 0x0000);
+		r8a779f0_eth_serdes_write32(channel->addr, 0x00c4, 0x180, 0x0310);
+		r8a779f0_eth_serdes_write32(channel->addr, 0x00c8, 0x180, 0x0301);
+		ret = r8a779f0_eth_serdes_reg_wait(channel, 0x00c8, 0x180, BIT(0), 0);
+		if (ret)
+			return ret;
+		r8a779f0_eth_serdes_write32(channel->addr, 0x0148, 0x180, 0x0301);
+		ret = r8a779f0_eth_serdes_reg_wait(channel, 0x0148, 0x180, BIT(0), 0);
+		if (ret)
+			return ret;
+		r8a779f0_eth_serdes_write32(channel->addr, 0x00c4, 0x180, 0x1310);
+		r8a779f0_eth_serdes_write32(channel->addr, 0x00d8, 0x180, 0x1800);
+		r8a779f0_eth_serdes_write32(channel->addr, 0x00dc, 0x180, 0x0000);
+		r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x380, 0x2300);
+		ret = r8a779f0_eth_serdes_reg_wait(channel, 0x0000, 0x380, BIT(8), 0);
+		if (ret)
+			return ret;
+		break;
+
 	default:
 		return -EOPNOTSUPP;
 	}
@@ -179,6 +216,14 @@ r8a779f0_eth_serdes_chan_speed(struct r8a779f0_eth_serdes_channel *channel)
 			return ret;
 		r8a779f0_eth_serdes_write32(channel->addr, 0x0008, 0x1f80, 0x0000);
 		break;
+	case PHY_INTERFACE_MODE_USXGMII:
+		r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x1f00, 0x0120);
+		usleep_range(10, 20);
+		r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x380, 0x2600);
+		ret = r8a779f0_eth_serdes_reg_wait(channel, 0x0000, 0x380, BIT(10), 0);
+		if (ret)
+			return ret;
+		break;
 	default:
 		return -EOPNOTSUPP;
 	}

-- 
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[PATCH v2 2/2] phy: renesas: r8a779f0-ether-serdes: add new step added to latest datasheet

[Michael Dege]

R-Car S4-8 datasheet Rev.1.20 describes some additional register
settings at the end of the initialization.

Signed-off-by: Michael Dege <michael.dege@renesas.com>
---
 drivers/phy/renesas/r8a779f0-ether-serdes.c | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/drivers/phy/renesas/r8a779f0-ether-serdes.c b/drivers/phy/renesas/r8a779f0-ether-serdes.c
index ed83c46f6d00c255852cc5af867c89ab0d0db02a..85a19233f6105e7a309832edee3e6b919eb27eb2 100644
--- a/drivers/phy/renesas/r8a779f0-ether-serdes.c
+++ b/drivers/phy/renesas/r8a779f0-ether-serdes.c
@@ -49,6 +49,13 @@ static void r8a779f0_eth_serdes_write32(void __iomem *addr, u32 offs, u32 bank,
 	iowrite32(data, addr + offs);
 }
 
+static u32 r8a779f0_eth_serdes_read32(void __iomem *addr, u32 offs,  u32 bank)
+{
+	iowrite32(bank, addr + RENESAS_ETH_SERDES_BANK_SELECT);
+
+	return ioread32(addr + offs);
+}
+
 static int
 r8a779f0_eth_serdes_reg_wait(struct r8a779f0_eth_serdes_channel *channel,
 			     u32 offs, u32 bank, u32 mask, u32 expected)
@@ -319,6 +326,7 @@ static int r8a779f0_eth_serdes_hw_init_late(struct r8a779f0_eth_serdes_channel
 *channel)
 {
 	int ret;
+	u32 val;
 
 	ret = r8a779f0_eth_serdes_chan_setting(channel);
 	if (ret)
@@ -332,6 +340,26 @@ static int r8a779f0_eth_serdes_hw_init_late(struct r8a779f0_eth_serdes_channel
 
 	r8a779f0_eth_serdes_write32(channel->addr, 0x03d0, 0x380, 0x0000);
 
+	val = r8a779f0_eth_serdes_read32(channel->addr, 0x00c0, 0x180);
+	r8a779f0_eth_serdes_write32(channel->addr, 0x00c0, 0x180, val | BIT(8));
+	ret = r8a779f0_eth_serdes_reg_wait(channel, 0x0100, 0x180, BIT(0), 1);
+	if (ret)
+		return ret;
+	r8a779f0_eth_serdes_write32(channel->addr, 0x00c0, 0x180, val & ~BIT(8));
+	ret = r8a779f0_eth_serdes_reg_wait(channel, 0x0100, 0x180, BIT(0), 0);
+	if (ret)
+		return ret;
+
+	val = r8a779f0_eth_serdes_read32(channel->addr, 0x0144, 0x180);
+	r8a779f0_eth_serdes_write32(channel->addr, 0x0144, 0x180, val | BIT(4));
+	ret = r8a779f0_eth_serdes_reg_wait(channel, 0x0180, 0x180, BIT(0), 1);
+	if (ret)
+		return ret;
+	r8a779f0_eth_serdes_write32(channel->addr, 0x0144, 0x180, val & ~BIT(4));
+	ret = r8a779f0_eth_serdes_reg_wait(channel, 0x0180, 0x180, BIT(0), 0);
+	if (ret)
+		return ret;
+
 	return r8a779f0_eth_serdes_monitor_linkup(channel);
 }
 

-- 
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Re: [PATCH v2 2/2] phy: renesas: r8a779f0-ether-serdes: add new step added to latest datasheet

[kernel test robot]

Hi Michael,

kernel test robot noticed the following build errors:

[auto build test ERROR on a5806cd506af5a7c19bcd596e4708b5c464bfd21]

url:    https://github.com/intel-lab-lkp/linux/commits/Michael-Dege/phy-renesas-r8a779f0-ether-serdes-add-USXGMII-mode/20250527-150048
base:   a5806cd506af5a7c19bcd596e4708b5c464bfd21
patch link:    https://lore.kernel.org/r/20250527-renesas-serdes-update-v2-2-ef17c71cd94c%40renesas.com
patch subject: [PATCH v2 2/2] phy: renesas: r8a779f0-ether-serdes: add new step added to latest datasheet
config: arc-randconfig-001-20250527 (https://download.01.org/0day-ci/archive/20250527/202505271711.WM48TTTI-lkp@intel.com/config)
compiler: arc-linux-gcc (GCC) 10.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250527/202505271711.WM48TTTI-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202505271711.WM48TTTI-lkp@intel.com/

All errors (new ones prefixed by >>):

   drivers/phy/renesas/r8a779f0-ether-serdes.c: In function 'r8a779f0_eth_serdes_read32':
>> drivers/phy/renesas/r8a779f0-ether-serdes.c:54:25: error: 'RENESAS_ETH_SERDES_BANK_SELECT' undeclared (first use in this function); did you mean 'R8A779F0_ETH_SERDES_BANK_SELECT'?
      54 |  iowrite32(bank, addr + RENESAS_ETH_SERDES_BANK_SELECT);
         |                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
         |                         R8A779F0_ETH_SERDES_BANK_SELECT
   drivers/phy/renesas/r8a779f0-ether-serdes.c:54:25: note: each undeclared identifier is reported only once for each function it appears in


vim +54 drivers/phy/renesas/r8a779f0-ether-serdes.c

    51	
    52	static u32 r8a779f0_eth_serdes_read32(void __iomem *addr, u32 offs,  u32 bank)
    53	{
  > 54		iowrite32(bank, addr + RENESAS_ETH_SERDES_BANK_SELECT);
    55	
    56		return ioread32(addr + offs);
    57	}
    58	

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RE: [PATCH v2 2/2] phy: renesas: r8a779f0-ether-serdes: add new step added to latest datasheet

[Michael Dege]

Hello,

> -----Original Message-----
> From: kernel test robot <lkp@intel.com>
> Sent: Tuesday, May 27, 2025 11:41 AM
> To: Michael Dege <michael.dege@renesas.com>; Vinod Koul <vkoul@kernel.org>; Kishon Vijay Abraham I
> <kishon@kernel.org>; Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> Cc: oe-kbuild-all@lists.linux.dev; Michael Dege <michael.dege@renesas.com>; Uwe Kleine-König
> <u.kleine-koenig@baylibre.com>; linux-phy@lists.infradead.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v2 2/2] phy: renesas: r8a779f0-ether-serdes: add new step added to latest
> datasheet
>
> Hi Michael,
>
> kernel test robot noticed the following build errors:
>
> [auto build test ERROR on a5806cd506af5a7c19bcd596e4708b5c464bfd21]
>
> url:    https://github.com/intel-lab-
> lkp%2Flinux%2Fcommits%2FMichael-Dege%2Fphy-renesas-r8a779f0-ether-serdes-add-USXGMII-mode%2F20250527-
> 150048&data=05%7C02%7Cmichael.dege%40renesas.com%7C8302e9fad5af4162a89e08dd9d02baac%7C53d82571da1947e4
> 9cb4625a166a4a2a%7C0%7C0%7C638839357252567523%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIw
> LjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=%2FImajCm4YD6H2309lF5m
> zmCObCS6%2FpCZMotTI57bteo%3D&reserved=0
> base:   a5806cd506af5a7c19bcd596e4708b5c464bfd21
> patch link:
> https://lore.kernel.org/r/20250527-
> renesas-serdes-update-v2-2-
> ef17c71cd94c%2540renesas.com&data=05%7C02%7Cmichael.dege%40renesas.com%7C8302e9fad5af4162a89e08dd9d02b
> aac%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C638839357252584964%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU
> 1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=
> JzM8KY23Z1AzRSwou%2BkMTRWBkvC6hOaDEDENTTH6GEQ%3D&reserved=0
> patch subject: [PATCH v2 2/2] phy: renesas: r8a779f0-ether-serdes: add new step added to latest
> datasheet
> config: arc-randconfig-001-20250527
> (https://download.01.org/0day-
> ci%2Farchive%2F20250527%2F202505271711.WM48TTTI-
> lkp%40intel.com%2Fconfig&data=05%7C02%7Cmichael.dege%40renesas.com%7C8302e9fad5af4162a89e08dd9d02baac%
> 7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C638839357252595528%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcG
> kiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=8JtB
> v%2BFmcJng5BiSSjnOhSodkQ2dtBH8kQnVQdXBhmo%3D&reserved=0)
> compiler: arc-linux-gcc (GCC) 10.5.0
> reproduce (this is a W=1 build):
> (https://download.01.org/0day-
> ci%2Farchive%2F20250527%2F202505271711.WM48TTTI-
> lkp%40intel.com%2Freproduce&data=05%7C02%7Cmichael.dege%40renesas.com%7C8302e9fad5af4162a89e08dd9d02ba
> ac%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C638839357252606183%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1
> hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=b
> tqrLQmBkVgPbAQ64H1ls6R9%2BQn0WTfNWUVrTApuDjY%3D&reserved=0)
>
> If you fix the issue in a separate patch/commit (i.e. not just a new version of the same
> patch/commit), kindly add following tags
> | Reported-by: kernel test robot <lkp@intel.com>
> | Closes:
> | https://lore/
> | .kernel.org%2Foe-kbuild-all%2F202505271711.WM48TTTI-lkp%40intel.com%2F
> | &data=05%7C02%7Cmichael.dege%40renesas.com%7C8302e9fad5af4162a89e08dd9
> | d02baac%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C63883935725261673
> | 0%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIs
> | IlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=ja
> | r%2FB6U8ENcw71CzP2jduv2gEQrSkOUj%2Fnhf6jcPv5A%3D&reserved=0
>
> All errors (new ones prefixed by >>):

I will fix the issue and send around a new version of the patch set.

>
>    drivers/phy/renesas/r8a779f0-ether-serdes.c: In function 'r8a779f0_eth_serdes_read32':
> >> drivers/phy/renesas/r8a779f0-ether-serdes.c:54:25: error: 'RENESAS_ETH_SERDES_BANK_SELECT'
> undeclared (first use in this function); did you mean 'R8A779F0_ETH_SERDES_BANK_SELECT'?
>       54 |  iowrite32(bank, addr + RENESAS_ETH_SERDES_BANK_SELECT);
>          |                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>          |                         R8A779F0_ETH_SERDES_BANK_SELECT
>    drivers/phy/renesas/r8a779f0-ether-serdes.c:54:25: note: each undeclared identifier is reported
> only once for each function it appears in
>
>
> vim +54 drivers/phy/renesas/r8a779f0-ether-serdes.c
>
>     51
>     52        static u32 r8a779f0_eth_serdes_read32(void __iomem *addr, u32 offs,  u32 bank)
>     53        {
>   > 54                iowrite32(bank, addr + RENESAS_ETH_SERDES_BANK_SELECT);
>     55
>     56                return ioread32(addr + offs);
>     57        }
>     58
>

Thank you and best regards,

Michael
> --
> 0-DAY CI Kernel Test Service
> https://github.com/intel/lkp-
> tests%2Fwiki&data=05%7C02%7Cmichael.dege%40renesas.com%7C8302e9fad5af4162a89e08dd9d02baac%7C53d82571da
> 1947e49cb4625a166a4a2a%7C0%7C0%7C638839357252626902%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIl
> YiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=s8LGQlWaPw4C3ihZ
> 9X6WiQaZWuxKLPlqd0sGv7T8uw8%3D&reserved=0
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