From: Vladimir Oltean <vladimir.oltean@nxp.com>
To: linux-phy@lists.infradead.org
Cc: Ioana Ciornei <ioana.ciornei@nxp.com>,
Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
Josua Mayer <josua@solid-run.com>,
linux-kernel@vger.kernel.org
Subject: [PATCH v4 phy 08/16] phy: lynx-28g: restructure protocol configuration register accesses
Date: Mon, 10 Nov 2025 11:22:33 +0200 [thread overview]
Message-ID: <20251110092241.1306838-9-vladimir.oltean@nxp.com> (raw)
In-Reply-To: <20251110092241.1306838-1-vladimir.oltean@nxp.com>
Eliminate the need to calculate a lane_offset manually, and generate
some macros which access the protocol converter corresponding to the
correct lane in the PCC* registers.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
v1->v4: none
drivers/phy/freescale/phy-fsl-lynx-28g.c | 55 ++++++++++++++----------
1 file changed, 33 insertions(+), 22 deletions(-)
diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c b/drivers/phy/freescale/phy-fsl-lynx-28g.c
index 3b19b7d22b6a..bf06ce42e291 100644
--- a/drivers/phy/freescale/phy-fsl-lynx-28g.c
+++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c
@@ -12,17 +12,32 @@
#define LYNX_28G_NUM_LANE 8
#define LYNX_28G_NUM_PLL 2
+#define LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1))
+
/* General registers per SerDes block */
#define PCC8 0x10a0
-#define PCC8_SGMII 0x1
-#define PCC8_SGMII_DIS 0x0
+#define PCC8_SGMIInCFG(lane, x) (((x) & GENMASK(2, 0)) << LNa_PCC_OFFSET(lane))
+#define PCC8_SGMIInCFG_EN(lane) PCC8_SGMIInCFG(lane, 1)
+#define PCC8_SGMIInCFG_MSK(lane) PCC8_SGMIInCFG(lane, GENMASK(2, 0))
+#define PCC8_SGMIIn_KX(lane, x) ((((x) << 3) & BIT(3)) << LNa_PCC_OFFSET(lane))
+#define PCC8_SGMIIn_KX_MSK(lane) PCC8_SGMIIn_KX(lane, 1)
+#define PCC8_MSK(lane) PCC8_SGMIInCFG_MSK(lane) | \
+ PCC8_SGMIIn_KX_MSK(lane)
#define PCCC 0x10b0
-#define PCCC_10GBASER 0x9
-#define PCCC_USXGMII 0x1
-#define PCCC_SXGMII_DIS 0x0
-
-#define LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1))
+#define PCCC_SXGMIInCFG(lane, x) (((x) & GENMASK(2, 0)) << LNa_PCC_OFFSET(lane))
+#define PCCC_SXGMIInCFG_EN(lane) PCCC_SXGMIInCFG(lane, 1)
+#define PCCC_SXGMIInCFG_MSK(lane) PCCC_SXGMIInCFG(lane, GENMASK(2, 0))
+#define PCCC_SXGMIInCFG_XFI(lane, x) ((((x) << 3) & BIT(3)) << LNa_PCC_OFFSET(lane))
+#define PCCC_SXGMIInCFG_XFI_MSK(lane) PCCC_SXGMIInCFG_XFI(lane, 1)
+#define PCCC_MSK(lane) PCCC_SXGMIInCFG_MSK(lane) | \
+ PCCC_SXGMIInCFG_XFI_MSK(lane)
+
+#define PCCD 0x10b4
+#define PCCD_E25GnCFG(lane, x) (((x) & GENMASK(2, 0)) << LNa_PCCD_OFFSET(lane))
+#define PCCD_E25GnCFG_EN(lane) PCCD_E25GnCFG(lane, 1)
+#define PCCD_E25GnCFG_MSK(lane) PCCD_E25GnCFG(lane, GENMASK(2, 0))
+#define PCCD_MSK(lane) PCCD_E25GnCFG_MSK(lane)
/* Per PLL registers */
#define PLLnRSTCTL(pll) (0x400 + (pll) * 0x100 + 0x0)
@@ -314,20 +329,21 @@ static void lynx_28g_lane_set_pll(struct lynx_28g_lane *lane,
static void lynx_28g_cleanup_lane(struct lynx_28g_lane *lane)
{
struct lynx_28g_priv *priv = lane->priv;
- u32 lane_offset = LNa_PCC_OFFSET(lane);
/* Cleanup the protocol configuration registers of the current protocol */
switch (lane->interface) {
case PHY_INTERFACE_MODE_10GBASER:
- lynx_28g_rmw(priv, PCCC,
- PCCC_SXGMII_DIS << lane_offset,
- GENMASK(3, 0) << lane_offset);
+ /* Cleanup the protocol configuration registers */
+ lynx_28g_rmw(priv, PCCC, 0, PCCC_MSK(lane));
break;
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_1000BASEX:
- lynx_28g_rmw(priv, PCC8,
- PCC8_SGMII_DIS << lane_offset,
- GENMASK(3, 0) << lane_offset);
+ /* Cleanup the protocol configuration registers */
+ lynx_28g_rmw(priv, PCC8, 0, PCC8_MSK(lane));
+
+ /* Disable the SGMII PCS */
+ lynx_28g_lane_rmw(lane, SGMIIaCR1, 0, SGMIIaCR1_SGPCS_EN);
+
break;
default:
break;
@@ -336,16 +352,13 @@ static void lynx_28g_cleanup_lane(struct lynx_28g_lane *lane)
static void lynx_28g_lane_set_sgmii(struct lynx_28g_lane *lane)
{
- u32 lane_offset = LNa_PCC_OFFSET(lane);
struct lynx_28g_priv *priv = lane->priv;
struct lynx_28g_pll *pll;
lynx_28g_cleanup_lane(lane);
/* Setup the lane to run in SGMII */
- lynx_28g_rmw(priv, PCC8,
- PCC8_SGMII << lane_offset,
- GENMASK(3, 0) << lane_offset);
+ lynx_28g_rmw(priv, PCC8, PCC8_SGMIInCFG_EN(lane), PCC8_MSK(lane));
/* Setup the protocol select and SerDes parallel interface width */
lynx_28g_lane_rmw(lane, LNaGCR0,
@@ -390,15 +403,13 @@ static void lynx_28g_lane_set_sgmii(struct lynx_28g_lane *lane)
static void lynx_28g_lane_set_10gbaser(struct lynx_28g_lane *lane)
{
struct lynx_28g_priv *priv = lane->priv;
- u32 lane_offset = LNa_PCC_OFFSET(lane);
struct lynx_28g_pll *pll;
lynx_28g_cleanup_lane(lane);
/* Enable the SXGMII lane */
- lynx_28g_rmw(priv, PCCC,
- PCCC_10GBASER << lane_offset,
- GENMASK(3, 0) << lane_offset);
+ lynx_28g_rmw(priv, PCCC, PCCC_SXGMIInCFG_EN(lane) |
+ PCCC_SXGMIInCFG_XFI(lane, 1), PCCC_MSK(lane));
/* Setup the protocol select and SerDes parallel interface width */
lynx_28g_lane_rmw(lane, LNaGCR0,
--
2.34.1
--
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next prev parent reply other threads:[~2025-11-10 9:23 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-10 9:22 [PATCH v4 phy 00/16] Lynx 28G improvements part 1 Vladimir Oltean
2025-11-10 9:22 ` [PATCH v4 phy 01/16] dt-bindings: phy: lynx-28g: permit lane OF PHY providers Vladimir Oltean
2025-11-12 16:20 ` Rob Herring (Arm)
2025-11-13 16:46 ` Vinod Koul
2025-11-13 16:54 ` Vladimir Oltean
2025-11-10 9:22 ` [PATCH v4 phy 02/16] phy: lynx-28g: refactor lane probing to lynx_28g_probe_lane() Vladimir Oltean
2025-11-13 16:49 ` Vinod Koul
2025-11-13 16:56 ` Vladimir Oltean
2025-11-17 18:57 ` Vladimir Oltean
2025-11-10 9:22 ` [PATCH v4 phy 03/16] phy: lynx-28g: support individual lanes as OF PHY providers Vladimir Oltean
2025-11-10 9:22 ` [PATCH v4 phy 04/16] phy: lynx-28g: remove LYNX_28G_ prefix from register names Vladimir Oltean
2025-11-10 9:22 ` [PATCH v4 phy 05/16] phy: lynx-28g: don't concatenate lynx_28g_lane_rmw() argument "reg" with "val" and "mask" Vladimir Oltean
2025-11-10 9:22 ` [PATCH v4 phy 06/16] phy: lynx-28g: use FIELD_GET() and FIELD_PREP() Vladimir Oltean
2025-11-10 9:22 ` [PATCH v4 phy 07/16] phy: lynx-28g: convert iowrite32() calls with magic values to macros Vladimir Oltean
2025-11-10 9:22 ` Vladimir Oltean [this message]
2025-11-10 9:22 ` [PATCH v4 phy 09/16] phy: lynx-28g: make lynx_28g_set_lane_mode() more systematic Vladimir Oltean
2025-11-10 9:22 ` [PATCH v4 phy 10/16] phy: lynx-28g: refactor lane->interface to lane->mode Vladimir Oltean
2025-11-10 9:22 ` [PATCH v4 phy 11/16] phy: lynx-28g: distinguish between 10GBASE-R and USXGMII Vladimir Oltean
2025-11-10 9:22 ` [PATCH v4 phy 12/16] phy: lynx-28g: configure more equalization params for 1GbE and 10GbE Vladimir Oltean
2025-11-10 9:22 ` [PATCH v4 phy 13/16] phy: lynx-28g: use "dev" argument more in lynx_28g_probe() Vladimir Oltean
2025-11-10 9:22 ` [PATCH v4 phy 14/16] phy: lynx-28g: improve lynx_28g_probe() sequence Vladimir Oltean
2025-11-10 9:22 ` [PATCH v4 phy 15/16] dt-bindings: phy: lynx-28g: add compatible strings per SerDes and instantiation Vladimir Oltean
2025-11-10 10:29 ` Rob Herring (Arm)
2025-11-10 11:58 ` Vladimir Oltean
2025-11-10 9:22 ` [PATCH v4 phy 16/16] phy: lynx-28g: probe on per-SoC and per-instance compatible strings Vladimir Oltean
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