From: Vladimir Oltean <vladimir.oltean@nxp.com>
To: sashiko-reviews@lists.linux.dev
Cc: robh@kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org,
neil.armstrong@linaro.org, linux-phy@lists.infradead.org,
olteanv@gmail.com, vkoul@kernel.org
Subject: Re: [PATCH phy-next 01/13] dt-bindings: phy: lynx-10g: initial document
Date: Fri, 29 May 2026 15:50:17 +0300 [thread overview]
Message-ID: <20260529125017.ifqunh52gdzhthdg@skbuf> (raw)
In-Reply-To: <20260528174508.bqu6ks4rgkysvgdg@skbuf>
On Thu, May 28, 2026 at 08:45:08PM +0300, Vladimir Oltean wrote:
> On Thu, May 28, 2026 at 05:40:44PM +0000, sashiko-bot@kernel.org wrote:
> > Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> > - [Low] Invalid JSON Schema syntax for the `reg` property constraint.
> > --
> >
> > commit e219405276839837989c30627d109ff39c15e361
> > Author: Vladimir Oltean <vladimir.oltean@nxp.com>
> >
> > dt-bindings: phy: lynx-10g: initial document
> >
> > This commit adds a new device tree binding schema for the 10G Lynx SerDes.
> > It defines the register map constraints and allows flexibility for the
> > #phy-cells property.
> >
> > > diff --git a/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml b/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml
> > > new file mode 100644
> > > index 0000000000000..993f076bba4e6
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml
> > [ ... ]
> > > patternProperties:
> > > "^phy@[0-7]$":
> > > type: object
> > > description: SerDes lane (single RX/TX differential pair)
> > >
> > > properties:
> > > reg:
> > > minimum: 0
> > > maximum: 7
> >
> > [Severity: Low]
> > Will this cause a meta-schema validation error during make dt_binding_check?
> >
> > The reg property is parsed as an array type by dt-schema. Applying minimum
> > and maximum directly to an array property is invalid in JSON Schema, as those
> > keywords are only applicable to numeric types.
> >
> > Should these constraints be wrapped inside an items list?
> >
> > [ ... ]
> > > allOf:
> > > - if:
> > > properties:
> > > compatible:
> > > contains:
> > > enum:
> > > - fsl,ls1028a-serdes
> > > - fsl,ls1046a-serdes1
> > > - fsl,ls1046a-serdes2
> > > - fsl,ls1088a-serdes1
> > > - fsl,ls1088a-serdes2
> > > then:
> > > patternProperties:
> > > "^phy@[0-7]$":
> > > properties:
> > > reg:
> > > minimum: 0
> > > maximum: 3
> >
> > [Severity: Low]
> > Could the same meta-schema validation issue occur here?
> >
> > Since reg is an array, perhaps this constraint would be better enforced by
> > rejecting invalid unit addresses in the then clause entirely, for example,
> > by setting "^phy@[4-7]$": false?
> >
> > --
> > Sashiko AI review · https://sashiko.dev/#/patchset/20260528172404.733196-1-vladimir.oltean@nxp.com?part=1
>
> We have the same pattern in fsl,lynx-28g.yaml and it didn't cause schema
> validation failures there.
Yes, so the dt_binding_check test passed fine:
https://patchwork.kernel.org/project/linux-phy/patch/20260528172404.733196-2-vladimir.oltean@nxp.com/
I will not be making any change to this patch in response to this LLM
feedback, just humans.
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
next prev parent reply other threads:[~2026-05-29 12:50 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-28 17:23 [PATCH phy-next 00/13] New Generic PHY driver for Lynx 10G SerDes Vladimir Oltean
2026-05-28 17:23 ` [PATCH phy-next 01/13] dt-bindings: phy: lynx-10g: initial document Vladimir Oltean
2026-05-28 17:40 ` sashiko-bot
2026-05-28 17:45 ` Vladimir Oltean
2026-05-29 12:50 ` Vladimir Oltean [this message]
2026-06-05 19:04 ` Rob Herring (Arm)
2026-05-28 17:23 ` [PATCH phy-next 02/13] phy: lynx-28g: move lane mode helpers to new core module Vladimir Oltean
2026-05-28 17:23 ` [PATCH phy-next 03/13] phy: lynx-28g: move data structures to core Vladimir Oltean
2026-05-28 17:23 ` [PATCH phy-next 04/13] phy: lynx-28g: common lynx_pll_get() Vladimir Oltean
2026-05-28 17:23 ` [PATCH phy-next 05/13] phy: lynx-28g: generalize protocol converter accessors Vladimir Oltean
2026-05-28 17:23 ` [PATCH phy-next 06/13] phy: lynx-28g: provide default lynx_lane_supports_mode() implementation Vladimir Oltean
2026-05-28 17:23 ` [PATCH phy-next 07/13] phy: lynx-28g: move struct lynx_info definitions downwards Vladimir Oltean
2026-05-28 17:23 ` [PATCH phy-next 08/13] phy: lynx-28g: make lynx_28g_pll_read_configuration() callable per PLL Vladimir Oltean
2026-05-28 17:46 ` sashiko-bot
2026-05-28 17:24 ` [PATCH phy-next 09/13] phy: lynx-28g: common probe() and remove() Vladimir Oltean
2026-05-28 18:02 ` sashiko-bot
2026-05-29 12:47 ` Vladimir Oltean
2026-05-28 17:24 ` [PATCH phy-next 10/13] phy: lynx-28g: add support for big endian register maps Vladimir Oltean
2026-05-28 17:47 ` sashiko-bot
2026-05-29 12:00 ` Vladimir Oltean
2026-05-28 17:24 ` [PATCH phy-next 11/13] phy: lynx-28g: optimize read-modify-write operation Vladimir Oltean
2026-05-28 17:24 ` [PATCH phy-next 12/13] phy: lynx-10g: new driver Vladimir Oltean
2026-05-28 18:20 ` sashiko-bot
2026-05-29 12:34 ` Vladimir Oltean
2026-05-28 17:24 ` [PATCH phy-next 13/13] MAINTAINERS: expand Lynx 28G entry to cover Lynx 10G SerDes Vladimir Oltean
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