Re: [PATCH v2 phy-next 13/15] dt-bindings: phy: lynx-10g: initial document

[Vladimir Oltean <vladimir.oltean@nxp.com>]

On Tue, Jun 02, 2026 at 06:10:30PM +0100, Conor Dooley wrote:
> On Fri, May 29, 2026 at 08:15:07PM +0300, Vladimir Oltean wrote:
> > Add a schema for the 10G Lynx SerDes. This is very similar to the modern
> > form of the 28G Lynx SerDes, which is very much the intention.
> > 
> > We allow both forms of #phy-cells = <1> in the top-level provider
> > and #phy-cells = <0> in the per-lane provider for more flexibility to
> > consumers, and because the kernel code is shared with the 28G Lynx which
> > already has that support for compatibility reasons.
> > 
> > Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> > ---
> > Cc: devicetree@vger.kernel.org
> > Cc: Conor Dooley <conor+dt@kernel.org>
> > Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
> > Cc: Rob Herring <robh@kernel.org>
> > 
> > v1->v2:
> > - move patch later in series, right before driver
> > - deliberately ignoring this Sashiko feedback:
> >   https://lore.kernel.org/linux-phy/20260529125017.ifqunh52gdzhthdg@skbuf/
> > ---
> >  .../devicetree/bindings/phy/fsl,lynx-10g.yaml | 131 ++++++++++++++++++
> >  1 file changed, 131 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml b/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml
> > new file mode 100644
> > index 000000000000..993f076bba4e
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml
> > @@ -0,0 +1,131 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/phy/fsl,lynx-10g.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Freescale Lynx 10G SerDes PHY
> > +
> > +maintainers:
> > +  - Vladimir Oltean <vladimir.oltean@nxp.com>
> > +
> > +description:
> > +  The 10G Lynx is a multi-protocol SerDes block which handles networking, PCIe,
> > +  SATA and other high-speed interfaces. It is present on most QorIQ and
> > +  Layerscape SoCs. The register map is common, but the integration is
> > +  SoC-specific, with the differences consisting in register endianness, the
> > +  number of lanes, protocol converters available per lane and their location in
> > +  the PCCR registers. Some SoCs have multiple SerDes blocks and those differ in
> > +  their protocol capabilities per lane.
> > +
> > +properties:
> > +  compatible:
> > +    description:
> > +      There is intentionally no generic fsl,lynx-10g compatible string due to
> > +      the hardware inability to report its capabilities, despite having a
> > +      common register map.
> 
> I think you can probably drop this from the diff, and put it in the
> commit message.

Ok.

> > +    enum:
> > +      - fsl,ls1028a-serdes
> > +      - fsl,ls1046a-serdes1
> > +      - fsl,ls1046a-serdes2
> > +      - fsl,ls1088a-serdes1
> > +      - fsl,ls1088a-serdes2
> > +      - fsl,ls2088a-serdes1
> > +      - fsl,ls2088a-serdes2
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  big-endian: true
> 
> This isn't a required property, but should it be made required for the
> specific compatibles that are big endian? Or are we not that lucky, and
> devices can be either?

I can make big-endian a required property for fsl,ls1046a-serdes1 and
fsl,ls1046a-serdes2.

Thanks for the review!

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