From: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
To: "Vinod Koul" <vkoul@kernel.org>,
"Neil Armstrong" <neil.armstrong@linaro.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Bjorn Andersson" <andersson@kernel.org>,
"Chaitanya Chundru" <krishna.chundru@oss.qualcomm.com>,
"Bartosz Golaszewski" <brgl@kernel.org>,
"Konrad Dybcio" <konradybcio@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pci@vger.kernel.org,
Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
Subject: [PATCH 8/9] arm64: dts: qcom: shikra-evk: Add TC9563 PCIe switch node for PCIe
Date: Wed, 01 Jul 2026 00:32:50 +0530 [thread overview]
Message-ID: <20260701-shikra-upstream-v1-8-e1a721eb8943@oss.qualcomm.com> (raw)
In-Reply-To: <20260701-shikra-upstream-v1-0-e1a721eb8943@oss.qualcomm.com>
Add a node for the TC9563 PCIe switch connected to PCIe. The switch
has three downstream ports.Two embedded Ethernet devices are present
on one of the downstream ports. All the ports present in the
node represent the downstream ports and embedded endpoints.
Power to the TC9563 is supplied through two LDO regulators, which
are on by default and are added as fixed regulators. TC9563 can be
configured through I2C.
Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra-evk.dtsi | 152 +++++++++++++++++++++++++++++++
1 file changed, 152 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra-evk.dtsi b/arch/arm64/boot/dts/qcom/shikra-evk.dtsi
index 5411f22426b7..b6d24fe5fb61 100644
--- a/arch/arm64/boot/dts/qcom/shikra-evk.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra-evk.dtsi
@@ -3,6 +3,136 @@
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
+/ {
+ aliases {
+ i2c3 = &i2c3;
+ };
+
+ vreg_0p9: regulator-0v9 {
+ compatible = "regulator-fixed";
+ regulator-name = "VREG_0P9";
+
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vreg_1p8: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VREG_1P8";
+
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&pcie {
+ wake-gpios = <&tlmm 119 GPIO_ACTIVE_LOW>;
+
+ iommu-map = <0x0 &apps_smmu 0x0800 0x1>,
+ <0x100 &apps_smmu 0x0801 0x1>,
+ <0x208 &apps_smmu 0x0802 0x1>,
+ <0x210 &apps_smmu 0x0803 0x1>,
+ <0x218 &apps_smmu 0x0804 0x1>,
+ <0x300 &apps_smmu 0x0805 0x1>,
+ <0x400 &apps_smmu 0x0806 0x1>,
+ <0x500 &apps_smmu 0x0807 0x1>,
+ <0x501 &apps_smmu 0x0808 0x1>;
+
+ pinctrl-0 = <&pcie_default_state>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie_port0 {
+
+ tc9563: pcie@0,0 {
+ compatible = "pci1179,0623";
+ reg = <0x10000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x2 0xff>;
+
+ vddc-supply = <&vreg_0p9>;
+ vdd18-supply = <&vreg_1p8>;
+ vdd09-supply = <&vreg_0p9>;
+ vddio1-supply = <&vreg_1p8>;
+ vddio2-supply = <&vreg_1p8>;
+ vddio18-supply = <&vreg_1p8>;
+
+ i2c-parent = <&i2c3 0x77>;
+
+ resx-gpios = <&tlmm 118 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&tc9563_resx_n>;
+ pinctrl-names = "default";
+
+ pcie@1,0 {
+ reg = <0x20800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x3 0xff>;
+
+ ep-pwr-en-gpios = <&tc9563 2 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&tc9563 5 GPIO_ACTIVE_LOW>;
+ };
+
+ pcie@2,0 {
+ reg = <0x21000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x4 0xff>;
+
+ ep-pwr-en-gpios = <&tc9563 4 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&tc9563 3 GPIO_ACTIVE_LOW>;
+ };
+
+ pcie@3,0 {
+ reg = <0x21800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ bus-range = <0x5 0xff>;
+
+ pci@0,0 {
+ reg = <0x50000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ };
+
+ pci@0,1 {
+ reg = <0x50100 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ };
+ };
+ };
+};
+
&qupv3_0 {
firmware-name = "qcom/shikra/qupv3fw.elf";
@@ -10,11 +140,33 @@ &qupv3_0 {
};
&tlmm {
+ pcie_default_state: pcie-default-state {
+ clkreq-pins {
+ pins = "gpio117";
+ function = "pcie0_clk_req_n";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake-pins {
+ pins = "gpio119";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
sw_ctrl_default: sw-ctrl-default-state {
pins = "gpio88";
function = "gpio";
bias-pull-down;
};
+
+ tc9563_resx_n: tc9563-resx-state {
+ pins = "gpio118";
+ function = "gpio";
+ bias-disable;
+ };
};
&uart0 {
--
2.43.0
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
next prev parent reply other threads:[~2026-06-30 19:04 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-30 19:02 [PATCH 0/9] PCI: qcom: Add PCIe support for Shikra SoC Sushrut Shree Trivedi
2026-06-30 19:02 ` [PATCH 1/9] dt-bindings: phy: sc8280xp-qmp-pcie: Document Shikra PCIe phy Sushrut Shree Trivedi
2026-07-01 9:50 ` Bartosz Golaszewski
2026-06-30 19:02 ` [PATCH 2/9] dt-bindings: PCI: qcom: Document the Shikra PCIe Controller Sushrut Shree Trivedi
2026-06-30 19:18 ` Bjorn Helgaas
2026-06-30 20:35 ` Rob Herring (Arm)
2026-07-07 5:41 ` Sushrut Shree Trivedi
2026-07-01 6:26 ` Krzysztof Kozlowski
2026-07-07 5:29 ` Sushrut Shree Trivedi
2026-07-07 6:01 ` Manivannan Sadhasivam
2026-06-30 19:02 ` [PATCH 3/9] dt-bindings: PCI: Add bindings for endpoint gpios Sushrut Shree Trivedi
2026-06-30 19:22 ` Bjorn Helgaas
2026-07-07 5:39 ` Sushrut Shree Trivedi
2026-06-30 20:35 ` Rob Herring (Arm)
2026-07-07 5:42 ` Sushrut Shree Trivedi
2026-07-01 6:27 ` Krzysztof Kozlowski
2026-07-07 5:26 ` Sushrut Shree Trivedi
2026-07-07 6:48 ` Manivannan Sadhasivam
2026-06-30 19:02 ` [PATCH 4/9] PCI: qcom: Add support for Shikra Sushrut Shree Trivedi
2026-07-01 9:51 ` Bartosz Golaszewski
2026-06-30 19:02 ` [PATCH 5/9] phy: qcom: qmp-pcie: Add QMP PCIe PHY " Sushrut Shree Trivedi
2026-06-30 19:02 ` [PATCH 6/9] PCI/pwrctrl: tc9563: Add API to control endpoint power and reset Sushrut Shree Trivedi
2026-06-30 19:28 ` Bjorn Helgaas
2026-07-07 5:40 ` Sushrut Shree Trivedi
2026-06-30 19:02 ` [PATCH 7/9] arm64: dts: qcom: shikra: Add PCIe PHY and controller nodes Sushrut Shree Trivedi
2026-06-30 19:29 ` Bjorn Helgaas
2026-07-07 5:40 ` Sushrut Shree Trivedi
2026-07-01 10:34 ` Konrad Dybcio
2026-07-07 5:23 ` Sushrut Shree Trivedi
2026-06-30 19:02 ` Sushrut Shree Trivedi [this message]
2026-06-30 19:30 ` [PATCH 8/9] arm64: dts: qcom: shikra-evk: Add TC9563 PCIe switch node for PCIe Bjorn Helgaas
2026-07-07 5:41 ` Sushrut Shree Trivedi
2026-07-01 10:35 ` Konrad Dybcio
2026-07-07 5:22 ` Sushrut Shree Trivedi
2026-06-30 19:02 ` [PATCH 9/9] arm64: dts: qcom: shikra-(cqm/cqs/iqs)-evk: Enable PCIe PHY node Sushrut Shree Trivedi
2026-07-01 10:36 ` Konrad Dybcio
2026-07-07 5:21 ` Sushrut Shree Trivedi
2026-07-08 8:02 ` [PATCH 0/9] PCI: qcom: Add PCIe support for Shikra SoC Manivannan Sadhasivam
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