From: Andrew Lunn <andrew@lunn.ch>
To: Siddharth Vadapalli <s-vadapalli@ti.com>
Cc: vkoul@kernel.org, neil.armstrong@linaro.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, sjakhade@cadence.com,
rogerq@kernel.org, thomas.richard@bootlin.com,
linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
srk@ti.com
Subject: Re: [PATCH v3 2/2] phy: cadence-torrent: Add PCIe + XAUI multilink configuration for 100MHz refclk
Date: Mon, 12 Jan 2026 14:05:10 +0100 [thread overview]
Message-ID: <38da25fd-a402-4b34-8131-0655bccc1953@lunn.ch> (raw)
In-Reply-To: <20260112054636.108027-3-s-vadapalli@ti.com>
On Mon, Jan 12, 2026 at 11:16:31AM +0530, Siddharth Vadapalli wrote:
> From: Swapnil Jakhade <sjakhade@cadence.com>
>
> Add register sequences for PCIe + XAUI multilink configuration for
> 100MHz reference clock.
>
> The register sequences are fetched from a table by indexing entries based
> on unique 'keys' generated by the Bitwise OR defined below:
> REFCLK0_RATE | REFCLK1_RATE | LINK0_TYPE | LINK1_TYPE | SSC_TYPE
>
> As of now, LINK_TYPE is a 3-bit value corresponding to the PHY type.
> With the introduction of TYPE_XAUI, we need a 4-bit value to represent
> the LINK_TYPE as TYPE_XAUI has the numerical value 8. Hence, extend the
> LINKx_MASK macros to 4-bit masks. While at it, extend REFCLKx_MASK macros
> as well to 4-bit masks to support reference clock frequencies that will be
> added in the future.
>
> Adjust the 'LINKx_SHIFT' and the 'REFCLKx_SHIFT' macros to account for
> the aforementioned changes made to the masks.
>
> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
> [s-vadapalli: elaborated on changes made to macros in the commit message]
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
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next prev parent reply other threads:[~2026-01-12 13:05 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-12 5:46 [PATCH v3 0/2] Cadence: Torrent: Enable PCIe + XAUI multilink configuration Siddharth Vadapalli
2026-01-12 5:46 ` [PATCH v3 1/2] dt-bindings: phy: Add PHY_TYPE_XAUI definition Siddharth Vadapalli
2026-01-12 5:46 ` [PATCH v3 2/2] phy: cadence-torrent: Add PCIe + XAUI multilink configuration for 100MHz refclk Siddharth Vadapalli
2026-01-12 13:05 ` Andrew Lunn [this message]
2026-01-14 14:01 ` [PATCH v3 0/2] Cadence: Torrent: Enable PCIe + XAUI multilink configuration Vinod Koul
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