Re: Lynx 10G SerDes Driver on my kernel

[Tanjeff Moos <Tanjeff.Moos@westermo.com>]

On 12/3/25 13:26, Vladimir Oltean wrote:
> On Wed, Dec 03, 2025 at 12:41:16PM +0100, Tanjeff Moos wrote:
>> I created the patches for kernel 5.15.167, and they do not apply on
>> v6.6.110. Instead of reworking my patch, I'd rather use your work, which
>> is much cleaner. Also I hope that it supports switching between SGMII
>> and XFI, which would allow our "fast" variant to support all speeds from
>> 100M to 10G.
> 
> The intention, based on hardware capabilities, is for the SerDes driver
> to read the PLL clock net frequencies at probe time, and build for each
> of the 2 PLLs a list of supported SerDes protocols.
> 
> The phy_validate() API function is supposed to return which SerDes protocols
> can be used on a particular lane. Phylink in particular uses this
> information to build its phylink_config :: supported_interfaces map.
> 
> In the SerDes, each lane can be reconfigured to use the clock net
> provided by PLLF or PLLS ("F" = first, "S" - second), further divided or
> multiplied by a configurable power of 2 factor.
> 
> Furthermore, each lane may support only a subset of SerDes protocols
> that its PLL selection can support (depending which protocol converters
> are instantiated on it).
> 
> For LS1046A, lanes 2 and 3 have all the required protocol converters to
> support LANE_MODE_1000BASEX_SGMII, LANE_MODE_2500BASEX and LANE_MODE_10GBASER:
> https://github.com/nxp-qoriq/linux/blob/lf-6.12.34-2.1.0/drivers/phy/freescale/phy-fsl-lynx-10g.c#L774-L790
>
> but there is an incompatibility between your use case and the PLL frequencies.
> Each SerDes protocol requires a different clock net frequency:
> - LANE_MODE_1000BASEX_SGMII requires PLLnCR0_FRATE_5G
> - LANE_MODE_2500BASEX requires PLLnCR0_FRATE_3_125G
> - LANE_MODE_10GBASER requires PLLnCR0_FRATE_5_15625G
> https://github.com/nxp-qoriq/linux/blob/lf-6.12.34-2.1.0/drivers/phy/freescale/phy-fsl-lynx-10g.c#L2273-L2298
According to LS1046ARM [1] SGMII requires 1.25 Gbps. I don't understand 
where the 5 GHz comes from. I believe I am missing some knowledge here.

> The problem is that 2 PLLs can't provide 3 distinct clock net frequencies.
> So you can either support 1G and 2.5G, or 1G and 10G, or 2.5G and 10G.
According to table 31-4 "Valid SerDes RCW Encodings and Reference 
Clocks" (page 1919):
- SGMII can be used with PLL=100 MHz or PLL=125 MHZ
- 2.5G SGMII can be used with PLL=125 MHz or PLL=156.25 MHZ
- XFI can be used with PLL=156.25 MHZ
My clocks receive the following frequencies (on all devices, "fast" and 
"slow"):
- PLL 1: 125 MHz
- PLL 2: 156.25 MHz
By choosing the right PLL I can use SGMII, 2.5G SGMII or XFI, which I 
actually do. It is possible to freely assign PLL 1 or PLL 2 to any lane 
using LNxGCR0[RPLL_LES].

> Reading your message carefully, it seems that you aren't requesting the
> "fast" Ethernet device to support the 2.5G media speed via LANE_MODE_2500BASEX,
> because that isn't going to be possible.
Correct.

> You are just requesting to support the 10G, 5G and 2.5G media speeds via
> LANE_MODE_10GBASER (with pause-based rate adaptation in the Ethernet PHY),
> and the 1G and 100M media speeds via LANE_MODE_1000BASEX_SGMII.
Yes, that is my minimum target. I hoped that the "fast" device can 
support all speeds, but it's not mandatory.

> That second case *is* going to be possible, provided that your PLL clock
> net frequencies are properly provisioned.
>
> Look at the output from lynx_10g_pll_dump() to avoid any unpleasant
> surprises. It should tell you that PLLF supports LANE_MODE_1000BASEX_SGMII,
> and PLLS supports LANE_MODE_10GBASER. If it doesn't, you need to make
> changes to your hardware design.
I will, thank you.

Kind regards, Tanjeff

[1] LS1046A Reference Manual, LS1046ARM, Rev. 3, 08/2021

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