[PATCH 00/18] Add USB2.0 support for RZ/G3E

[PATCH 00/18] Add USB2.0 support for RZ/G3E

[Tommaso Merciai]

Dear All,

This patch series adds USB2.0 support for the Renesas R9A09G047 (RZ/G3E)
SoC and enables it on the RZ/G3E SMARC II board.
The RZ/G3E USB2.0 IP is identical to that used in the RZ/V2H (R9A09G057),
so the existing support has been extended accordingly.

The series applies on top of [1] and [2] and includes driver cleanups,
VBUS/OTG handling fixes, regulator improvements, clock/reset additions,
and device tree updates for RZ/G3E, RZ/V2H, and RZ/V2N SoCs and boards.

Thanks & Regards,
Tommaso

[1] https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=1001788
[2] https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=1006104

Tommaso Merciai (18):
  phy: renesas: rcar-gen3-usb2: Use devm_pm_runtime_enable()
  phy: renesas: rcar-gen3-usb2: Factor out VBUS control logic
  reset: rzv2h-usb2phy: Simplify pm_runtime driver handling
  reset: rzv2h-usb2phy: Set VBENCTL register for OTG mode
  dt-bindings: phy: renesas,usb2-phy: Document USB VBUS regulator
  phy: renesas: rcar-gen3-usb2: Add regulator for OTG VBUS control
  regulator: devres: Disable exclusive regulator before releasing
  dt-bindings: clock: renesas,r9a09g047-cpg: Add USB2 PHY core clocks
  clk: renesas: r9a09g047: Add clock and reset entries for USB2
  dt-bindings: usb: renesas,usbhs: Add RZ/G3E SoC support
  dt-bindings: phy: renesas,usb2-phy: Document RZ/G3E SoC
  dt-bindings: reset: Document RZ/G3E USB2PHY reset
  arm64: dts: renesas: r9a09g056: Add USB2.0 PHY VBUS internal regulator
    node
  arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable USB2 PHY0 VBUS
    support
  arm64: dts: renesas: r9a09g057: Add USB2.0 PHY VBUS internal regulator
    node
  arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable USB2 PHY0 VBUS
    support
  arm64: dts: renesas: r9a09g047: Add USB2.0 support
  arm64: dts: renesas: r9a09g047e57-smarc: Enable USB2.0 support

 .../bindings/phy/renesas,usb2-phy.yaml        |  10 +-
 .../reset/renesas,rzv2h-usb2phy-reset.yaml    |   4 +-
 .../bindings/usb/renesas,usbhs.yaml           |   1 +
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi    | 122 +++++++++++
 .../boot/dts/renesas/r9a09g047e57-smarc.dts   |  49 +++++
 arch/arm64/boot/dts/renesas/r9a09g056.dtsi    |   6 +
 .../dts/renesas/r9a09g056n48-rzv2n-evk.dts    |   5 +
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi    |   6 +
 .../dts/renesas/r9a09g057h44-rzv2h-evk.dts    |   5 +
 .../boot/dts/renesas/renesas-smarc2.dtsi      |  23 ++
 drivers/clk/renesas/r9a09g047-cpg.c           |  18 +-
 drivers/phy/renesas/phy-rcar-gen3-usb2.c      | 199 +++++++++++++-----
 drivers/regulator/devres.c                    |   8 +-
 drivers/reset/reset-rzv2h-usb2phy.c           | 105 ++++++---
 .../dt-bindings/clock/renesas,r9a09g047-cpg.h |   2 +
 15 files changed, 478 insertions(+), 85 deletions(-)

-- 
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[PATCH 01/18] phy: renesas: rcar-gen3-usb2: Use devm_pm_runtime_enable()

[Tommaso Merciai]

Replace pm_runtime_enable() with devm_pm_runtime_enable() to ensure proper
cleanup if the probe fails. This change enhances driver reliability by
avoiding resource leaks, as the devm-managed version automatically handles
disabling at probe failure or device removal.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 drivers/phy/renesas/phy-rcar-gen3-usb2.c | 53 ++++++++++--------------
 1 file changed, 21 insertions(+), 32 deletions(-)

diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
index 150423dbb1f2..38b49ceb5ff3 100644
--- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
+++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
@@ -850,13 +850,13 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
 	 * devm_phy_create() will call pm_runtime_enable(&phy->dev);
 	 * And then, phy-core will manage runtime pm for this device.
 	 */
-	pm_runtime_enable(dev);
+	ret = devm_pm_runtime_enable(dev);
+	if (ret)
+		return dev_err_probe(dev, ret, "Failed to enable pm_runtime\n");
 
 	channel->phy_data = of_device_get_match_data(dev);
-	if (!channel->phy_data) {
-		ret = -EINVAL;
-		goto error;
-	}
+	if (!channel->phy_data)
+		return -EINVAL;
 
 	platform_set_drvdata(pdev, channel);
 	channel->dev = dev;
@@ -864,18 +864,17 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
 	if (channel->phy_data->init_bus) {
 		ret = rcar_gen3_phy_usb2_init_bus(channel);
 		if (ret)
-			goto error;
+			return ret;
 	}
 
 	spin_lock_init(&channel->lock);
 	for (i = 0; i < NUM_OF_PHYS; i++) {
 		channel->rphys[i].phy = devm_phy_create(dev, NULL,
 							channel->phy_data->phy_usb2_ops);
-		if (IS_ERR(channel->rphys[i].phy)) {
-			dev_err(dev, "Failed to create USB2 PHY\n");
-			ret = PTR_ERR(channel->rphys[i].phy);
-			goto error;
-		}
+		if (IS_ERR(channel->rphys[i].phy))
+			return dev_err_probe(dev, PTR_ERR(channel->rphys[i].phy),
+					     "Failed to create USB2 PHY\n");
+
 		channel->rphys[i].ch = channel;
 		channel->rphys[i].int_enable_bits = rcar_gen3_int_enable[i];
 		phy_set_drvdata(channel->rphys[i].phy, &channel->rphys[i]);
@@ -886,44 +885,36 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
 	else
 		channel->vbus = devm_regulator_get_optional(dev, "vbus");
 	if (IS_ERR(channel->vbus)) {
-		if (PTR_ERR(channel->vbus) == -EPROBE_DEFER) {
-			ret = PTR_ERR(channel->vbus);
-			goto error;
-		}
+		if (PTR_ERR(channel->vbus) == -EPROBE_DEFER)
+			return PTR_ERR(channel->vbus);
+
 		channel->vbus = NULL;
 	}
 
 	irq = platform_get_irq_optional(pdev, 0);
 	if (irq < 0 && irq != -ENXIO) {
-		ret = irq;
-		goto error;
+		return irq;
 	} else if (irq > 0) {
 		INIT_WORK(&channel->work, rcar_gen3_phy_usb2_work);
 		ret = devm_request_irq(dev, irq, rcar_gen3_phy_usb2_irq,
 				       IRQF_SHARED, dev_name(dev), channel);
-		if (ret < 0) {
-			dev_err(dev, "Failed to request irq (%d)\n", irq);
-			goto error;
-		}
+		if (ret < 0)
+			return dev_err_probe(dev, ret,
+					     "Failed to request irq (%d)\n",
+					     irq);
 	}
 
 	provider = devm_of_phy_provider_register(dev, rcar_gen3_phy_usb2_xlate);
 	if (IS_ERR(provider)) {
-		dev_err(dev, "Failed to register PHY provider\n");
-		ret = PTR_ERR(provider);
-		goto error;
+		return dev_err_probe(dev, PTR_ERR(provider),
+				     "Failed to register PHY provider\n");
 	} else if (channel->is_otg_channel) {
 		ret = device_create_file(dev, &dev_attr_role);
 		if (ret < 0)
-			goto error;
+			return ret;
 	}
 
 	return 0;
-
-error:
-	pm_runtime_disable(dev);
-
-	return ret;
 }
 
 static void rcar_gen3_phy_usb2_remove(struct platform_device *pdev)
@@ -932,8 +923,6 @@ static void rcar_gen3_phy_usb2_remove(struct platform_device *pdev)
 
 	if (channel->is_otg_channel)
 		device_remove_file(&pdev->dev, &dev_attr_role);
-
-	pm_runtime_disable(&pdev->dev);
 }
 
 static struct platform_driver rcar_gen3_phy_usb2_driver = {
-- 
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[PATCH 02/18] phy: renesas: rcar-gen3-usb2: Factor out VBUS control logic

[Tommaso Merciai]

Refactor the VBUS control logic into a new helper function to improve
code clarity and reduce duplication. This makes it easier to handle
different VBUS control register cases and aids future maintenance.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 drivers/phy/renesas/phy-rcar-gen3-usb2.c | 34 +++++++++++++++---------
 1 file changed, 22 insertions(+), 12 deletions(-)

diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
index 38b49ceb5ff3..f6026b3b95e3 100644
--- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
+++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
@@ -203,28 +203,38 @@ static void rcar_gen3_set_linectrl(struct rcar_gen3_chan *ch, int dp, int dm)
 	writel(val, usb2_base + USB2_LINECTRL1);
 }
 
-static void rcar_gen3_enable_vbus_ctrl(struct rcar_gen3_chan *ch, int vbus)
+static void rcar_gen3_phy_usb2_set_vbus(struct rcar_gen3_chan *ch,
+					u32 vbus_ctrl_reg,
+					u32 vbus_ctrl_val,
+					bool enable)
 {
 	void __iomem *usb2_base = ch->base;
-	u32 vbus_ctrl_reg = USB2_ADPCTRL;
-	u32 vbus_ctrl_val = USB2_ADPCTRL_DRVVBUS;
 	u32 val;
 
+	val = readl(usb2_base + vbus_ctrl_reg);
+	if (enable)
+		val |= vbus_ctrl_val;
+	else
+		val &= ~vbus_ctrl_val;
+	writel(val, usb2_base + vbus_ctrl_reg);
+
+	dev_vdbg(ch->dev, "%s: reg=0x%08x, val=%08x, enable=%d\n",
+		 __func__, vbus_ctrl_reg, val, enable);
+}
+
+static void rcar_gen3_enable_vbus_ctrl(struct rcar_gen3_chan *ch, int vbus)
+{
 	if (ch->phy_data->no_adp_ctrl || ch->phy_data->vblvl_ctrl) {
 		if (ch->vbus)
 			regulator_hardware_enable(ch->vbus, vbus);
 
-		vbus_ctrl_reg = USB2_VBCTRL;
-		vbus_ctrl_val = USB2_VBCTRL_VBOUT;
+		rcar_gen3_phy_usb2_set_vbus(ch, USB2_VBCTRL,
+					    USB2_VBCTRL_VBOUT, vbus);
+		return;
 	}
 
-	val = readl(usb2_base + vbus_ctrl_reg);
-	if (vbus)
-		val |= vbus_ctrl_val;
-	else
-		val &= ~vbus_ctrl_val;
-	dev_vdbg(ch->dev, "%s: %08x, %d\n", __func__, val, vbus);
-	writel(val, usb2_base + vbus_ctrl_reg);
+	rcar_gen3_phy_usb2_set_vbus(ch, USB2_ADPCTRL,
+				    USB2_ADPCTRL_DRVVBUS, vbus);
 }
 
 static void rcar_gen3_control_otg_irq(struct rcar_gen3_chan *ch, int enable)
-- 
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[PATCH 03/18] reset: rzv2h-usb2phy: Simplify pm_runtime driver handling

[Tommaso Merciai]

Remove redundant pm_runtime_resume_and_get() and pm_runtime_put() calls
from the reset assert, deassert, and status paths.

These paths do not require runtime PM handling, as power management is
already taken care of during probe and remove.

Additionally, the IP is active only when its clock is enabled.
Previously, the clock was being turned off immediately after register
configuration, which is incorrect. The code may have appeared to work
if another module had incremented the clock usage count, but this
behavior is unreliable.

This change streamlines the code and prevents unnecessary PM and
clock state changes.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 drivers/reset/reset-rzv2h-usb2phy.c | 48 +++++++++--------------------
 1 file changed, 15 insertions(+), 33 deletions(-)

diff --git a/drivers/reset/reset-rzv2h-usb2phy.c b/drivers/reset/reset-rzv2h-usb2phy.c
index ae643575b067..7cd559bc52aa 100644
--- a/drivers/reset/reset-rzv2h-usb2phy.c
+++ b/drivers/reset/reset-rzv2h-usb2phy.c
@@ -66,19 +66,9 @@ static int rzv2h_usbphy_reset_assert(struct reset_controller_dev *rcdev,
 				     unsigned long id)
 {
 	struct rzv2h_usb2phy_reset_priv *priv = rzv2h_usbphy_rcdev_to_priv(rcdev);
-	struct device *dev = priv->dev;
-	int ret;
-
-	ret = pm_runtime_resume_and_get(dev);
-	if (ret) {
-		dev_err(dev, "pm_runtime_resume_and_get failed\n");
-		return ret;
-	}
 
 	rzv2h_usbphy_assert_helper(priv);
 
-	pm_runtime_put(dev);
-
 	return 0;
 }
 
@@ -87,14 +77,6 @@ static int rzv2h_usbphy_reset_deassert(struct reset_controller_dev *rcdev,
 {
 	struct rzv2h_usb2phy_reset_priv *priv = rzv2h_usbphy_rcdev_to_priv(rcdev);
 	const struct rzv2h_usb2phy_reset_of_data *data = priv->data;
-	struct device *dev = priv->dev;
-	int ret;
-
-	ret = pm_runtime_resume_and_get(dev);
-	if (ret) {
-		dev_err(dev, "pm_runtime_resume_and_get failed\n");
-		return ret;
-	}
 
 	scoped_guard(spinlock, &priv->lock) {
 		writel(data->reset_deassert_val, priv->base + data->reset_reg);
@@ -102,8 +84,6 @@ static int rzv2h_usbphy_reset_deassert(struct reset_controller_dev *rcdev,
 		writel(data->reset_release_val, priv->base + data->reset_reg);
 	}
 
-	pm_runtime_put(dev);
-
 	return 0;
 }
 
@@ -111,20 +91,10 @@ static int rzv2h_usbphy_reset_status(struct reset_controller_dev *rcdev,
 				     unsigned long id)
 {
 	struct rzv2h_usb2phy_reset_priv *priv = rzv2h_usbphy_rcdev_to_priv(rcdev);
-	struct device *dev = priv->dev;
-	int ret;
 	u32 reg;
 
-	ret = pm_runtime_resume_and_get(dev);
-	if (ret) {
-		dev_err(dev, "pm_runtime_resume_and_get failed\n");
-		return ret;
-	}
-
 	reg = readl(priv->base + priv->data->reset_reg);
 
-	pm_runtime_put(dev);
-
 	return (reg & priv->data->reset_status_bits) == priv->data->reset_status_bits;
 }
 
@@ -141,6 +111,11 @@ static int rzv2h_usb2phy_reset_of_xlate(struct reset_controller_dev *rcdev,
 	return 0;
 }
 
+static void rzv2h_usb2phy_reset_pm_runtime_put(void *data)
+{
+	pm_runtime_put(data);
+}
+
 static int rzv2h_usb2phy_reset_probe(struct platform_device *pdev)
 {
 	const struct rzv2h_usb2phy_reset_of_data *data;
@@ -175,14 +150,17 @@ static int rzv2h_usb2phy_reset_probe(struct platform_device *pdev)
 	if (error)
 		return dev_err_probe(dev, error, "pm_runtime_resume_and_get failed\n");
 
+	error = devm_add_action_or_reset(dev, rzv2h_usb2phy_reset_pm_runtime_put,
+					 dev);
+	if (error)
+		return dev_err_probe(dev, error, "unable to register cleanup action\n");
+
 	for (unsigned int i = 0; i < data->init_val_count; i++)
 		writel(data->init_vals[i].val, priv->base + data->init_vals[i].reg);
 
 	/* keep usb2phy in asserted state */
 	rzv2h_usbphy_assert_helper(priv);
 
-	pm_runtime_put(dev);
-
 	priv->rcdev.ops = &rzv2h_usbphy_reset_ops;
 	priv->rcdev.of_reset_n_cells = 0;
 	priv->rcdev.nr_resets = 1;
@@ -190,7 +168,11 @@ static int rzv2h_usb2phy_reset_probe(struct platform_device *pdev)
 	priv->rcdev.of_node = dev->of_node;
 	priv->rcdev.dev = dev;
 
-	return devm_reset_controller_register(dev, &priv->rcdev);
+	error = devm_reset_controller_register(dev, &priv->rcdev);
+	if (error)
+		return dev_err_probe(dev, error, "could not register reset controller\n");
+
+	return 0;
 }
 
 /*
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Re: [PATCH 03/18] reset: rzv2h-usb2phy: Simplify pm_runtime driver handling

[Philipp Zabel]

Hi Tommaso,

On Mi, 2025-10-01 at 23:26 +0200, Tommaso Merciai wrote:
> Remove redundant pm_runtime_resume_and_get() and pm_runtime_put() calls
> from the reset assert, deassert, and status paths.

These calls are only made redundant by this patch.

> These paths do not require runtime PM handling, as power management is
> already taken care of during probe and remove.

Only since you removed the pm_runtime_put() in
rzv2h_usb2phy_reset_probe(). It feels like the important part of this
patch is actually the side note:

> Additionally, the IP is active only when its clock is enabled.
> Previously, the clock was being turned off immediately after register
> configuration, which is incorrect. The code may have appeared to work
> if another module had incremented the clock usage count, but this
> behavior is unreliable.

So this is a reliability fix first and foremost?
The IP must be active to reliably keep reset lines at the configured
level?

If so, please make this clear in the commit subject and description.

regards
Philipp

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Re: [PATCH 03/18] reset: rzv2h-usb2phy: Simplify pm_runtime driver handling

[Tommaso Merciai]

Hi Philipp,
Thanks for your review.

On Mon, Oct 06, 2025 at 06:21:25PM +0200, Philipp Zabel wrote:
> Hi Tommaso,
> 
> On Mi, 2025-10-01 at 23:26 +0200, Tommaso Merciai wrote:
> > Remove redundant pm_runtime_resume_and_get() and pm_runtime_put() calls
> > from the reset assert, deassert, and status paths.
> 
> These calls are only made redundant by this patch.
> 
> > These paths do not require runtime PM handling, as power management is
> > already taken care of during probe and remove.
> 
> Only since you removed the pm_runtime_put() in
> rzv2h_usb2phy_reset_probe(). It feels like the important part of this
> patch is actually the side note:
> 
> > Additionally, the IP is active only when its clock is enabled.
> > Previously, the clock was being turned off immediately after register
> > configuration, which is incorrect. The code may have appeared to work
> > if another module had incremented the clock usage count, but this
> > behavior is unreliable.
> 
> So this is a reliability fix first and foremost?
> The IP must be active to reliably keep reset lines at the configured
> level?
> 
> If so, please make this clear in the commit subject and description.

The main purpose of this patch is to ensure the USB PHY controller
remain in a proper state by keeping the IP clock enabled and reset
deasserted for the normal operation.

I will make it clear in v2 also adding Fixes tag.

Thanks & Regards,
Tommaso



> 
> regards
> Philipp

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[PATCH 04/18] reset: rzv2h-usb2phy: Set VBENCTL register for OTG mode

[Tommaso Merciai]

Add logic to set the VBENCTL register when the USB controller operates in
OTG mode. This is required to ensure proper USB transceiver behavior when
the device is configured as OTG.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 drivers/reset/reset-rzv2h-usb2phy.c | 57 +++++++++++++++++++++++++++++
 1 file changed, 57 insertions(+)

diff --git a/drivers/reset/reset-rzv2h-usb2phy.c b/drivers/reset/reset-rzv2h-usb2phy.c
index 7cd559bc52aa..059915cbace5 100644
--- a/drivers/reset/reset-rzv2h-usb2phy.c
+++ b/drivers/reset/reset-rzv2h-usb2phy.c
@@ -10,10 +10,14 @@
 #include <linux/io.h>
 #include <linux/module.h>
 #include <linux/of.h>
+#include <linux/of_platform.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
 #include <linux/reset.h>
 #include <linux/reset-controller.h>
+#include <linux/usb/of.h>
+
+#define VBENCTL		0xf0c
 
 struct rzv2h_usb2phy_regval {
 	u16 reg;
@@ -111,6 +115,57 @@ static int rzv2h_usb2phy_reset_of_xlate(struct reset_controller_dev *rcdev,
 	return 0;
 }
 
+static enum usb_dr_mode
+rzv2h_usb2phy_reset_of_usb_get_dr_mode_by_reset(struct device_node *np)
+{
+	struct device_node *controller;
+	struct of_phandle_args args;
+	struct platform_device *pd;
+	const char *dr_mode_str;
+	enum usb_dr_mode dr_mode;
+	int index;
+
+	for_each_node_with_property(controller, "dr_mode") {
+		index = 0;
+		while (!of_parse_phandle_with_args(controller, "resets",
+						   "#reset-cells", index++,
+						    &args)) {
+			if (args.np == np) {
+				of_node_put(args.np);
+
+				if (!of_property_read_string(controller,
+							     "dr_mode",
+							     &dr_mode_str)) {
+					pd = of_find_device_by_node(controller);
+					dr_mode = usb_get_dr_mode(&pd->dev);
+					of_node_put(controller);
+					put_device(&pd->dev);
+					return dr_mode;
+				}
+
+				of_node_put(controller);
+				break;
+			}
+			of_node_put(args.np);
+		}
+		of_node_put(controller);
+	}
+
+	return USB_DR_MODE_UNKNOWN;
+}
+
+static void rzv2h_usb2phy_reset_setup_vbenctl(struct rzv2h_usb2phy_reset_priv *priv)
+{
+	struct device *dev = priv->rcdev.dev;
+	enum usb_dr_mode dr_mode;
+
+	dr_mode = rzv2h_usb2phy_reset_of_usb_get_dr_mode_by_reset(dev->of_node);
+	dev_dbg(priv->rcdev.dev, "dr_mode: %d\n", dr_mode);
+
+	if (dr_mode == USB_DR_MODE_OTG)
+		writel(BIT(0), priv->base + VBENCTL);
+}
+
 static void rzv2h_usb2phy_reset_pm_runtime_put(void *data)
 {
 	pm_runtime_put(data);
@@ -172,6 +227,8 @@ static int rzv2h_usb2phy_reset_probe(struct platform_device *pdev)
 	if (error)
 		return dev_err_probe(dev, error, "could not register reset controller\n");
 
+	rzv2h_usb2phy_reset_setup_vbenctl(priv);
+
 	return 0;
 }
 
-- 
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Re: [PATCH 04/18] reset: rzv2h-usb2phy: Set VBENCTL register for OTG mode

[Philipp Zabel]

On Mi, 2025-10-01 at 23:26 +0200, Tommaso Merciai wrote:
> Add logic to set the VBENCTL register when the USB controller operates in
> OTG mode. This is required to ensure proper USB transceiver behavior when
> the device is configured as OTG.
> 
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>

I had reservations about this driver before, because of the opaque
register initialization sequence, and I was told that no, this is a
reset driver alright [1].

Can you please try to find a proper abstraction for this, because
drivers/reset is not the correct place for USB OTG mode handling.

[1] https://lore.kernel.org/all/TYCPR01MB12093DB963348A8FD58409E5AC2DE2@TYCPR01MB12093.jpnprd01.prod.outlook.com/


regards
Philipp

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RE: [PATCH 04/18] reset: rzv2h-usb2phy: Set VBENCTL register for OTG mode

[Biju Das]

Hi Philipp,

Thanks for the feedback.

> -----Original Message-----
> From: Philipp Zabel <p.zabel@pengutronix.de>
> Sent: 06 October 2025 17:32
> Subject: Re: [PATCH 04/18] reset: rzv2h-usb2phy: Set VBENCTL register for OTG mode
> 
> On Mi, 2025-10-01 at 23:26 +0200, Tommaso Merciai wrote:
> > Add logic to set the VBENCTL register when the USB controller operates
> > in OTG mode. This is required to ensure proper USB transceiver
> > behavior when the device is configured as OTG.
> >
> > Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> 
> I had reservations about this driver before, because of the opaque register initialization sequence, and
> I was told that no, this is a reset driver alright [1].

The latest hardware manual document about VBENCTRL register which sets source for VBUS selection.
s
> 
> Can you please try to find a proper abstraction for this, because drivers/reset is not the correct place
> for USB OTG mode handling.

Sorry for the confusion. This driver is not handling USB OTG mode. It just configures VBENCTRL(one time setting)
that selects the source for VBUS_SEL. Actual USB OTG mode handling is done USB PHY driver
which sets host/device mode based on ID detection.

Cheers,
Biju
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Re: [PATCH 04/18] reset: rzv2h-usb2phy: Set VBENCTL register for OTG mode

[Philipp Zabel]

Hi Biju,

On Di, 2025-10-07 at 04:02 +0000, Biju Das wrote:
> Hi Philipp,
> 
> Thanks for the feedback.
> 
> > -----Original Message-----
> > From: Philipp Zabel <p.zabel@pengutronix.de>
> > Sent: 06 October 2025 17:32
> > Subject: Re: [PATCH 04/18] reset: rzv2h-usb2phy: Set VBENCTL register for OTG mode
> > 
> > On Mi, 2025-10-01 at 23:26 +0200, Tommaso Merciai wrote:
> > > Add logic to set the VBENCTL register when the USB controller operates
> > > in OTG mode. This is required to ensure proper USB transceiver
> > > behavior when the device is configured as OTG.
> > > 
> > > Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> > 
> > I had reservations about this driver before, because of the opaque register initialization sequence, and
> > I was told that no, this is a reset driver alright [1].
> 
> The latest hardware manual document about VBENCTRL register which sets source for VBUS selection.
> s

I still can't look at this, right? The USB2PHY control register space
appears to be documented in the "RZ/V2H Group User's Manual: Hardware
(Additional document)" (under NDA).

> > Can you please try to find a proper abstraction for this, because drivers/reset is not the correct place
> > for USB OTG mode handling.
> 
> Sorry for the confusion. This driver is not handling USB OTG mode. It just configures VBENCTRL(one time setting)
> that selects the source for VBUS_SEL. Actual USB OTG mode handling is done USB PHY driver
> which sets host/device mode based on ID detection.

So this is a mux for the VBUS_SEL signal?

Why don't the USB host controller drivers parse their "dr_mode"
property themselves and control USB2PHY VBENCTRL via the mux API, for
example?

regards
Philipp

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RE: [PATCH 04/18] reset: rzv2h-usb2phy: Set VBENCTL register for OTG mode

[Biju Das]

Hi Philipp,

> -----Original Message-----
> From: Philipp Zabel <p.zabel@pengutronix.de>
> Sent: 07 October 2025 10:44
> Subject: Re: [PATCH 04/18] reset: rzv2h-usb2phy: Set VBENCTL register for OTG mode
> 
> Hi Biju,
> 
> On Di, 2025-10-07 at 04:02 +0000, Biju Das wrote:
> > Hi Philipp,
> >
> > Thanks for the feedback.
> >
> > > -----Original Message-----
> > > From: Philipp Zabel <p.zabel@pengutronix.de>
> > > Sent: 06 October 2025 17:32
> > > Subject: Re: [PATCH 04/18] reset: rzv2h-usb2phy: Set VBENCTL
> > > register for OTG mode
> > >
> > > On Mi, 2025-10-01 at 23:26 +0200, Tommaso Merciai wrote:
> > > > Add logic to set the VBENCTL register when the USB controller
> > > > operates in OTG mode. This is required to ensure proper USB
> > > > transceiver behavior when the device is configured as OTG.
> > > >
> > > > Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> > >
> > > I had reservations about this driver before, because of the opaque
> > > register initialization sequence, and I was told that no, this is a reset driver alright [1].
> >
> > The latest hardware manual document about VBENCTRL register which sets source for VBUS selection.
> > s
> 
> I still can't look at this, right? The USB2PHY control register space appears to be documented in
> the "RZ/V2H Group User's Manual: Hardware (Additional document)" (under NDA).	

It is documented here[1], Page 2177, USB2PHY Control Register (USB2m_PHY_VBENCTL)

[1]
https://www.renesas.com/en/document/mah/rzg3e-group-users-manual-hardware?r=25574493


> 
> > > Can you please try to find a proper abstraction for this, because
> > > drivers/reset is not the correct place for USB OTG mode handling.
> >
> > Sorry for the confusion. This driver is not handling USB OTG mode. It
> > just configures VBENCTRL(one time setting) that selects the source for
> > VBUS_SEL. Actual USB OTG mode handling is done USB PHY driver which sets host/device mode based on
> ID detection.
> 
> So this is a mux for the VBUS_SEL signal?

Yes, Please find the bit definition.

0 VBUS_SEL 0h RW Select VBUSEN control
0b: Output PP controlled by PORTSC1 register of the Host Controller as VBUSEN.
1b: Output VBOUT controlled by VBCTRL register of the Host Controller as VBUSEN.

We have USB PHY control driver(This driver)-> USB PHY driver->| USB HOST(Generic ehci/ohci)
                                                       	  | USB function (renesas usbhs)

We plan to set 1b for this IP in this driver for OTG channel during probe.
After that using VBOUT register the PHY driver can switch between Host and device.

> 
> Why don't the USB host controller drivers parse their "dr_mode"
> property themselves and control USB2PHY VBENCTRL via the mux API, for example?

Currently for OTG channel, based ID detection IRQ, the USB PHY driver switches between host
and device. We use method2 below for the host operation.

For Host operation:
Method1: USB2m_PHY_VBENCTL.VBUS_SEL=0
or
method2: USB2m_PHY_VBENCTL.VBUS_SEL=1 and USB_HOST_VBCTRL.VBOUT = 1

For device operation:
USB2m_PHY_VBENCTL.VBUS_SEL=1 and USB_HOST_VBCTRL.VBOUT = 0

Are you suggesting to use method1(mux) for host operation?

Currently this is one time configuration. If we plan to
use mux, then it becomes dynamic.

How we can we make use of PHY driver using mux API to select the mux register(VBUS_SEL)
in USB PHY control Driver?

Cheers,
Biju





 








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Re: [PATCH 04/18] reset: rzv2h-usb2phy: Set VBENCTL register for OTG mode

[Philipp Zabel]

Hi Biju,

On Di, 2025-10-07 at 11:04 +0000, Biju Das wrote:
> Hi Philipp,
> 
> > -----Original Message-----
> > From: Philipp Zabel <p.zabel@pengutronix.de>
> > Sent: 07 October 2025 10:44
> > Subject: Re: [PATCH 04/18] reset: rzv2h-usb2phy: Set VBENCTL register for OTG mode
> > 
> > Hi Biju,
> > 
> > On Di, 2025-10-07 at 04:02 +0000, Biju Das wrote:
> > > Hi Philipp,
> > > 
> > > Thanks for the feedback.
> > > 
> > > > -----Original Message-----
> > > > From: Philipp Zabel <p.zabel@pengutronix.de>
> > > > Sent: 06 October 2025 17:32
> > > > Subject: Re: [PATCH 04/18] reset: rzv2h-usb2phy: Set VBENCTL
> > > > register for OTG mode
> > > > 
> > > > On Mi, 2025-10-01 at 23:26 +0200, Tommaso Merciai wrote:
> > > > > Add logic to set the VBENCTL register when the USB controller
> > > > > operates in OTG mode. This is required to ensure proper USB
> > > > > transceiver behavior when the device is configured as OTG.
> > > > > 
> > > > > Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> > > > 
> > > > I had reservations about this driver before, because of the opaque
> > > > register initialization sequence, and I was told that no, this is a reset driver alright [1].
> > > 
> > > The latest hardware manual document about VBENCTRL register which sets source for VBUS selection.
> > > s
> > 
> > I still can't look at this, right? The USB2PHY control register space appears to be documented in
> > the "RZ/V2H Group User's Manual: Hardware (Additional document)" (under NDA).	
> 
> It is documented here[1], Page 2177, USB2PHY Control Register (USB2m_PHY_VBENCTL)
> 
> [1]
> https://www.renesas.com/en/document/mah/rzg3e-group-users-manual-hardware?r=25574493

For me, that link points to a document without the USB2m_PHY_* register
definitions. Page 2177 is unrelated (documenting PCI_EP_HLOG2_Fn,
somewhere in the PCIe interface chapter).

> > > > Can you please try to find a proper abstraction for this, because
> > > > drivers/reset is not the correct place for USB OTG mode handling.
> > > 
> > > Sorry for the confusion. This driver is not handling USB OTG mode. It
> > > just configures VBENCTRL(one time setting) that selects the source for
> > > VBUS_SEL. Actual USB OTG mode handling is done USB PHY driver which sets host/device mode based on
> > ID detection.
> > 
> > So this is a mux for the VBUS_SEL signal?
> 
> Yes, Please find the bit definition.
> 
> 0 VBUS_SEL 0h RW Select VBUSEN control
> 0b: Output PP controlled by PORTSC1 register of the Host Controller as VBUSEN.
> 1b: Output VBOUT controlled by VBCTRL register of the Host Controller as VBUSEN.
> 
> We have USB PHY control driver(This driver)-> USB PHY driver->| USB HOST(Generic ehci/ohci)
>                                                        	  | USB function (renesas usbhs)
> 
> We plan to set 1b for this IP in this driver for OTG channel during probe.
> After that using VBOUT register the PHY driver can switch between Host and device.

Thank you for the explanation.

> > Why don't the USB host controller drivers parse their "dr_mode"
> > property themselves and control USB2PHY VBENCTRL via the mux API, for example?
> 
> Currently for OTG channel, based ID detection IRQ, the USB PHY driver switches between host
> and device. We use method2 below for the host operation.
> 
> For Host operation:
> Method1: USB2m_PHY_VBENCTL.VBUS_SEL=0
> or
> method2: USB2m_PHY_VBENCTL.VBUS_SEL=1 and USB_HOST_VBCTRL.VBOUT = 1
> 
> For device operation:
> USB2m_PHY_VBENCTL.VBUS_SEL=1 and USB_HOST_VBCTRL.VBOUT = 0
> 
> Are you suggesting to use method1(mux) for host operation?

No, not necessarily. I was thinking of letting the PHY driver, before
registering the VBOUT controlled VBUS regulator in its probe function,
call into the mux API to set VBENCTL.VBUS_SEL=1 and thus make the VBOUT
bit functional.

> Currently this is one time configuration. If we plan to
> use mux, then it becomes dynamic.
>
> How we can we make use of PHY driver using mux API to select the mux register(VBUS_SEL)
> in USB PHY control Driver?

For example, this driver could spawn an auxiliary mux device with a
driver in drivers/mux that registers a mux for VBENCTL.VBUS_SEL on the
&usb20phyrst node.

The phy could then get a "mux-states = <&usb20phyrst 1>;" property in
its device tree node and call the equivalent of:

  mux_state = devm_mux_state_get_optional(dev, NULL);
  mux_state_select(mux_state);

to switch to VBOUT controlled VBUSEN.

regards
Philipp

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RE: [PATCH 04/18] reset: rzv2h-usb2phy: Set VBENCTL register for OTG mode

[Biju Das]

Hi Philipp,

> -----Original Message-----
> From: Philipp Zabel <p.zabel@pengutronix.de>
> Sent: 07 October 2025 15:13
> Subject: Re: [PATCH 04/18] reset: rzv2h-usb2phy: Set VBENCTL register for OTG mode
> 
> Hi Biju,
> 
> On Di, 2025-10-07 at 11:04 +0000, Biju Das wrote:
> > Hi Philipp,
> >
> > > -----Original Message-----
> > > From: Philipp Zabel <p.zabel@pengutronix.de>
> > > Sent: 07 October 2025 10:44
> > > Subject: Re: [PATCH 04/18] reset: rzv2h-usb2phy: Set VBENCTL
> > > register for OTG mode
> > >
> > > Hi Biju,
> > >
> > > On Di, 2025-10-07 at 04:02 +0000, Biju Das wrote:
> > > > Hi Philipp,
> > > >
> > > > Thanks for the feedback.
> > > >
> > > > > -----Original Message-----
> > > > > From: Philipp Zabel <p.zabel@pengutronix.de>
> > > > > Sent: 06 October 2025 17:32
> > > > > Subject: Re: [PATCH 04/18] reset: rzv2h-usb2phy: Set VBENCTL
> > > > > register for OTG mode
> > > > >
> > > > > On Mi, 2025-10-01 at 23:26 +0200, Tommaso Merciai wrote:
> > > > > > Add logic to set the VBENCTL register when the USB controller
> > > > > > operates in OTG mode. This is required to ensure proper USB
> > > > > > transceiver behavior when the device is configured as OTG.
> > > > > >
> > > > > > Signed-off-by: Tommaso Merciai
> > > > > > <tommaso.merciai.xr@bp.renesas.com>
> > > > >
> > > > > I had reservations about this driver before, because of the
> > > > > opaque register initialization sequence, and I was told that no, this is a reset driver
> alright [1].
> > > >
> > > > The latest hardware manual document about VBENCTRL register which sets source for VBUS
> selection.
> > > > s
> > >
> > > I still can't look at this, right? The USB2PHY control register space appears to be documented in
> > > the "RZ/V2H Group User's Manual: Hardware (Additional document)" (under NDA).
> >
> > It is documented here[1], Page 2177, USB2PHY Control Register
> > (USB2m_PHY_VBENCTL)
> >
> > [1]
> > https://www.renesas.com/en/document/mah/rzg3e-group-users-manual-hardw
> > are?r=25574493
> 
> For me, that link points to a document without the USB2m_PHY_* register definitions. Page 2177 is
> unrelated (documenting PCI_EP_HLOG2_Fn, somewhere in the PCIe interface chapter).

My Bad. I rechecked the link and confirm what you said is correct.
I am using NDA document.

> 
> > > > > Can you please try to find a proper abstraction for this,
> > > > > because drivers/reset is not the correct place for USB OTG mode handling.
> > > >
> > > > Sorry for the confusion. This driver is not handling USB OTG mode.
> > > > It just configures VBENCTRL(one time setting) that selects the
> > > > source for VBUS_SEL. Actual USB OTG mode handling is done USB PHY
> > > > driver which sets host/device mode based on
> > > ID detection.
> > >
> > > So this is a mux for the VBUS_SEL signal?
> >
> > Yes, Please find the bit definition.
> >
> > 0 VBUS_SEL 0h RW Select VBUSEN control
> > 0b: Output PP controlled by PORTSC1 register of the Host Controller as VBUSEN.
> > 1b: Output VBOUT controlled by VBCTRL register of the Host Controller as VBUSEN.
> >
> > We have USB PHY control driver(This driver)-> USB PHY driver->| USB HOST(Generic ehci/ohci)
> >                                                        	  | USB
> > function (renesas usbhs)
> >
> > We plan to set 1b for this IP in this driver for OTG channel during probe.
> > After that using VBOUT register the PHY driver can switch between Host and device.
> 
> Thank you for the explanation.
> 
> > > Why don't the USB host controller drivers parse their "dr_mode"
> > > property themselves and control USB2PHY VBENCTRL via the mux API, for example?
> >
> > Currently for OTG channel, based ID detection IRQ, the USB PHY driver
> > switches between host and device. We use method2 below for the host operation.
> >
> > For Host operation:
> > Method1: USB2m_PHY_VBENCTL.VBUS_SEL=0
> > or
> > method2: USB2m_PHY_VBENCTL.VBUS_SEL=1 and USB_HOST_VBCTRL.VBOUT = 1
> >
> > For device operation:
> > USB2m_PHY_VBENCTL.VBUS_SEL=1 and USB_HOST_VBCTRL.VBOUT = 0
> >
> > Are you suggesting to use method1(mux) for host operation?
> 
> No, not necessarily. I was thinking of letting the PHY driver, before registering the VBOUT
> controlled VBUS regulator in its probe function, call into the mux API to set VBENCTL.VBUS_SEL=1 and
> thus make the VBOUT bit functional.

OK.

> 
> > Currently this is one time configuration. If we plan to use mux, then
> > it becomes dynamic.
> >
> > How we can we make use of PHY driver using mux API to select the mux
> > register(VBUS_SEL) in USB PHY control Driver?
> 
> For example, this driver could spawn an auxiliary mux device with a driver in drivers/mux that
> registers a mux for VBENCTL.VBUS_SEL on the &usb20phyrst node.
> 
> The phy could then get a "mux-states = <&usb20phyrst 1>;" property in its device tree node and call
> the equivalent of:
> 
>   mux_state = devm_mux_state_get_optional(dev, NULL);
>   mux_state_select(mux_state);
> 
> to switch to VBOUT controlled VBUSEN.

Will check this and update you.

Cheers,
Biju
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[PATCH 05/18] dt-bindings: phy: renesas,usb2-phy: Document USB VBUS regulator

[Tommaso Merciai]

Document the 'vbus-regulator' child node in the Renesas USB2 PHY binding
to describe the internal USB VBUS regulator.

Require this regulator node on OTG channels to accurately represent
hardware dependencies in the device tree.

Documenting this regulator allows device trees to model the VBUS power
requirements of these SoCs properly.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
index 179cb4bfc424..dde5269b0db2 100644
--- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
@@ -89,6 +89,12 @@ properties:
       Phandle to a regulator that provides power to the VBUS. This regulator
       will be managed during the PHY power on/off sequence.
 
+  vbus-regulator:
+    $ref: /schemas/regulator/regulator.yaml#
+    description: USB VBUS internal regulator
+    type: object
+    unevaluatedProperties: false
+
   renesas,no-otg-pins:
     $ref: /schemas/types.yaml#/definitions/flag
     description: |
-- 
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[PATCH 06/18] phy: renesas: rcar-gen3-usb2: Add regulator for OTG VBUS control

[Tommaso Merciai]

Enable OTG VBUS control on R-Car Gen3 USB2 PHY by registering a regulator
driver that manages the VBOUT line. This change allows the controller to
handle VBUS output for OTG ports using the regulator framework when the
platform requires hardware-based VBUS control.

Without this, some platforms cannot properly manage VBUS power on OTG-
capable ports, leading to potential USB functionality issues.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 drivers/phy/renesas/phy-rcar-gen3-usb2.c | 112 ++++++++++++++++++++++-
 1 file changed, 108 insertions(+), 4 deletions(-)

diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
index f6026b3b95e3..81de01410c19 100644
--- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
+++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
@@ -22,6 +22,7 @@
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
 #include <linux/regulator/consumer.h>
+#include <linux/regulator/driver.h>
 #include <linux/reset.h>
 #include <linux/string.h>
 #include <linux/usb/of.h>
@@ -140,6 +141,7 @@ struct rcar_gen3_chan {
 	bool extcon_host;
 	bool is_otg_channel;
 	bool uses_otg_pins;
+	bool otg_internal_reg;
 };
 
 struct rcar_gen3_phy_drv_data {
@@ -224,6 +226,11 @@ static void rcar_gen3_phy_usb2_set_vbus(struct rcar_gen3_chan *ch,
 
 static void rcar_gen3_enable_vbus_ctrl(struct rcar_gen3_chan *ch, int vbus)
 {
+	if (ch->otg_internal_reg) {
+		regulator_hardware_enable(ch->vbus, vbus);
+		return;
+	}
+
 	if (ch->phy_data->no_adp_ctrl || ch->phy_data->vblvl_ctrl) {
 		if (ch->vbus)
 			regulator_hardware_enable(ch->vbus, vbus);
@@ -592,7 +599,7 @@ static int rcar_gen3_phy_usb2_power_on(struct phy *p)
 	u32 val;
 	int ret = 0;
 
-	if (channel->vbus) {
+	if (channel->vbus && !channel->otg_internal_reg) {
 		ret = regulator_enable(channel->vbus);
 		if (ret)
 			return ret;
@@ -633,7 +640,7 @@ static int rcar_gen3_phy_usb2_power_off(struct phy *p)
 		}
 	}
 
-	if (channel->vbus)
+	if (channel->vbus && !channel->otg_internal_reg)
 		ret = regulator_disable(channel->vbus);
 
 	return ret;
@@ -819,6 +826,98 @@ static int rcar_gen3_phy_usb2_init_bus(struct rcar_gen3_chan *channel)
 	return ret;
 }
 
+static int rcar_gen3_phy_usb2_regulator_endisable(struct regulator_dev *rdev,
+						  bool enable)
+{
+	struct rcar_gen3_chan *channel = rdev_get_drvdata(rdev);
+	struct device *dev = channel->dev;
+	int ret;
+
+	ret = pm_runtime_resume_and_get(dev);
+	if (ret < 0) {
+		dev_warn(dev, "pm_runtime_get failed: %i\n", ret);
+		return ret;
+	}
+
+	rcar_gen3_phy_usb2_set_vbus(channel, USB2_VBCTRL,
+				    USB2_VBCTRL_VBOUT, enable);
+	pm_runtime_put_noidle(dev);
+
+	return ret;
+}
+
+static int rcar_gen3_phy_usb2_regulator_enable(struct regulator_dev *rdev)
+{
+	return rcar_gen3_phy_usb2_regulator_endisable(rdev, true);
+}
+
+static int rcar_gen3_phy_usb2_regulator_disable(struct regulator_dev *rdev)
+{
+	return rcar_gen3_phy_usb2_regulator_endisable(rdev, false);
+}
+
+static int rcar_gen3_phy_usb2_regulator_is_enabled(struct regulator_dev *rdev)
+{
+	struct rcar_gen3_chan *channel = rdev_get_drvdata(rdev);
+	void __iomem *usb2_base = channel->base;
+	struct device *dev = channel->dev;
+	u32 vbus_ctrl_reg = USB2_VBCTRL;
+	u32 val;
+	int ret;
+
+	ret = pm_runtime_resume_and_get(dev);
+	if (ret < 0) {
+		dev_warn(dev, "pm_runtime_get failed: %i\n", ret);
+		return ret;
+	}
+
+	val = readl(usb2_base + vbus_ctrl_reg);
+
+	pm_runtime_put_noidle(dev);
+	dev_dbg(channel->dev, "%s: %08x\n", __func__, val);
+
+	return (val & USB2_VBCTRL_VBOUT) ? 1 : 0;
+}
+
+static const struct regulator_ops rcar_gen3_phy_usb2_regulator_ops = {
+	.enable = rcar_gen3_phy_usb2_regulator_enable,
+	.disable = rcar_gen3_phy_usb2_regulator_disable,
+	.is_enabled = rcar_gen3_phy_usb2_regulator_is_enabled,
+};
+
+static const struct regulator_desc rcar_gen3_phy_usb2_regulator = {
+	.name = "otg-vbus-regulator",
+	.of_match = of_match_ptr("vbus-regulator"),
+	.ops = &rcar_gen3_phy_usb2_regulator_ops,
+	.type = REGULATOR_VOLTAGE,
+	.owner = THIS_MODULE,
+	.fixed_uV = 5000000,
+	.n_voltages = 1,
+};
+
+static int rcar_gen3_phy_usb2_vbus_regulator_register(struct rcar_gen3_chan *channel)
+{
+	struct device *dev = channel->dev;
+	struct regulator_config rcfg = { .dev = dev, };
+	struct regulator_dev *rdev;
+
+	rcfg.of_node = of_get_available_child_by_name(dev->of_node,
+						      "vbus-regulator");
+	if (rcfg.of_node) {
+		rcfg.driver_data = channel;
+		rdev = devm_regulator_register(dev, &rcar_gen3_phy_usb2_regulator,
+					       &rcfg);
+		of_node_put(rcfg.of_node);
+		if (IS_ERR(rdev))
+			return dev_err_probe(dev, PTR_ERR(rdev),
+					"Failed to create vbus-regulator\n");
+
+		channel->otg_internal_reg = true;
+	}
+
+	return 0;
+}
+
 static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
@@ -890,10 +989,15 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
 		phy_set_drvdata(channel->rphys[i].phy, &channel->rphys[i]);
 	}
 
-	if (channel->phy_data->no_adp_ctrl && channel->is_otg_channel)
+	if (channel->phy_data->no_adp_ctrl && channel->is_otg_channel) {
+		ret = rcar_gen3_phy_usb2_vbus_regulator_register(channel);
+		if (ret)
+			return ret;
+
 		channel->vbus = devm_regulator_get_exclusive(dev, "vbus");
-	else
+	} else {
 		channel->vbus = devm_regulator_get_optional(dev, "vbus");
+	}
 	if (IS_ERR(channel->vbus)) {
 		if (PTR_ERR(channel->vbus) == -EPROBE_DEFER)
 			return PTR_ERR(channel->vbus);
-- 
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[PATCH 07/18] regulator: devres: Disable exclusive regulator before releasing

[Tommaso Merciai]

Ensure that exclusive regulators are properly disabled when their reference
count drops to one before they are released. This prevents possible issues
where exclusive regulators may remain enabled unintentionally after being
put.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 drivers/regulator/devres.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/regulator/devres.c b/drivers/regulator/devres.c
index 2cf03042fddf..48da9823ce2f 100644
--- a/drivers/regulator/devres.c
+++ b/drivers/regulator/devres.c
@@ -16,7 +16,13 @@
 
 static void devm_regulator_release(struct device *dev, void *res)
 {
-	regulator_put(*(struct regulator **)res);
+	struct regulator *regulator = *(struct regulator **)res;
+	struct regulator_dev *rdev = regulator->rdev;
+
+	if (rdev->exclusive && regulator->enable_count == 1)
+		regulator_disable(regulator);
+
+	regulator_put(regulator);
 }
 
 static struct regulator *_devm_regulator_get(struct device *dev, const char *id,
-- 
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Re: [PATCH 07/18] regulator: devres: Disable exclusive regulator before releasing

[Mark Brown]

[-- Attachment #1.1: Type: text/plain, Size: 1631 bytes --]

On Wed, Oct 01, 2025 at 11:26:51PM +0200, Tommaso Merciai wrote:

You've not copied me on the rest of the series so I don't know what's
going on with dependencies.  When sending a patch series it is important
to ensure that all the various maintainers understand what the
relationship between the patches as the expecation is that there will be
interdependencies.  Either copy everyone on the whole series or at least
copy them on the cover letter and explain what's going on.  If there are
no strong interdependencies then it's generally simplest to just send
the patches separately to avoid any possible confusion.

> Ensure that exclusive regulators are properly disabled when their reference
> count drops to one before they are released. This prevents possible issues
> where exclusive regulators may remain enabled unintentionally after being
> put.

The reason we don't normally drop references that devices hold is that
we're allowing the driver to control if the suppy should be disabled on
exit, powering off something that's critical for the system just because
we're not managing it in software won't go well.  Consider reloading a
module during development for example.

>  static void devm_regulator_release(struct device *dev, void *res)
>  {
> -	regulator_put(*(struct regulator **)res);
> +	struct regulator *regulator = *(struct regulator **)res;
> +	struct regulator_dev *rdev = regulator->rdev;
> +
> +	if (rdev->exclusive && regulator->enable_count == 1)
> +		regulator_disable(regulator);
> +
> +	regulator_put(regulator);
>  }

There's no reason that exclusive consumers don't use the refcounting
support...

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Re: [PATCH 07/18] regulator: devres: Disable exclusive regulator before releasing

[Tommaso Merciai]

Hi Mark,
Thank you for your comments,

On Thu, Oct 02, 2025 at 05:29:19PM +0100, Mark Brown wrote:
> On Wed, Oct 01, 2025 at 11:26:51PM +0200, Tommaso Merciai wrote:
> 
> You've not copied me on the rest of the series so I don't know what's
> going on with dependencies.  When sending a patch series it is important
> to ensure that all the various maintainers understand what the
> relationship between the patches as the expecation is that there will be
> interdependencies.  Either copy everyone on the whole series or at least
> copy them on the cover letter and explain what's going on.  If there are
> no strong interdependencies then it's generally simplest to just send
> the patches separately to avoid any possible confusion.

Thanks for the explanation.
I made a mistake when I sent the series.
I only ran ./scripts/get_maintainer.pl on some patches, not all.
My fault, sorry for that.

> 
> > Ensure that exclusive regulators are properly disabled when their reference
> > count drops to one before they are released. This prevents possible issues
> > where exclusive regulators may remain enabled unintentionally after being
> > put.
> 
> The reason we don't normally drop references that devices hold is that
> we're allowing the driver to control if the suppy should be disabled on
> exit, powering off something that's critical for the system just because
> we're not managing it in software won't go well.  Consider reloading a
> module during development for example.
> 
> >  static void devm_regulator_release(struct device *dev, void *res)
> >  {
> > -	regulator_put(*(struct regulator **)res);
> > +	struct regulator *regulator = *(struct regulator **)res;
> > +	struct regulator_dev *rdev = regulator->rdev;
> > +
> > +	if (rdev->exclusive && regulator->enable_count == 1)
> > +		regulator_disable(regulator);
> > +
> > +	regulator_put(regulator);
> >  }
> 
> There's no reason that exclusive consumers don't use the refcounting
> support...

I will need to move the refcounting handlingfor the exclusive regulator
at USB driver lvl.
The drivers/phy/renesas/phy-rcar-gen3-usb2.c is using
regulator_hardware_enable() for some USB otg channel. I think this is
the reason why I need this patch to handle multiple unbind/bind.
Without this I'm getting some WARN_ON(regulator->enable_count) doing
multiple unbind/bind.

I'm going to investigate on that and I need to find a solution at usb driver lvl.
Thanks again for your feedback!

Regards,
Tommaso



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Re: [PATCH 07/18] regulator: devres: Disable exclusive regulator before releasing

[Mark Brown]

[-- Attachment #1.1: Type: text/plain, Size: 700 bytes --]

On Fri, Oct 03, 2025 at 07:33:25PM +0200, Tommaso Merciai wrote:
> On Thu, Oct 02, 2025 at 05:29:19PM +0100, Mark Brown wrote:

> I will need to move the refcounting handlingfor the exclusive regulator
> at USB driver lvl.
> The drivers/phy/renesas/phy-rcar-gen3-usb2.c is using
> regulator_hardware_enable() for some USB otg channel. I think this is
> the reason why I need this patch to handle multiple unbind/bind.
> Without this I'm getting some WARN_ON(regulator->enable_count) doing
> multiple unbind/bind.

Are you sure it's not just that the driver doesn't always disable the
regulator before unbinding?  It only disables in the power off callback
so might leave a dangling reference behind.

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Re: [PATCH 07/18] regulator: devres: Disable exclusive regulator before releasing

[Tommaso Merciai]

Hi Mark,
Thanks for your comment.

On Mon, Oct 06, 2025 at 12:52:29PM +0100, Mark Brown wrote:
> On Fri, Oct 03, 2025 at 07:33:25PM +0200, Tommaso Merciai wrote:
> > On Thu, Oct 02, 2025 at 05:29:19PM +0100, Mark Brown wrote:
> 
> > I will need to move the refcounting handlingfor the exclusive regulator
> > at USB driver lvl.
> > The drivers/phy/renesas/phy-rcar-gen3-usb2.c is using
> > regulator_hardware_enable() for some USB otg channel. I think this is
> > the reason why I need this patch to handle multiple unbind/bind.
> > Without this I'm getting some WARN_ON(regulator->enable_count) doing
> > multiple unbind/bind.
> 
> Are you sure it's not just that the driver doesn't always disable the
> regulator before unbinding?  It only disables in the power off callback
> so might leave a dangling reference behind.

Yep you are right.
I will fix that in v2 dropping this unnecessary patch.

Thanks & Regards,
Tommaso


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[PATCH 08/18] dt-bindings: clock: renesas,r9a09g047-cpg: Add USB2 PHY core clocks

[Tommaso Merciai]

Add definitions for USB2 PHY core clocks in the R9A09G047 CPG DT
bindings header file.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 include/dt-bindings/clock/renesas,r9a09g047-cpg.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
index f165df8a6f5a..dab24740de3c 100644
--- a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
+++ b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
@@ -22,5 +22,7 @@
 #define R9A09G047_GBETH_1_CLK_PTP_REF_I		11
 #define R9A09G047_USB3_0_REF_ALT_CLK_P		12
 #define R9A09G047_USB3_0_CLKCORE		13
+#define R9A09G047_USB2_0_CLK_CORE0		14
+#define R9A09G047_USB2_0_CLK_CORE1		15
 
 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */
-- 
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Re: [PATCH 08/18] dt-bindings: clock: renesas,r9a09g047-cpg: Add USB2 PHY core clocks

[Geert Uytterhoeven]

On Wed, 1 Oct 2025 at 23:28, Tommaso Merciai
<tommaso.merciai.xr@bp.renesas.com> wrote:
> Add definitions for USB2 PHY core clocks in the R9A09G047 CPG DT
> bindings header file.
>
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in a branch shared by renesas-clk and renesas-dts.

Gr{oetje,eeting}s,

                        Geert

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[PATCH 09/18] clk: renesas: r9a09g047: Add clock and reset entries for USB2

[Tommaso Merciai]

Add clock and reset entries for USB2.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 drivers/clk/renesas/r9a09g047-cpg.c | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index ef115f9ec0e6..68f8b08bd16f 100644
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -16,7 +16,7 @@
 
 enum clk_ids {
 	/* Core Clock Outputs exported to DT */
-	LAST_DT_CORE_CLK = R9A09G047_USB3_0_CLKCORE,
+	LAST_DT_CORE_CLK = R9A09G047_USB2_0_CLK_CORE1,
 
 	/* External Input Clocks */
 	CLK_AUDIO_EXTAL,
@@ -177,6 +177,8 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
 		 CDDIV1_DIVCTL3, dtable_1_8),
 	DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
 	DEF_FIXED("spi_clk_spi", R9A09G047_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2),
+	DEF_FIXED("usb2_0_clk_core0", R9A09G047_USB2_0_CLK_CORE0, CLK_QEXTAL, 1, 1),
+	DEF_FIXED("usb2_0_clk_core1", R9A09G047_USB2_0_CLK_CORE1, CLK_QEXTAL, 1, 1),
 	DEF_FIXED("gbeth_0_clk_ptp_ref_i", R9A09G047_GBETH_0_CLK_PTP_REF_I,
 		  CLK_PLLETH_DIV_125_FIX, 1, 1),
 	DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G047_GBETH_1_CLK_PTP_REF_I,
@@ -282,6 +284,16 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
 						BUS_MSTOP(7, BIT(12))),
 	DEF_MOD("usb3_0_pclk_usbtst",		CLK_PLLDTY_ACPU_DIV4, 11, 0, 5, 16,
 						BUS_MSTOP(7, BIT(14))),
+	DEF_MOD("usb2_0_u2h0_hclk",		CLK_PLLDTY_DIV8, 11, 3, 5, 19,
+						BUS_MSTOP(7, BIT(7))),
+	DEF_MOD("usb2_0_u2h1_hclk",		CLK_PLLDTY_DIV8, 11, 4, 5, 20,
+						BUS_MSTOP(7, BIT(8))),
+	DEF_MOD("usb2_0_u2p_exr_cpuclk",	CLK_PLLDTY_ACPU_DIV4, 11, 5, 5, 21,
+						BUS_MSTOP(7, BIT(9))),
+	DEF_MOD("usb2_0_pclk_usbtst0",		CLK_PLLDTY_ACPU_DIV4, 11, 6, 5, 22,
+						BUS_MSTOP(7, BIT(10))),
+	DEF_MOD("usb2_0_pclk_usbtst1",		CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23,
+						BUS_MSTOP(7, BIT(11))),
 	DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
 						BUS_MSTOP(8, BIT(5)), 1),
 	DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
@@ -359,6 +371,10 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
 	DEF_RST(10, 8, 4, 25),		/* SDHI_1_IXRST */
 	DEF_RST(10, 9, 4, 26),		/* SDHI_2_IXRST */
 	DEF_RST(10, 10, 4, 27),		/* USB3_0_ARESETN */
+	DEF_RST(10, 12, 4, 29),		/* USB2_0_U2H0_HRESETN */
+	DEF_RST(10, 13, 4, 30),		/* USB2_0_U2H1_HRESETN */
+	DEF_RST(10, 14, 4, 31),		/* USB2_0_U2P_EXL_SYSRST */
+	DEF_RST(10, 15, 5, 0),		/* USB2_0_PRESETN */
 	DEF_RST(11, 0, 5, 1),		/* GBETH_0_ARESETN_I */
 	DEF_RST(11, 1, 5, 2),		/* GBETH_1_ARESETN_I */
 	DEF_RST(12, 5, 5, 22),		/* CRU_0_PRESETN */
-- 
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Re: [PATCH 09/18] clk: renesas: r9a09g047: Add clock and reset entries for USB2

[Geert Uytterhoeven]

On Wed, 1 Oct 2025 at 23:28, Tommaso Merciai
<tommaso.merciai.xr@bp.renesas.com> wrote:
> Add clock and reset entries for USB2.
>
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>

I couldn't verify all details, due to the lack of the Additional Manual,
but the rest LGTM, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk for v6.19.

Gr{oetje,eeting}s,

                        Geert

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[PATCH 10/18] dt-bindings: usb: renesas,usbhs: Add RZ/G3E SoC support

[Tommaso Merciai]

Document the Renesas USBHS controller found on the Renesas RZ/G3E SoC.
The USBHS block on RZ/G3E is functionally identical to the one found
on the RZ/G2L family, so no driver changes are needed. The existing
"renesas,rzg2l-usbhs" fallback compatible will continue to be used for
handling this IP.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 Documentation/devicetree/bindings/usb/renesas,usbhs.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
index 0b8b90dd1951..dc74e70f1b92 100644
--- a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
+++ b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
@@ -27,6 +27,7 @@ properties:
               - renesas,usbhs-r9a07g044 # RZ/G2{L,LC}
               - renesas,usbhs-r9a07g054 # RZ/V2L
               - renesas,usbhs-r9a08g045 # RZ/G3S
+              - renesas,usbhs-r9a09g047 # RZ/G3E
               - renesas,usbhs-r9a09g056 # RZ/V2N
               - renesas,usbhs-r9a09g057 # RZ/V2H(P)
           - const: renesas,rzg2l-usbhs
-- 
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[PATCH 11/18] dt-bindings: phy: renesas,usb2-phy: Document RZ/G3E SoC

[Tommaso Merciai]

Document USB2.0 phy bindings for RZ/G3E ("R9A09G047") SoC.

The RZ/G3E USB2.0 phy is functionally identical to the one found
on the RZ/V2H(P), so no driver changes are needed. The existing
"renesas,usb2-phy-r9a09g057" will be used as a fallback compatible for
this IP.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
index dde5269b0db2..80d80b4ce523 100644
--- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
@@ -41,7 +41,9 @@ properties:
           - const: renesas,rzg2l-usb2-phy
 
       - items:
-          - const: renesas,usb2-phy-r9a09g056 # RZ/V2N
+          - enum:
+              - renesas,usb2-phy-r9a09g047 # RZ/G3E
+              - renesas,usb2-phy-r9a09g056 # RZ/V2N
           - const: renesas,usb2-phy-r9a09g057
 
       - const: renesas,usb2-phy-r9a09g077 # RZ/T2H
-- 
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[PATCH 12/18] dt-bindings: reset: Document RZ/G3E USB2PHY reset

[Tommaso Merciai]

Document USB2PHY reset controller bindings for RZ/G3E ("R9A09G047") SoC.

The RZ/G3E USB2PHY reset controller is functionally identical to the one
found on the RZ/V2H(P), so no driver changes are needed. The existing
"renesas,r9a09g057-usb2phy-reset" will be used as a fallback compatible
for this IP.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 .../bindings/reset/renesas,rzv2h-usb2phy-reset.yaml           | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml b/Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml
index c1b800a10b53..567c998d3c85 100644
--- a/Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml
+++ b/Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml
@@ -17,7 +17,9 @@ properties:
   compatible:
     oneOf:
       - items:
-          - const: renesas,r9a09g056-usb2phy-reset # RZ/V2N
+          - enum:
+              - renesas,r9a09g047-usb2phy-reset # RZ/G3E
+              - renesas,r9a09g056-usb2phy-reset # RZ/V2N
           - const: renesas,r9a09g057-usb2phy-reset
 
       - const: renesas,r9a09g057-usb2phy-reset # RZ/V2H(P)
-- 
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[PATCH 13/18] arm64: dts: renesas: r9a09g056: Add USB2.0 PHY VBUS internal regulator node

[Tommaso Merciai]

USB2.0 PHY of the RZ/V2N SoC can drive VBUS line via the VBOUT bit of
the VBCTRL register.

Add VBUS regulator nodes (usb2_phy0_vbus_otg) under the usb2_phy0
node to describe this hw functionality.

This enables proper management of VBUS for USB2.0 OTG devices and ensures
compliance with hardware requirements.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
index 887110878906..1cd489e3df52 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
@@ -659,6 +659,12 @@ usb2_phy0: usb-phy@15800200 {
 			#phy-cells = <1>;
 			power-domains = <&cpg>;
 			status = "disabled";
+
+			usb2_phy0_vbus_otg: vbus-regulator {
+				regulator-name = "USB2PHY0-VBUS-OTG";
+				regulator-boot-on;
+				status = "disabled";
+			};
 		};
 
 		hsusb: usb@15820000 {
-- 
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[PATCH 14/18] arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable USB2 PHY0 VBUS support

[Tommaso Merciai]

Enable the vbus-supply and status properties for USB2 PHY0 and its
VBUS OTG regulator in the r9a09g056n48-rzv2n-evk device tree.

Enabling them ensures proper VBUS handling and reliable USB OTG
operation on the channel.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts
index 066e66b5d51a..54ed7cb2d73b 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts
@@ -389,6 +389,11 @@ &usb2_phy0 {
 	pinctrl-0 = <&usb20_pins>;
 	pinctrl-names = "default";
 
+	vbus-supply = <&usb2_phy0_vbus_otg>;
+	status = "okay";
+};
+
+&usb2_phy0_vbus_otg {
 	status = "okay";
 };
 
-- 
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[PATCH 15/18] arm64: dts: renesas: r9a09g057: Add USB2.0 PHY VBUS internal regulator node

[Tommaso Merciai]

USB2.0 PHY of the RZ/V2H(P) SoC can drive VBUS line via the VBOUT bit of
the VBCTRL register.

Add VBUS regulator nodes (usb2_phy0_vbus_otg) under the usb2_phy0
nodes to describe this hw functionality.

This enables proper management of VBUS for USB2.0 OTG devices and ensures
compliance with hardware requirements.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 630f7a98df38..73b7d6cc2db0 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -985,6 +985,12 @@ usb2_phy0: usb-phy@15800200 {
 			#phy-cells = <1>;
 			power-domains = <&cpg>;
 			status = "disabled";
+
+			usb2_phy0_vbus_otg: vbus-regulator {
+				regulator-name = "USB2PHY0-VBUS-OTG";
+				regulator-boot-on;
+				status = "disabled";
+			};
 		};
 
 		usb2_phy1: usb-phy@15810200 {
-- 
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[PATCH 16/18] arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable USB2 PHY0 VBUS support

[Tommaso Merciai]

Enable the vbus-supply and status properties for USB2 PHY0 and its
VBUS OTG regulator in the r9a09g057h44-rzv2h-evk device tree.

Enabling them ensures proper VBUS handling and reliable USB OTG
operation on the channel.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
index 5c06bce3d5b4..69ca9f0381f3 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
@@ -423,6 +423,11 @@ &usb2_phy0 {
 	pinctrl-0 = <&usb20_pins>;
 	pinctrl-names = "default";
 
+	vbus-supply = <&usb2_phy0_vbus_otg>;
+	status = "okay";
+};
+
+&usb2_phy0_vbus_otg {
 	status = "okay";
 };
 
-- 
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[PATCH 17/18] arm64: dts: renesas: r9a09g047: Add USB2.0 support

[Tommaso Merciai]

The Renesas RZ/G3E ("R9A09G047") SoC supports 1x channel with OTG/DRD
and 1x channel with host interface.

Add the ECHI, OHCI, USB2.0 PHY and reset control nodes for USB2.0 channels
in R9A09G047 SoC DTSI.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 122 +++++++++++++++++++++
 1 file changed, 122 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index 47d843c79021..6c48ef5f4188 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -836,6 +836,128 @@ gic: interrupt-controller@14900000 {
 			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
 		};
 
+		ohci0: usb@15800000 {
+			compatible = "generic-ohci";
+			reg = <0 0x15800000 0 0x100>;
+			interrupts = <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>;
+			resets = <&usb20phyrst>, <&cpg 0xac>;
+			phys = <&usb2_phy0 1>;
+			phy-names = "usb";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		ohci1: usb@15810000 {
+			compatible = "generic-ohci";
+			reg = <0 0x15810000 0 0x100>;
+			interrupts = <GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 0xb4>, <&cpg CPG_MOD 0xb7>;
+			resets = <&usb21phyrst>, <&cpg 0xad>;
+			phys = <&usb2_phy1 1>;
+			phy-names = "usb";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		ehci0: usb@15800100 {
+			compatible = "generic-ehci";
+			reg = <0 0x15800100 0 0x100>;
+			interrupts = <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>;
+			resets = <&usb20phyrst>, <&cpg 0xac>;
+			phys = <&usb2_phy0 2>;
+			phy-names = "usb";
+			companion = <&ohci0>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		ehci1: usb@15810100 {
+			compatible = "generic-ehci";
+			reg = <0 0x15810100 0 0x100>;
+			interrupts = <GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 0xb4>, <&cpg CPG_MOD 0xb7>;
+			resets = <&usb21phyrst>, <&cpg 0xad>;
+			phys = <&usb2_phy1 2>;
+			phy-names = "usb";
+			companion = <&ohci1>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		usb2_phy0: usb-phy@15800200 {
+			compatible = "renesas,usb2-phy-r9a09g047",
+				     "renesas,usb2-phy-r9a09g057";
+			reg = <0 0x15800200 0 0x700>;
+			interrupts = <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 0xb3>,
+				 <&cpg CPG_CORE R9A09G047_USB2_0_CLK_CORE0>;
+			clock-names = "fck", "usb_x1";
+			resets = <&usb20phyrst>;
+			#phy-cells = <1>;
+			power-domains = <&cpg>;
+			status = "disabled";
+
+			usb2_phy0_vbus_otg: vbus-regulator {
+				regulator-name = "USB2PHY0-VBUS-OTG";
+				regulator-boot-on;
+				status = "disabled";
+			};
+		};
+
+		usb2_phy1: usb-phy@15810200 {
+			compatible = "renesas,usb2-phy-r9a09g047",
+				     "renesas,usb2-phy-r9a09g057";
+			reg = <0 0x15810200 0 0x700>;
+			interrupts = <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 0xb4>,
+				 <&cpg CPG_CORE R9A09G047_USB2_0_CLK_CORE1>;
+			clock-names = "fck", "usb_x1";
+			resets = <&usb21phyrst>;
+			#phy-cells = <1>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		hsusb: usb@15820000 {
+			compatible = "renesas,usbhs-r9a09g047",
+				     "renesas,rzg2l-usbhs";
+			reg = <0 0x15820000 0 0x10000>;
+			interrupts = <GIC_SPI 751 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb5>;
+			resets = <&usb20phyrst>, <&cpg 0xae>;
+			phys = <&usb2_phy0 3>;
+			phy-names = "usb";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		usb20phyrst: reset-controller@15830000 {
+			compatible = "renesas,r9a09g047-usb2phy-reset",
+				     "renesas,r9a09g057-usb2phy-reset";
+			reg = <0 0x15830000 0 0x10000>;
+			clocks = <&cpg CPG_MOD 0xb6>;
+			resets = <&cpg 0xaf>;
+			power-domains = <&cpg>;
+			#reset-cells = <0>;
+			status = "disabled";
+		};
+
+		usb21phyrst: reset-controller@15840000 {
+			compatible = "renesas,r9a09g047-usb2phy-reset",
+				     "renesas,r9a09g057-usb2phy-reset";
+			reg = <0 0x15840000 0 0x10000>;
+			clocks = <&cpg CPG_MOD 0xb7>;
+			resets = <&cpg 0xaf>;
+			power-domains = <&cpg>;
+			#reset-cells = <0>;
+			status = "disabled";
+		};
+
 		sdhi0: mmc@15c00000  {
 			compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057";
 			reg = <0x0 0x15c00000 0 0x10000>;
-- 
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[PATCH 18/18] arm64: dts: renesas: r9a09g047e57-smarc: Enable USB2.0 support

[Tommaso Merciai]

Enable USB2.0 support on the RZ/G3E EVK board, USB1B_1A_HOST and
USB5_4_HOST connectors support only host operation and USB0_OTG
supports host/peripheral operation.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 .../boot/dts/renesas/r9a09g047e57-smarc.dts   | 49 +++++++++++++++++++
 .../boot/dts/renesas/renesas-smarc2.dtsi      | 23 +++++++++
 2 files changed, 72 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
index 08e814c03fa8..ca19e8628c80 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
@@ -164,6 +164,28 @@ sd1-data {
 				 <RZG3E_PORT_PINMUX(G, 5, 1)>; /* SD1DAT3 */
 		};
 	};
+
+	usb20_pins: usb20 {
+		ovc {
+			pinmux =  <RZG3E_PORT_PINMUX(0, 0, 12)>; /* OVC */
+			bias-pull-up;
+		};
+
+		vbus {
+			pinmux = <RZG3E_PORT_PINMUX(0, 1, 12)>; /* VBUS */
+		};
+	};
+
+	usb21_pins: usb21 {
+		ovc {
+			pinmux = <RZG3E_PORT_PINMUX(G, 6, 12)>; /* OVC */
+			bias-pull-up;
+		};
+
+		vbus {
+			pinmux = <RZG3E_PORT_PINMUX(K, 3, 12)>; /* VBUS */
+		};
+	};
 };
 
 &scif0 {
@@ -179,3 +201,30 @@ &sdhi1 {
 	vmmc-supply = <&reg_3p3v>;
 	vqmmc-supply = <&vqmmc_sd1_pvdd>;
 };
+
+&usb20phyrst {
+	status = "okay";
+};
+
+&usb21phyrst {
+	status = "okay";
+};
+
+&usb2_phy0 {
+	pinctrl-0 = <&usb20_pins>;
+	pinctrl-names = "default";
+
+	vbus-supply = <&usb2_phy0_vbus_otg>;
+	status = "okay";
+};
+
+&usb2_phy0_vbus_otg {
+	status = "okay";
+};
+
+&usb2_phy1 {
+	pinctrl-0 = <&usb21_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
index 58561da3007a..2daf437abb82 100644
--- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
+++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
@@ -90,11 +90,34 @@ &canfd {
 	status = "okay";
 };
 
+&ehci0 {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&hsusb {
+	dr_mode = "otg";
+	status = "okay";
+};
+
 &i2c0 {
 	status = "okay";
 	clock-frequency = <400000>;
 };
 
+&ohci0 {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&ohci1 {
+	status = "okay";
+};
+
 &scif0 {
 	status = "okay";
 };
-- 
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Re: [PATCH 00/18] Add USB2.0 support for RZ/G3E

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 3322 bytes --]

On Wed, Oct 01, 2025 at 11:26:44PM +0200, Tommaso Merciai wrote:
> Dear All,
> 
> This patch series adds USB2.0 support for the Renesas R9A09G047 (RZ/G3E)
> SoC and enables it on the RZ/G3E SMARC II board.
> The RZ/G3E USB2.0 IP is identical to that used in the RZ/V2H (R9A09G057),
> so the existing support has been extended accordingly.
> 
> The series applies on top of [1] and [2] and includes driver cleanups,
> VBUS/OTG handling fixes, regulator improvements, clock/reset additions,
> and device tree updates for RZ/G3E, RZ/V2H, and RZ/V2N SoCs and boards.
> 
> Thanks & Regards,
> Tommaso

If you're not gonna CC me on all the patches in the series, please at
least CC me on the cover so I have an idea about what is going on in the
rest of the set.
All the bindings are
Acked-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.

> 
> [1] https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=1001788
> [2] https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=1006104
> 
> Tommaso Merciai (18):
>   phy: renesas: rcar-gen3-usb2: Use devm_pm_runtime_enable()
>   phy: renesas: rcar-gen3-usb2: Factor out VBUS control logic
>   reset: rzv2h-usb2phy: Simplify pm_runtime driver handling
>   reset: rzv2h-usb2phy: Set VBENCTL register for OTG mode
>   dt-bindings: phy: renesas,usb2-phy: Document USB VBUS regulator
>   phy: renesas: rcar-gen3-usb2: Add regulator for OTG VBUS control
>   regulator: devres: Disable exclusive regulator before releasing
>   dt-bindings: clock: renesas,r9a09g047-cpg: Add USB2 PHY core clocks
>   clk: renesas: r9a09g047: Add clock and reset entries for USB2
>   dt-bindings: usb: renesas,usbhs: Add RZ/G3E SoC support
>   dt-bindings: phy: renesas,usb2-phy: Document RZ/G3E SoC
>   dt-bindings: reset: Document RZ/G3E USB2PHY reset
>   arm64: dts: renesas: r9a09g056: Add USB2.0 PHY VBUS internal regulator
>     node
>   arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable USB2 PHY0 VBUS
>     support
>   arm64: dts: renesas: r9a09g057: Add USB2.0 PHY VBUS internal regulator
>     node
>   arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable USB2 PHY0 VBUS
>     support
>   arm64: dts: renesas: r9a09g047: Add USB2.0 support
>   arm64: dts: renesas: r9a09g047e57-smarc: Enable USB2.0 support
> 
>  .../bindings/phy/renesas,usb2-phy.yaml        |  10 +-
>  .../reset/renesas,rzv2h-usb2phy-reset.yaml    |   4 +-
>  .../bindings/usb/renesas,usbhs.yaml           |   1 +
>  arch/arm64/boot/dts/renesas/r9a09g047.dtsi    | 122 +++++++++++
>  .../boot/dts/renesas/r9a09g047e57-smarc.dts   |  49 +++++
>  arch/arm64/boot/dts/renesas/r9a09g056.dtsi    |   6 +
>  .../dts/renesas/r9a09g056n48-rzv2n-evk.dts    |   5 +
>  arch/arm64/boot/dts/renesas/r9a09g057.dtsi    |   6 +
>  .../dts/renesas/r9a09g057h44-rzv2h-evk.dts    |   5 +
>  .../boot/dts/renesas/renesas-smarc2.dtsi      |  23 ++
>  drivers/clk/renesas/r9a09g047-cpg.c           |  18 +-
>  drivers/phy/renesas/phy-rcar-gen3-usb2.c      | 199 +++++++++++++-----
>  drivers/regulator/devres.c                    |   8 +-
>  drivers/reset/reset-rzv2h-usb2phy.c           | 105 ++++++---
>  .../dt-bindings/clock/renesas,r9a09g047-cpg.h |   2 +
>  15 files changed, 478 insertions(+), 85 deletions(-)
> 
> -- 
> 2.43.0
> 

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Re: [PATCH 00/18] Add USB2.0 support for RZ/G3E

[Tommaso Merciai]

Hi Conor,
Thanks for your review.

On Thu, Oct 02, 2025 at 07:48:57PM +0100, Conor Dooley wrote:
> On Wed, Oct 01, 2025 at 11:26:44PM +0200, Tommaso Merciai wrote:
> > Dear All,
> > 
> > This patch series adds USB2.0 support for the Renesas R9A09G047 (RZ/G3E)
> > SoC and enables it on the RZ/G3E SMARC II board.
> > The RZ/G3E USB2.0 IP is identical to that used in the RZ/V2H (R9A09G057),
> > so the existing support has been extended accordingly.
> > 
> > The series applies on top of [1] and [2] and includes driver cleanups,
> > VBUS/OTG handling fixes, regulator improvements, clock/reset additions,
> > and device tree updates for RZ/G3E, RZ/V2H, and RZ/V2N SoCs and boards.
> > 
> > Thanks & Regards,
> > Tommaso
> 
> If you're not gonna CC me on all the patches in the series, please at
> least CC me on the cover so I have an idea about what is going on in the
> rest of the set.

Sorry, I made a mistake when I sent the series.
I only ran ./scripts/get_maintainer.pl on some patches, not all.
My fault.

> All the bindings are
> Acked-by: Conor Dooley <conor.dooley@microchip.com>

Thanks for your tag!

Regards,
Tommaso

> 
> Cheers,
> Conor.
> 
> > 
> > [1] https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=1001788
> > [2] https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=1006104
> > 
> > Tommaso Merciai (18):
> >   phy: renesas: rcar-gen3-usb2: Use devm_pm_runtime_enable()
> >   phy: renesas: rcar-gen3-usb2: Factor out VBUS control logic
> >   reset: rzv2h-usb2phy: Simplify pm_runtime driver handling
> >   reset: rzv2h-usb2phy: Set VBENCTL register for OTG mode
> >   dt-bindings: phy: renesas,usb2-phy: Document USB VBUS regulator
> >   phy: renesas: rcar-gen3-usb2: Add regulator for OTG VBUS control
> >   regulator: devres: Disable exclusive regulator before releasing
> >   dt-bindings: clock: renesas,r9a09g047-cpg: Add USB2 PHY core clocks
> >   clk: renesas: r9a09g047: Add clock and reset entries for USB2
> >   dt-bindings: usb: renesas,usbhs: Add RZ/G3E SoC support
> >   dt-bindings: phy: renesas,usb2-phy: Document RZ/G3E SoC
> >   dt-bindings: reset: Document RZ/G3E USB2PHY reset
> >   arm64: dts: renesas: r9a09g056: Add USB2.0 PHY VBUS internal regulator
> >     node
> >   arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable USB2 PHY0 VBUS
> >     support
> >   arm64: dts: renesas: r9a09g057: Add USB2.0 PHY VBUS internal regulator
> >     node
> >   arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable USB2 PHY0 VBUS
> >     support
> >   arm64: dts: renesas: r9a09g047: Add USB2.0 support
> >   arm64: dts: renesas: r9a09g047e57-smarc: Enable USB2.0 support
> > 
> >  .../bindings/phy/renesas,usb2-phy.yaml        |  10 +-
> >  .../reset/renesas,rzv2h-usb2phy-reset.yaml    |   4 +-
> >  .../bindings/usb/renesas,usbhs.yaml           |   1 +
> >  arch/arm64/boot/dts/renesas/r9a09g047.dtsi    | 122 +++++++++++
> >  .../boot/dts/renesas/r9a09g047e57-smarc.dts   |  49 +++++
> >  arch/arm64/boot/dts/renesas/r9a09g056.dtsi    |   6 +
> >  .../dts/renesas/r9a09g056n48-rzv2n-evk.dts    |   5 +
> >  arch/arm64/boot/dts/renesas/r9a09g057.dtsi    |   6 +
> >  .../dts/renesas/r9a09g057h44-rzv2h-evk.dts    |   5 +
> >  .../boot/dts/renesas/renesas-smarc2.dtsi      |  23 ++
> >  drivers/clk/renesas/r9a09g047-cpg.c           |  18 +-
> >  drivers/phy/renesas/phy-rcar-gen3-usb2.c      | 199 +++++++++++++-----
> >  drivers/regulator/devres.c                    |   8 +-
> >  drivers/reset/reset-rzv2h-usb2phy.c           | 105 ++++++---
> >  .../dt-bindings/clock/renesas,r9a09g047-cpg.h |   2 +
> >  15 files changed, 478 insertions(+), 85 deletions(-)
> > 
> > -- 
> > 2.43.0
> > 



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