[PATCH v2 0/3] phy: qcom: qmp-pcie: Add vdda-refgen supply support for Glymur

[PATCH v2 0/3] phy: qcom: qmp-pcie: Add vdda-refgen supply support for Glymur

[Qiang Yu]

The PCIe QMP PHYs on Glymur require both refgen for stable reference
voltage and qref for stable reference clock. The refgen requires two power
supplies: vdda-refgen0p9 and vdda-refgen1p2.

can be extended in the future.

This series creates a Glymur-specific supply list including the refgen
supplies and updates both Gen5x4 and Gen4x2 configurations to use it.

Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>

Changes in v2:
- Add dts patch in this series.
- Reword commit msg of dtbinding patch.
- Link to v1: https://lore.kernel.org/all/20260208-refgen-v1-0-87ca84fd78b3@oss.qualcomm.com/ 

---
Qiang Yu (3):
      dt-bindings: phy: sc8280xp-qmp-pcie: Add vdda-refgen supply for Glymur
      phy: qcom: qmp-pcie: Add vdda-refgen supplies for Glymur
      arm64: dts: qcom: glymur-crd: Add refgen supplies for PCIe PHY on Glymur

 .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml         | 16 ++++++++++++++++
 arch/arm64/boot/dts/qcom/glymur-crd.dtsi                 |  8 ++++++++
 drivers/phy/qualcomm/phy-qcom-qmp-pcie.c                 | 12 ++++++++----
 3 files changed, 32 insertions(+), 4 deletions(-)
---
base-commit: 3ce97bd3c4f18608335e709c24d6a40e7036cab8
change-id: 20260621-phy_refgen-db77317ec05a

Best regards,
--  
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[PATCH v2 1/3] dt-bindings: phy: sc8280xp-qmp-pcie: Add vdda-refgen supply for Glymur

[Qiang Yu]

The PCIe QMP PHYs require a stable reference voltage provided by REFGEN,
which in turn requires two separate LDOs to operate.

Add vdda-refgen0p9-supply and vdda-refgen1p2-supply properties. Mark them
as required for the Glymur PCIe QMP PHYs for now; other platforms having
the same requirement and can be added later.

Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
---
 .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml         | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
index 108cf9dc86ea..375f5fb2111f 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
@@ -91,6 +91,10 @@ properties:
 
   vdda-qref-supply: true
 
+  vdda-refgen0p9-supply: true
+
+  vdda-refgen1p2-supply: true
+
   qcom,4ln-config-sel:
     description: PCIe 4-lane configuration
     $ref: /schemas/types.yaml#/definitions/phandle-array
@@ -261,6 +265,18 @@ allOf:
         "#clock-cells":
           const: 0
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,glymur-qmp-gen4x2-pcie-phy
+              - qcom,glymur-qmp-gen5x4-pcie-phy
+    then:
+      required:
+        - vdda-refgen0p9-supply
+        - vdda-refgen1p2-supply
+
 examples:
   - |
     #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>

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Re: [PATCH v2 1/3] dt-bindings: phy: sc8280xp-qmp-pcie: Add vdda-refgen supply for Glymur

[Krzysztof Kozlowski]

On Tue, Jun 23, 2026 at 06:05:17AM -0700, Qiang Yu wrote:
> The PCIe QMP PHYs require a stable reference voltage provided by REFGEN,
> which in turn requires two separate LDOs to operate.
> 
> Add vdda-refgen0p9-supply and vdda-refgen1p2-supply properties. Mark them
> as required for the Glymur PCIe QMP PHYs for now; other platforms having
> the same requirement and can be added later.
> 
> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> ---
>  .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml         | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof


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[PATCH v2 2/3] phy: qcom: qmp-pcie: Add vdda-refgen supplies for Glymur

[Qiang Yu]

The refgen providing reference voltage for PCIe QMP PHY on Glymur requires
two power supplies independent from the PHY's core and qref rails. Add
support for vdda-refgen0p9 and vdda-refgen1p2 supplies with a dedicated
glymur_qmp_phy_vreg_l list.

Update both Gen5x4 and Gen4x2 configurations to use the new supply list.

Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
---
 drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index d3effad7a074..08bc89ce80e1 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -3488,6 +3488,10 @@ static const char * const sm8550_qmp_phy_vreg_l[] = {
 	"vdda-phy", "vdda-pll", "vdda-qref",
 };
 
+static const char * const glymur_qmp_phy_vreg_l[] = {
+	"vdda-phy", "vdda-pll", "vdda-refgen0p9", "vdda-refgen1p2",
+};
+
 /* list of resets */
 static const char * const ipq8074_pciephy_reset_l[] = {
 	"phy", "common",
@@ -4756,8 +4760,8 @@ static const struct qmp_phy_cfg glymur_qmp_gen5x4_pciephy_cfg = {
 
 	.reset_list		= sdm845_pciephy_reset_l,
 	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),
-	.vreg_list		= qmp_phy_vreg_l,
-	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
+	.vreg_list		= glymur_qmp_phy_vreg_l,
+	.num_vregs		= ARRAY_SIZE(glymur_qmp_phy_vreg_l),
 
 	.regs			= pciephy_v8_50_regs_layout,
 
@@ -4772,8 +4776,8 @@ static const struct qmp_phy_cfg glymur_qmp_gen4x2_pciephy_cfg = {
 
 	.reset_list		= sdm845_pciephy_reset_l,
 	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),
-	.vreg_list		= qmp_phy_vreg_l,
-	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
+	.vreg_list		= glymur_qmp_phy_vreg_l,
+	.num_vregs		= ARRAY_SIZE(glymur_qmp_phy_vreg_l),
 
 	.regs			= pciephy_v8_regs_layout,
 

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[PATCH v2 3/3] arm64: dts: qcom: glymur-crd: Add refgen supplies for PCIe PHY on Glymur

[Qiang Yu]

The PCIe PHYs on Glymur require a reference voltage provided by REFGEN,
which in turn is powered by two LDOs.

Since there is no devicetree node for REFGEN, add the vdda-refgen0p9 and
vdda-refgen1p2 supplies for each PCIe PHY node.

Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
index e784b538f42e..bdf7db3493bd 100644
--- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
@@ -454,6 +454,8 @@ &pcie3b {
 &pcie3b_phy {
 	vdda-phy-supply = <&vreg_l3c_e1_0p89>;
 	vdda-pll-supply = <&vreg_l2c_e1_1p14>;
+	vdda-refgen0p9-supply = <&vreg_l1c_e1_0p82>;
+	vdda-refgen1p2-supply = <&vreg_l4f_e1_1p08>;
 };
 
 &pcie3b_port0 {
@@ -471,6 +473,8 @@ &pcie4 {
 &pcie4_phy {
 	vdda-phy-supply = <&vreg_l1c_e1_0p82>;
 	vdda-pll-supply = <&vreg_l4f_e1_1p08>;
+	vdda-refgen0p9-supply = <&vreg_l1c_e1_0p82>;
+	vdda-refgen1p2-supply = <&vreg_l4f_e1_1p08>;
 
 	status = "okay";
 };
@@ -507,6 +511,8 @@ &pcie5 {
 &pcie5_phy {
 	vdda-phy-supply = <&vreg_l2f_e0_0p82>;
 	vdda-pll-supply = <&vreg_l4h_e0_1p2>;
+	vdda-refgen0p9-supply = <&vreg_l2f_e0_0p82>;
+	vdda-refgen1p2-supply = <&vreg_l4h_e0_1p2>;
 
 	status = "okay";
 };
@@ -528,6 +534,8 @@ &pcie6 {
 &pcie6_phy {
 	vdda-phy-supply = <&vreg_l1c_e1_0p82>;
 	vdda-pll-supply = <&vreg_l4f_e1_1p08>;
+	vdda-refgen0p9-supply = <&vreg_l1c_e1_0p82>;
+	vdda-refgen1p2-supply = <&vreg_l4f_e1_1p08>;
 
 	status = "okay";
 };

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Re: [PATCH v2 0/3] phy: qcom: qmp-pcie: Add vdda-refgen supply support for Glymur

[Konrad Dybcio]

On 6/23/26 3:05 PM, Qiang Yu wrote:
> The PCIe QMP PHYs on Glymur require both refgen for stable reference
> voltage and qref for stable reference clock. The refgen requires two power
> supplies: vdda-refgen0p9 and vdda-refgen1p2.
> 
> can be extended in the future.
> 
> This series creates a Glymur-specific supply list including the refgen
> supplies and updates both Gen5x4 and Gen4x2 configurations to use it.
> 
> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> 
> Changes in v2:
> - Add dts patch in this series.
> - Reword commit msg of dtbinding patch.
> - Link to v1: https://lore.kernel.org/all/20260208-refgen-v1-0-87ca84fd78b3@oss.qualcomm.com/ 
> 
> ---

Is this necessary (for Glymur) now that we correlated some of the
TCSR clocks with the right nodes?

Perhaps this would be necessary for Mahua since its clocks don't
require QREF (or we can lie about it and handle them there)?

Konrad

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Re: [PATCH v2 0/3] phy: qcom: qmp-pcie: Add vdda-refgen supply support for Glymur

[Qiang Yu]

On Mon, Jun 29, 2026 at 12:51:55PM +0200, Konrad Dybcio wrote:
> On 6/23/26 3:05 PM, Qiang Yu wrote:
> > The PCIe QMP PHYs on Glymur require both refgen for stable reference
> > voltage and qref for stable reference clock. The refgen requires two power
> > supplies: vdda-refgen0p9 and vdda-refgen1p2.
> > 
> > can be extended in the future.
> > 
> > This series creates a Glymur-specific supply list including the refgen
> > supplies and updates both Gen5x4 and Gen4x2 configurations to use it.
> > 
> > Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> > 
> > Changes in v2:
> > - Add dts patch in this series.
> > - Reword commit msg of dtbinding patch.
> > - Link to v1: https://lore.kernel.org/all/20260208-refgen-v1-0-87ca84fd78b3@oss.qualcomm.com/ 
> > 
> > ---
> 
> Is this necessary (for Glymur) now that we correlated some of the
> TCSR clocks with the right nodes?

This patch is necessary for glymur and mahua and other Qualcomm targets,
which can be verified from the REFGEN page and power grid page on ipcat.

Take Glymur PCIe3 PHY as an example: it requires two REFGENs — REFGEN0 for
the PHY itself and REFGEN4 for QREF. In the TCSR driver, only the LDOs for
REFGEN4 are voted, not REFGEN0. This is intentional: each consumer is
responsible for voting the LDOs of the REFGEN it uses. Since QREF uses
REFGEN4, the TCSR driver votes the REFGEN4 LDOs; since the PHY uses
REFGEN0, the PHY driver votes the REFGEN0 LDOs.

For some PHY instances in power grid, you can only see one REFGEN, that
indicates the phy doesn't require QREF or the phy and the QREF it requires
share same REFGEN.
> 
> Perhaps this would be necessary for Mahua since its clocks don't
> require QREF (or we can lie about it and handle them there)?

For Mahua PCIe5 PHY, it doesn't require QREF. So we don't need to vote
REFGEN LDOs for QREF in tcsr driver. But the PHY requires REFGEN. So we
still need to vote in PHY driver.

- Qiang Yu

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Re: [PATCH v2 0/3] phy: qcom: qmp-pcie: Add vdda-refgen supply support for Glymur

[Konrad Dybcio]

On 6/29/26 2:14 PM, Qiang Yu wrote:
> On Mon, Jun 29, 2026 at 12:51:55PM +0200, Konrad Dybcio wrote:
>> On 6/23/26 3:05 PM, Qiang Yu wrote:
>>> The PCIe QMP PHYs on Glymur require both refgen for stable reference
>>> voltage and qref for stable reference clock. The refgen requires two power
>>> supplies: vdda-refgen0p9 and vdda-refgen1p2.
>>>
>>> can be extended in the future.
>>>
>>> This series creates a Glymur-specific supply list including the refgen
>>> supplies and updates both Gen5x4 and Gen4x2 configurations to use it.
>>>
>>> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
>>>
>>> Changes in v2:
>>> - Add dts patch in this series.
>>> - Reword commit msg of dtbinding patch.
>>> - Link to v1: https://lore.kernel.org/all/20260208-refgen-v1-0-87ca84fd78b3@oss.qualcomm.com/ 
>>>
>>> ---
>>
>> Is this necessary (for Glymur) now that we correlated some of the
>> TCSR clocks with the right nodes?
> 
> This patch is necessary for glymur and mahua and other Qualcomm targets,
> which can be verified from the REFGEN page and power grid page on ipcat.
> 
> Take Glymur PCIe3 PHY as an example: it requires two REFGENs — REFGEN0 for
> the PHY itself and REFGEN4 for QREF. In the TCSR driver, only the LDOs for
> REFGEN4 are voted, not REFGEN0. This is intentional: each consumer is
> responsible for voting the LDOs of the REFGEN it uses. Since QREF uses
> REFGEN4, the TCSR driver votes the REFGEN4 LDOs; since the PHY uses
> REFGEN0, the PHY driver votes the REFGEN0 LDOs.
> 
> For some PHY instances in power grid, you can only see one REFGEN, that
> indicates the phy doesn't require QREF or the phy and the QREF it requires
> share same REFGEN.
>>
>> Perhaps this would be necessary for Mahua since its clocks don't
>> require QREF (or we can lie about it and handle them there)?
> 
> For Mahua PCIe5 PHY, it doesn't require QREF. So we don't need to vote
> REFGEN LDOs for QREF in tcsr driver. But the PHY requires REFGEN. So we
> still need to vote in PHY driver.

OK, I think I got my mental model of all of this straight. But expect
me to make more mistakes and sorry for that!

Konrad

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