* [PATCH v6 1/7] dt-bindings: phy: qcom,x1e80100-csi2-phy: Add SM8750 CSI2 PHY
2026-07-21 12:45 [PATCH v6 0/7] media: qcom: camss: Add SM8750 support Hangxiang Ma
@ 2026-07-21 12:46 ` Hangxiang Ma
2026-07-22 6:57 ` Krzysztof Kozlowski
2026-07-21 12:46 ` [PATCH v6 2/7] media: dt-bindings: Add CAMSS device for SM8750 Hangxiang Ma
` (6 subsequent siblings)
7 siblings, 1 reply; 15+ messages in thread
From: Hangxiang Ma @ 2026-07-21 12:46 UTC (permalink / raw)
To: Robert Foss, Todor Tomov, Bryan O'Donoghue,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Loic Poulain, Vinod Koul, Neil Armstrong
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, linux-phy,
jeyaprakash.soundrapandian, Vijay Kumar Tumati, Hangxiang Ma
The SM8750 camera subsystem exposes six CSI2 D-PHY blocks that follow the
same programming model as Kaanapali. Describe the SM8750 CSI2 PHY using a
"qcom,sm8750-csi2-phy" compatible with the "qcom,kaanapali-csi2-phy"
fallback, so the CAMSS binding can instantiate the CSIPHY nodes as
separate phy devices.
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
---
.../devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
index 7943049834f9..95375efb2597 100644
--- a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
@@ -16,9 +16,13 @@ description:
properties:
compatible:
- enum:
- - qcom,kaanapali-csi2-phy
- - qcom,x1e80100-csi2-phy
+ oneOf:
+ - enum:
+ - qcom,kaanapali-csi2-phy
+ - qcom,x1e80100-csi2-phy
+ - items:
+ - const: qcom,sm8750-csi2-phy
+ - const: qcom,kaanapali-csi2-phy
reg:
maxItems: 1
--
2.34.1
--
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https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v6 1/7] dt-bindings: phy: qcom,x1e80100-csi2-phy: Add SM8750 CSI2 PHY
2026-07-21 12:46 ` [PATCH v6 1/7] dt-bindings: phy: qcom,x1e80100-csi2-phy: Add SM8750 CSI2 PHY Hangxiang Ma
@ 2026-07-22 6:57 ` Krzysztof Kozlowski
2026-07-22 8:19 ` Hangxiang Ma
0 siblings, 1 reply; 15+ messages in thread
From: Krzysztof Kozlowski @ 2026-07-22 6:57 UTC (permalink / raw)
To: Hangxiang Ma
Cc: Robert Foss, Todor Tomov, Bryan O'Donoghue,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Loic Poulain, Vinod Koul, Neil Armstrong, linux-media,
linux-arm-msm, devicetree, linux-kernel, linux-phy,
jeyaprakash.soundrapandian, Vijay Kumar Tumati
On Tue, Jul 21, 2026 at 05:46:00AM -0700, Hangxiang Ma wrote:
> The SM8750 camera subsystem exposes six CSI2 D-PHY blocks that follow the
> same programming model as Kaanapali. Describe the SM8750 CSI2 PHY using a
No, SM8750 does not have the same programming model as Kaanapali. When
SM8750 was created, there was no Kaanapali, so how it could have the
same interface?
> "qcom,sm8750-csi2-phy" compatible with the "qcom,kaanapali-csi2-phy"
> fallback, so the CAMSS binding can instantiate the CSIPHY nodes as
> separate phy devices.
Redundant sentence.
>
> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
> ---
> .../devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml | 10 +++++++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
> index 7943049834f9..95375efb2597 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
I just commented on very similar patch. This is confusing, there is no
such file and I do not get why you keep adding some long chain of
patches touching the same lines. Squash patches.
This is untestable.
> @@ -16,9 +16,13 @@ description:
>
> properties:
> compatible:
> - enum:
> - - qcom,kaanapali-csi2-phy
> - - qcom,x1e80100-csi2-phy
> + oneOf:
> + - enum:
> + - qcom,kaanapali-csi2-phy
> + - qcom,x1e80100-csi2-phy
> + - items:
> + - const: qcom,sm8750-csi2-phy
> + - const: qcom,kaanapali-csi2-phy
SM8750 came one year before Kaanapali, so how such compatibility is possible?
Best regards,
Krzysztof
--
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https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v6 1/7] dt-bindings: phy: qcom,x1e80100-csi2-phy: Add SM8750 CSI2 PHY
2026-07-22 6:57 ` Krzysztof Kozlowski
@ 2026-07-22 8:19 ` Hangxiang Ma
0 siblings, 0 replies; 15+ messages in thread
From: Hangxiang Ma @ 2026-07-22 8:19 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Robert Foss, Todor Tomov, Bryan O'Donoghue,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Loic Poulain, Vinod Koul, Neil Armstrong, linux-media,
linux-arm-msm, devicetree, linux-kernel, linux-phy,
jeyaprakash.soundrapandian, Vijay Kumar Tumati
On 7/22/2026 2:57 PM, Krzysztof Kozlowski wrote:
> On Tue, Jul 21, 2026 at 05:46:00AM -0700, Hangxiang Ma wrote:
>> The SM8750 camera subsystem exposes six CSI2 D-PHY blocks that follow the
>> same programming model as Kaanapali. Describe the SM8750 CSI2 PHY using a
>
> No, SM8750 does not have the same programming model as Kaanapali. When
> SM8750 was created, there was no Kaanapali, so how it could have the
> same interface?
Will optimize the description for that. This description is not accurate
and cause ambiguity.
>> "qcom,sm8750-csi2-phy" compatible with the "qcom,kaanapali-csi2-phy"
>> fallback, so the CAMSS binding can instantiate the CSIPHY nodes as
>> separate phy devices.
>
> Redundant sentence.
ACK>>
>> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
>> ---
>> .../devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml | 10 +++++++---
>> 1 file changed, 7 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
>> index 7943049834f9..95375efb2597 100644
>> --- a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
>> +++ b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
>
> I just commented on very similar patch. This is confusing, there is no
> such file and I do not get why you keep adding some long chain of
> patches touching the same lines. Squash patches.
>
> This is untestable.
>
>> @@ -16,9 +16,13 @@ description:
>>
>> properties:
>> compatible:
>> - enum:
>> - - qcom,kaanapali-csi2-phy
>> - - qcom,x1e80100-csi2-phy
>> + oneOf:
>> + - enum:
>> + - qcom,kaanapali-csi2-phy
>> + - qcom,x1e80100-csi2-phy
>> + - items:
>> + - const: qcom,sm8750-csi2-phy
>> + - const: qcom,kaanapali-csi2-phy
>
> SM8750 came one year before Kaanapali, so how such compatibility is possible?
>
> Best regards,
> Krzysztof
>
I acknowledge the truth that SM8750 is older than Kaanapali. I handle
the compatible like this because the Kaanapali series was developed and
posted earlier than SM8750.
I agree with you that handling compatible string in this way may raise
unnecessary ambiguity of the relationship between these two series. I
think it's better to treat them as separate ones and add additional
compatible string standalone.
Could you please confirm whether the following format is acceptable or not?
properties:
compatible:
enum:
- qcom,kaanapali-csi2-phy
- qcom,sm8750-csi2-phy
- qcom,x1e80100-csi2-phy
Best regards,
Hangxiang
--
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^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v6 2/7] media: dt-bindings: Add CAMSS device for SM8750
2026-07-21 12:45 [PATCH v6 0/7] media: qcom: camss: Add SM8750 support Hangxiang Ma
2026-07-21 12:46 ` [PATCH v6 1/7] dt-bindings: phy: qcom,x1e80100-csi2-phy: Add SM8750 CSI2 PHY Hangxiang Ma
@ 2026-07-21 12:46 ` Hangxiang Ma
2026-07-22 7:00 ` Krzysztof Kozlowski
2026-07-21 12:46 ` [PATCH v6 3/7] media: qcom: camss: Add SM8750 compatible camss driver Hangxiang Ma
` (5 subsequent siblings)
7 siblings, 1 reply; 15+ messages in thread
From: Hangxiang Ma @ 2026-07-21 12:46 UTC (permalink / raw)
To: Robert Foss, Todor Tomov, Bryan O'Donoghue,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Loic Poulain, Vinod Koul, Neil Armstrong
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, linux-phy,
jeyaprakash.soundrapandian, Vijay Kumar Tumati, Hangxiang Ma,
Krzysztof Kozlowski
Add bindings for Camera Subsystem (CAMSS) on the Qualcomm SM8750 platform.
The SM8750 platform provides:
- 6 x CSIPHY (CSI Physical Layer)
- 3 x TPG (Test Pattern Generator)
- 3 x CSID (CSI Decoder)
- 2 x CSID Lite
- 3 x VFE (Video Front End), 5 RDI per VFE
- 2 x VFE Lite, 4 RDI per VFE Lite
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
---
.../bindings/media/qcom,sm8750-camss.yaml | 427 +++++++++++++++++++++
1 file changed, 427 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml
new file mode 100644
index 000000000000..fca288d2b82a
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml
@@ -0,0 +1,427 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,sm8750-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8750 Camera Subsystem (CAMSS)
+
+maintainers:
+ - Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
+
+description:
+ The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
+
+properties:
+ compatible:
+ const: qcom,sm8750-camss
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 2
+
+ ranges: true
+
+ reg:
+ maxItems: 13
+
+ reg-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid_lite0
+ - const: csid_lite1
+ - const: csitpg0
+ - const: csitpg1
+ - const: csitpg2
+ - const: vfe0
+ - const: vfe1
+ - const: vfe2
+ - const: vfe_lite0
+ - const: vfe_lite1
+
+ clocks:
+ maxItems: 23
+
+ clock-names:
+ items:
+ - const: camnoc_nrt_axi
+ - const: camnoc_rt_axi
+ - const: cpas_ahb
+ - const: cpas_fast_ahb
+ - const: cpas_vfe0
+ - const: cpas_vfe1
+ - const: cpas_vfe2
+ - const: cpas_vfe_lite
+ - const: csid
+ - const: csid_csiphy_rx
+ - const: gcc_axi_hf
+ - const: gcc_axi_sf
+ - const: vfe0
+ - const: vfe0_fast_ahb
+ - const: vfe1
+ - const: vfe1_fast_ahb
+ - const: vfe2
+ - const: vfe2_fast_ahb
+ - const: vfe_lite
+ - const: vfe_lite_ahb
+ - const: vfe_lite_cphy_rx
+ - const: vfe_lite_csid
+ - const: qdss_debug_xo
+
+ interrupts:
+ maxItems: 10
+
+ interrupt-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid_lite0
+ - const: csid_lite1
+ - const: vfe0
+ - const: vfe1
+ - const: vfe2
+ - const: vfe_lite0
+ - const: vfe_lite1
+
+ phys:
+ maxItems: 6
+ description: CSIPHY 0-5 PHYs used by the CSID controllers.
+
+ phy-names:
+ items:
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: csiphy3
+ - const: csiphy4
+ - const: csiphy5
+
+ interconnects:
+ maxItems: 4
+
+ interconnect-names:
+ items:
+ - const: ahb
+ - const: hf_mnoc
+ - const: sf_mnoc
+ - const: sf_icp_mnoc
+
+ iommus:
+ maxItems: 1
+
+ power-domains:
+ items:
+ - description:
+ IFE0 GDSC - Global Distributed Switch Controller for IFE0.
+ - description:
+ IFE1 GDSC - Global Distributed Switch Controller for IFE1.
+ - description:
+ IFE2 GDSC - Global Distributed Switch Controller for IFE2.
+ - description:
+ Titan GDSC - Global Distributed Switch Controller for the entire camss.
+
+ power-domain-names:
+ items:
+ - const: ife0
+ - const: ife1
+ - const: ife2
+ - const: top
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ description:
+ CSI input ports, one per CSID. Each port receives the CSI data
+ decoded by the matching CSIPHY.
+
+ patternProperties:
+ "^port@[0-5]$":
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data from CSIPHY 0-5.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ bus-type:
+ enum:
+ - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
+ - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
+
+ required:
+ - data-lanes
+
+patternProperties:
+ "^phy@[0-9a-f]+$":
+ $ref: /schemas/phy/qcom,x1e80100-csi2-phy.yaml#
+ unevaluatedProperties: false
+ description:
+ CSIPHY blocks decoding the incoming MIPI CSI2 sensor streams.
+
+ "^opp-table(-.*)?$":
+ type: object
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+ - interconnects
+ - interconnect-names
+ - iommus
+ - power-domains
+ - power-domain-names
+ - phys
+ - phy-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,sm8750-gcc.h>
+ #include <dt-bindings/clock/qcom,sm8750-camcc.h>
+ #include <dt-bindings/interconnect/qcom,icc.h>
+ #include <dt-bindings/interconnect/qcom,sm8750-rpmh.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/phy/phy.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ isp@ad27000 {
+ compatible = "qcom,sm8750-camss";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ reg = <0x0 0x0ad27000 0x0 0x2b00>,
+ <0x0 0x0ad2a000 0x0 0x2b00>,
+ <0x0 0x0ad2d000 0x0 0x2b00>,
+ <0x0 0x0ad6d000 0x0 0xa00>,
+ <0x0 0x0ad72000 0x0 0xa00>,
+ <0x0 0x0ad8b000 0x0 0x400>,
+ <0x0 0x0ad8c000 0x0 0x400>,
+ <0x0 0x0ad8d000 0x0 0x400>,
+ <0x0 0x0ac86000 0x0 0x10000>,
+ <0x0 0x0ac96000 0x0 0x10000>,
+ <0x0 0x0aca6000 0x0 0x10000>,
+ <0x0 0x0ad6e000 0x0 0x3000>,
+ <0x0 0x0ad73000 0x0 0x3000>;
+ reg-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csitpg0",
+ "csitpg1",
+ "csitpg2",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ clocks = <&camcc CAM_CC_CAMNOC_NRT_AXI_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>,
+ <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
+ <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>,
+ <&camcc CAM_CC_CSID_CLK>,
+ <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&gcc GCC_CAMERA_SF_AXI_CLK>,
+ <&camcc CAM_CC_TFE_0_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_0_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TFE_1_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_1_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TFE_2_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_2_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>,
+ <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>;
+ clock-names = "camnoc_nrt_axi",
+ "camnoc_rt_axi",
+ "cpas_ahb",
+ "cpas_fast_ahb",
+ "cpas_vfe0",
+ "cpas_vfe1",
+ "cpas_vfe2",
+ "cpas_vfe_lite",
+ "csid",
+ "csid_csiphy_rx",
+ "gcc_axi_hf",
+ "gcc_axi_sf",
+ "vfe0",
+ "vfe0_fast_ahb",
+ "vfe1",
+ "vfe1_fast_ahb",
+ "vfe2",
+ "vfe2_fast_ahb",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid",
+ "qdss_debug_xo";
+
+ interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 457 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_CAMNOC_NRT_ICP_SF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ahb",
+ "hf_mnoc",
+ "sf_mnoc",
+ "sf_icp_mnoc";
+
+ iommus = <&apps_smmu 0x1c00 0x00>;
+
+ power-domains = <&camcc CAM_CC_TFE_0_GDSC>,
+ <&camcc CAM_CC_TFE_1_GDSC>,
+ <&camcc CAM_CC_TFE_2_GDSC>,
+ <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ power-domain-names = "ife0",
+ "ife1",
+ "ife2",
+ "top";
+
+ phys = <&csiphy0 PHY_TYPE_DPHY>,
+ <&csiphy1 PHY_TYPE_DPHY>,
+ <&csiphy2 PHY_TYPE_DPHY>,
+ <&csiphy3 PHY_TYPE_DPHY>,
+ <&csiphy4 PHY_TYPE_DPHY>,
+ <&csiphy5 PHY_TYPE_DPHY>;
+ phy-names = "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "csiphy4",
+ "csiphy5";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ camss_csiphy0_inep0: endpoint@0 {
+ reg = <0>;
+ data-lanes = <0 1 2 3>;
+ remote-endpoint = <&csiphy0_out>;
+ };
+ };
+ };
+
+ csiphy0: phy@ada9000 {
+ compatible = "qcom,sm8750-csi2-phy",
+ "qcom,kaanapali-csi2-phy";
+ reg = <0x0 0x0ada9000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>;
+
+ operating-points-v2 = <&csiphy_mxc_opp_table>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ vdda-0p9-supply = <&vreg_0p9_supply>;
+ vdda-1p2-supply = <&vreg_1p2_supply>;
+
+ #phy-cells = <1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csiphy0_in: endpoint {
+ data-lanes = <0 1 2 3>;
+ clock-lanes = <7>;
+ remote-endpoint = <&sensor_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ csiphy0_out: endpoint {
+ remote-endpoint = <&camss_csiphy0_inep0>;
+ };
+ };
+ };
+
+ csiphy_mxc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_low_svs_d1>,
+ <&rpmhpd_opp_low_svs_d1>;
+ };
+ };
+ };
+ };
+ };
--
2.34.1
--
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^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v6 2/7] media: dt-bindings: Add CAMSS device for SM8750
2026-07-21 12:46 ` [PATCH v6 2/7] media: dt-bindings: Add CAMSS device for SM8750 Hangxiang Ma
@ 2026-07-22 7:00 ` Krzysztof Kozlowski
2026-07-22 7:14 ` hangxiang.ma
0 siblings, 1 reply; 15+ messages in thread
From: Krzysztof Kozlowski @ 2026-07-22 7:00 UTC (permalink / raw)
To: Hangxiang Ma
Cc: Robert Foss, Todor Tomov, Bryan O'Donoghue,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Loic Poulain, Vinod Koul, Neil Armstrong, linux-media,
linux-arm-msm, devicetree, linux-kernel, linux-phy,
jeyaprakash.soundrapandian, Vijay Kumar Tumati,
Krzysztof Kozlowski
On Tue, Jul 21, 2026 at 05:46:01AM -0700, Hangxiang Ma wrote:
> Add bindings for Camera Subsystem (CAMSS) on the Qualcomm SM8750 platform.
>
> The SM8750 platform provides:
> - 6 x CSIPHY (CSI Physical Layer)
> - 3 x TPG (Test Pattern Generator)
> - 3 x CSID (CSI Decoder)
> - 2 x CSID Lite
> - 3 x VFE (Video Front End), 5 RDI per VFE
> - 2 x VFE Lite, 4 RDI per VFE Lite
>
> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Drop both tags.
Binding was very different.
Best regards,
Krzysztof
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v6 2/7] media: dt-bindings: Add CAMSS device for SM8750
2026-07-22 7:00 ` Krzysztof Kozlowski
@ 2026-07-22 7:14 ` hangxiang.ma
0 siblings, 0 replies; 15+ messages in thread
From: hangxiang.ma @ 2026-07-22 7:14 UTC (permalink / raw)
To: Krzysztof Kozlowski, Robert Foss, Todor Tomov,
Bryan O'Donoghue, Vladimir Zapolskiy, Mauro Carvalho Chehab,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bryan O'Donoghue, Loic Poulain, Vinod Koul, Neil Armstrong,
linux-media, linux-arm-msm, devicetree, linux-kernel, linux-phy,
jeyaprakash.soundrapandian, Vijay Kumar Tumati,
Krzysztof Kozlowski
On 7/22/26 3:00 PM, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> On Tue, Jul 21, 2026 at 05:46:01AM -0700, Hangxiang Ma wrote:
> > Add bindings for Camera Subsystem (CAMSS) on the Qualcomm SM8750 platform.
> >
> > The SM8750 platform provides:
> > - 6 x CSIPHY (CSI Physical Layer)
> > - 3 x TPG (Test Pattern Generator)
> > - 3 x CSID (CSI Decoder)
> > - 2 x CSID Lite
> > - 3 x VFE (Video Front End), 5 RDI per VFE
> > - 2 x VFE Lite, 4 RDI per VFE Lite
> >
> > Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
>
> Drop both tags.
>
> Binding was very different.
>
> Best regards,
> Krzysztof
>
>
Ack
Best regards,
Hangxiang
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^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v6 3/7] media: qcom: camss: Add SM8750 compatible camss driver
2026-07-21 12:45 [PATCH v6 0/7] media: qcom: camss: Add SM8750 support Hangxiang Ma
2026-07-21 12:46 ` [PATCH v6 1/7] dt-bindings: phy: qcom,x1e80100-csi2-phy: Add SM8750 CSI2 PHY Hangxiang Ma
2026-07-21 12:46 ` [PATCH v6 2/7] media: dt-bindings: Add CAMSS device for SM8750 Hangxiang Ma
@ 2026-07-21 12:46 ` Hangxiang Ma
2026-07-21 12:46 ` [PATCH v6 4/7] media: qcom: camss: csiphy: Add support for v2.3.0 two-phase CSIPHY Hangxiang Ma
` (4 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Hangxiang Ma @ 2026-07-21 12:46 UTC (permalink / raw)
To: Robert Foss, Todor Tomov, Bryan O'Donoghue,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Loic Poulain, Vinod Koul, Neil Armstrong
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, linux-phy,
jeyaprakash.soundrapandian, Vijay Kumar Tumati, Hangxiang Ma
Add support for SM8750 in the camss driver. Add high level resource
information along with the bus bandwidth votes. Module level detailed
resource information will be enumerated in the following patches of the
series.
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
---
drivers/media/platform/qcom/camss/camss.c | 22 ++++++++++++++++++++++
drivers/media/platform/qcom/camss/camss.h | 1 +
2 files changed, 23 insertions(+)
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 252dc2fe4207..9982174ed1ad 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -4477,6 +4477,20 @@ static const struct resources_icc icc_res_sa8775p[] = {
},
};
+static const struct resources_icc icc_res_sm8750[] = {
+ {
+ .name = "ahb",
+ .icc_bw_tbl.avg = 150000,
+ .icc_bw_tbl.peak = 300000,
+ },
+ /* Based on 4096 x 3072 30 FPS 2496 Mbps mode */
+ {
+ .name = "hf_mnoc",
+ .icc_bw_tbl.avg = 471860,
+ .icc_bw_tbl.peak = 925857,
+ },
+};
+
static const struct camss_subdev_resources csiphy_res_x1e80100[] = {
/* CSIPHY0 */
{
@@ -6068,6 +6082,13 @@ static const struct camss_resources sm8650_resources = {
.vfe_num = ARRAY_SIZE(vfe_res_sm8650),
};
+static const struct camss_resources sm8750_resources = {
+ .version = CAMSS_8750,
+ .pd_name = "top",
+ .icc_res = icc_res_sm8750,
+ .icc_path_num = ARRAY_SIZE(icc_res_sm8750),
+};
+
static const struct camss_resources x1e80100_resources = {
.version = CAMSS_X1E80100,
.pd_name = "top",
@@ -6103,6 +6124,7 @@ static const struct of_device_id camss_dt_match[] = {
{ .compatible = "qcom,sm8250-camss", .data = &sm8250_resources },
{ .compatible = "qcom,sm8550-camss", .data = &sm8550_resources },
{ .compatible = "qcom,sm8650-camss", .data = &sm8650_resources },
+ { .compatible = "qcom,sm8750-camss", .data = &sm8750_resources },
{ .compatible = "qcom,x1e80100-camss", .data = &x1e80100_resources },
{ }
};
diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
index cea213dc36eb..7f525ac37cbb 100644
--- a/drivers/media/platform/qcom/camss/camss.h
+++ b/drivers/media/platform/qcom/camss/camss.h
@@ -95,6 +95,7 @@ enum camss_version {
CAMSS_845,
CAMSS_8550,
CAMSS_8650,
+ CAMSS_8750,
CAMSS_8775P,
CAMSS_KAANAPALI,
CAMSS_X1E80100,
--
2.34.1
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^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v6 4/7] media: qcom: camss: csiphy: Add support for v2.3.0 two-phase CSIPHY
2026-07-21 12:45 [PATCH v6 0/7] media: qcom: camss: Add SM8750 support Hangxiang Ma
` (2 preceding siblings ...)
2026-07-21 12:46 ` [PATCH v6 3/7] media: qcom: camss: Add SM8750 compatible camss driver Hangxiang Ma
@ 2026-07-21 12:46 ` Hangxiang Ma
2026-07-21 12:46 ` [PATCH v6 5/7] media: qcom: camss: csid: Add support for CSID 980 Hangxiang Ma
` (3 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Hangxiang Ma @ 2026-07-21 12:46 UTC (permalink / raw)
To: Robert Foss, Todor Tomov, Bryan O'Donoghue,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Loic Poulain, Vinod Koul, Neil Armstrong
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, linux-phy,
jeyaprakash.soundrapandian, Vijay Kumar Tumati, Hangxiang Ma
Add more detailed resource information for CSIPHY devices in the camss
driver along with the support for v2.3.0 in the 2 phase CSIPHY driver
that is responsible for the PHY lane register configuration, module
reset and interrupt handling.
Reviewed-by: Bryan O'Donoghue <bod@kernel.org>
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
---
drivers/media/platform/qcom/camss/camss.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 9982174ed1ad..1ab1a0cd82d2 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -6085,7 +6085,9 @@ static const struct camss_resources sm8650_resources = {
static const struct camss_resources sm8750_resources = {
.version = CAMSS_8750,
.pd_name = "top",
+ .csiphy_res = csiphy_res_kaanapali,
.icc_res = icc_res_sm8750,
+ .csiphy_num = ARRAY_SIZE(csiphy_res_kaanapali),
.icc_path_num = ARRAY_SIZE(icc_res_sm8750),
};
--
2.34.1
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^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v6 5/7] media: qcom: camss: csid: Add support for CSID 980
2026-07-21 12:45 [PATCH v6 0/7] media: qcom: camss: Add SM8750 support Hangxiang Ma
` (3 preceding siblings ...)
2026-07-21 12:46 ` [PATCH v6 4/7] media: qcom: camss: csiphy: Add support for v2.3.0 two-phase CSIPHY Hangxiang Ma
@ 2026-07-21 12:46 ` Hangxiang Ma
2026-07-21 12:46 ` [PATCH v6 6/7] media: qcom: camss: vfe: Add support for VFE 980 Hangxiang Ma
` (2 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Hangxiang Ma @ 2026-07-21 12:46 UTC (permalink / raw)
To: Robert Foss, Todor Tomov, Bryan O'Donoghue,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Loic Poulain, Vinod Koul, Neil Armstrong
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, linux-phy,
jeyaprakash.soundrapandian, Vijay Kumar Tumati, Hangxiang Ma,
Atiya Kailany
Add more detailed resource information for CSID devices along with the
driver for CSID 980 that is responsible for CSID register
configuration, module reset and IRQ handling for BUF_DONE events.
In SM8750, RUP and AUP updates for the CSID Full modules are split into
two registers along with a SET register. However, CSID Lite modules
still use a single register to update RUP and AUP without the additional
SET register. Handled such differences in the driver.
Co-developed-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
Signed-off-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
---
drivers/media/platform/qcom/camss/Makefile | 1 +
drivers/media/platform/qcom/camss/camss-csid-980.c | 443 +++++++++++++++++++++
drivers/media/platform/qcom/camss/camss-csid.h | 1 +
drivers/media/platform/qcom/camss/camss.c | 75 ++++
4 files changed, 520 insertions(+)
diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile
index b114ca37e36e..c19d3183882a 100644
--- a/drivers/media/platform/qcom/camss/Makefile
+++ b/drivers/media/platform/qcom/camss/Makefile
@@ -8,6 +8,7 @@ qcom-camss-objs += \
camss-csid-4-7.o \
camss-csid-340.o \
camss-csid-680.o \
+ camss-csid-980.o \
camss-csid-gen2.o \
camss-csid-gen3.o \
camss-csid-gen4.o \
diff --git a/drivers/media/platform/qcom/camss/camss-csid-980.c b/drivers/media/platform/qcom/camss/camss-csid-980.c
new file mode 100644
index 000000000000..6714b8aa8c2a
--- /dev/null
+++ b/drivers/media/platform/qcom/camss/camss-csid-980.c
@@ -0,0 +1,443 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * camss-csid-980.c
+ *
+ * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module
+ *
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include "camss.h"
+#include "camss-csid.h"
+#include "camss-csid-gen3.h"
+
+/* Reset and Command Registers */
+#define CSID_RST_CFG 0xC
+#define RST_MODE BIT(0)
+#define RST_LOCATION BIT(4)
+
+/* Reset and Command Registers */
+#define CSID_RST_CMD 0x10
+#define SELECT_HW_RST BIT(0)
+#define SELECT_IRQ_RST BIT(2)
+#define CSID_IRQ_CMD 0x14
+#define IRQ_CMD_CLEAR BIT(0)
+
+/* Register Update Commands, RUP/AUP */
+#define CSID_RUP_CMD 0x18
+#define CSID_AUP_CMD 0x1C
+#define CSID_RUP_AUP_RDI(rdi) (BIT(8) << (rdi))
+#define CSID_RUP_AUP_CMD 0x20
+#define RUP_SET BIT(0)
+#define MUP BIT(4)
+
+#define CSID_LITE_RUP_AUP_CMD 0x18
+#define CSID_LITE_RUP_RDI(rdi) (BIT(4) << (rdi))
+#define CSID_LITE_AUP_RDI(rdi) (BIT(20) << (rdi))
+
+/* Top level interrupt registers */
+#define CSID_TOP_IRQ_STATUS (csid_is_lite(csid) ? 0x7C : 0x84)
+#define CSID_TOP_IRQ_MASK (csid_is_lite(csid) ? 0x80 : 0x88)
+#define CSID_TOP_IRQ_CLEAR (csid_is_lite(csid) ? 0x84 : 0x8C)
+#define CSID_TOP_IRQ_SET (csid_is_lite(csid) ? 0x88 : 0x90)
+#define INFO_RST_DONE BIT(0)
+#define CSI2_RX_IRQ_STATUS BIT(2)
+#define BUF_DONE_IRQ_STATUS BIT(csid_is_lite(csid) ? 13 : 3)
+
+/* Buffer done interrupt registers */
+#define CSID_BUF_DONE_IRQ_STATUS (csid_is_lite(csid) ? 0x8C : 0xA4)
+#define BUF_DONE_IRQ_STATUS_RDI_OFFSET (csid_is_lite(csid) ? 1 : 16)
+#define CSID_BUF_DONE_IRQ_MASK (csid_is_lite(csid) ? 0x90 : 0xA8)
+#define CSID_BUF_DONE_IRQ_CLEAR (csid_is_lite(csid) ? 0x94 : 0xAC)
+#define CSID_BUF_DONE_IRQ_SET (csid_is_lite(csid) ? 0x98 : 0xB0)
+
+/* CSI2 RX interrupt registers */
+#define CSID_CSI2_RX_IRQ_STATUS (csid_is_lite(csid) ? 0x9C : 0xB4)
+#define CSID_CSI2_RX_IRQ_MASK (csid_is_lite(csid) ? 0xA0 : 0xB8)
+#define CSID_CSI2_RX_IRQ_CLEAR (csid_is_lite(csid) ? 0xA4 : 0xBC)
+#define CSID_CSI2_RX_IRQ_SET (csid_is_lite(csid) ? 0xA8 : 0xC0)
+
+/* CSI2 RX Configuration */
+#define CSID_CSI2_RX_CFG0 (csid_is_lite(csid) ? 0x200 : 0x400)
+#define CSI2_RX_CFG0_NUM_ACTIVE_LANES 0
+#define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1
+#define CSI2_RX_CFG0_DL0_INPUT_SEL 4
+#define CSI2_RX_CFG0_PHY_NUM_SEL 20
+#define CSID_CSI2_RX_CFG1 (csid_is_lite(csid) ? 0x204 : 0x404)
+#define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0)
+#define CSI2_RX_CFG1_VC_MODE BIT(2)
+
+#define MSM_CSID_MAX_SRC_STREAMS_980 (csid_is_lite(csid) ? 4 : 5)
+
+#define CSID_RDI_CFG0(rdi) \
+ ({ \
+ __typeof__(rdi) _rdi = (rdi); \
+ csid_is_lite(csid) ? 0x500 + 0x100 * _rdi : \
+ 0xE00 + 0x200 * _rdi; \
+ })
+#define RDI_CFG0_RETIME_BS BIT(5)
+#define RDI_CFG0_TIMESTAMP_EN BIT(6)
+#define RDI_CFG0_TIMESTAMP_STB_SEL BIT(8)
+#define RDI_CFG0_DECODE_FORMAT 12
+#define RDI_CFG0_DT 16
+#define RDI_CFG0_VC 22
+#define RDI_CFG0_DT_ID 27
+#define RDI_CFG0_EN BIT(31)
+
+/* RDI Control and Configuration */
+#define CSID_RDI_CTRL(rdi) \
+ ({ \
+ __typeof__(rdi) _rdi = (rdi); \
+ csid_is_lite(csid) ? 0x504 + 0x100 * _rdi : \
+ 0xE04 + 0x200 * _rdi; \
+ })
+#define RDI_CTRL_START_CMD BIT(0)
+
+#define CSID_RDI_CFG1(rdi) \
+ ({ \
+ __typeof__(rdi) _rdi = (rdi); \
+ csid_is_lite(csid) ? 0x510 + 0x100 * _rdi : \
+ 0xE10 + 0x200 * _rdi; \
+ })
+#define RDI_CFG1_DROP_H_EN BIT(5)
+#define RDI_CFG1_DROP_V_EN BIT(6)
+#define RDI_CFG1_CROP_H_EN BIT(7)
+#define RDI_CFG1_CROP_V_EN BIT(8)
+#define RDI_CFG1_PACKING_FORMAT_MIPI BIT(15)
+
+/* RDI Pixel Store Configuration */
+#define CSID_RDI_PIX_STORE_CFG0(rdi) (0xE14 + 0x200 * (rdi))
+#define RDI_PIX_STORE_CFG0_EN BIT(0)
+#define RDI_PIX_STORE_CFG0_MIN_HBI 1
+
+/* RDI IRQ Status in wrapper */
+#define CSID_CSI2_RDIN_IRQ_STATUS(rdi) \
+ (csid_is_lite(csid) ? 0xEC : 0x114 + 0x10 * (rdi))
+#define CSID_CSI2_RDIN_IRQ_CLEAR(rdi) \
+ (csid_is_lite(csid) ? 0xF4 : 0x11C + 0x10 * (rdi))
+#define INFO_RUP_DONE BIT(23)
+
+static void __csid_full_aup_rup_trigger(struct csid_device *csid)
+{
+ /* trigger SET in combined register */
+ writel(RUP_SET, csid->base + CSID_RUP_AUP_CMD);
+}
+
+static void __csid_aup_update(struct csid_device *csid, int port_id)
+{
+ if (csid_is_lite(csid)) {
+ /* CSID Lites in v980 follow the legacy way of a combined RUP
+ * and AUP commands without an explicit SET register.
+ */
+ csid->reg_update |= CSID_LITE_AUP_RDI(port_id);
+ writel(csid->reg_update, csid->base + CSID_LITE_RUP_AUP_CMD);
+ } else {
+ csid->aup_update |= CSID_RUP_AUP_RDI(port_id);
+ writel(csid->aup_update, csid->base + CSID_AUP_CMD);
+
+ /* CSID Fulls in v980 split AUP and RUP commands, which requires
+ * additional SET operation to make registers modification take
+ * effect.
+ */
+ __csid_full_aup_rup_trigger(csid);
+ }
+}
+
+static void __csid_rup_update(struct csid_device *csid, int port_id)
+{
+ if (csid_is_lite(csid)) {
+ /* CSID Lites in v980 follow the legacy way of a combined RUP
+ * and AUP commands without an explicit SET register.
+ */
+ csid->reg_update |= CSID_LITE_RUP_RDI(port_id);
+ writel(csid->reg_update, csid->base + CSID_LITE_RUP_AUP_CMD);
+ } else {
+ csid->rup_update |= CSID_RUP_AUP_RDI(port_id);
+ writel(csid->rup_update, csid->base + CSID_RUP_CMD);
+
+ /* CSID Fulls in v980 split AUP and RUP commands, which requires
+ * additional SET operation to make registers modification take
+ * effect.
+ */
+ __csid_full_aup_rup_trigger(csid);
+ }
+}
+
+static void __csid_aup_rup_clear(struct csid_device *csid, int port_id)
+{
+ /* Hardware clears the registers upon consuming the settings */
+ if (csid_is_lite(csid)) {
+ csid->reg_update &= ~CSID_LITE_RUP_RDI(port_id);
+ csid->reg_update &= ~CSID_LITE_AUP_RDI(port_id);
+ } else {
+ csid->aup_update &= ~CSID_RUP_AUP_RDI(port_id);
+ csid->rup_update &= ~CSID_RUP_AUP_RDI(port_id);
+ }
+}
+
+static void __csid_configure_rx(struct csid_device *csid,
+ struct csid_phy_config *phy)
+{
+ int val;
+
+ val = (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES;
+ val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL;
+ val |= (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX)
+ << CSI2_RX_CFG0_PHY_NUM_SEL;
+ writel(val, csid->base + CSID_CSI2_RX_CFG0);
+
+ val = CSI2_RX_CFG1_ECC_CORRECTION_EN;
+ writel(val, csid->base + CSID_CSI2_RX_CFG1);
+}
+
+static void __csid_configure_rx_vc(struct csid_device *csid, int vc)
+{
+ int val;
+
+ if (vc > 3) {
+ val = readl(csid->base + CSID_CSI2_RX_CFG1);
+ val |= CSI2_RX_CFG1_VC_MODE;
+ writel(val, csid->base + CSID_CSI2_RX_CFG1);
+ }
+}
+
+static void __csid_ctrl_rdi(struct csid_device *csid, int enable, u8 rdi)
+{
+ u32 rdi_ctrl_offset = CSID_RDI_CTRL(rdi);
+ int val = 0;
+
+ if (enable)
+ val = RDI_CTRL_START_CMD;
+
+ writel(val, csid->base + rdi_ctrl_offset);
+}
+
+static void __csid_configure_rdi_pix_store(struct csid_device *csid, u8 rdi)
+{
+ u32 val;
+
+ /*
+ * Configure pixel store to allow absorption of hblanking or idle time.
+ * This helps with horizontal crop and prevents line buffer conflicts.
+ * Reset state is 0x8 which has MIN_HBI=4, we keep the default MIN_HBI
+ * and just enable the pixel store functionality.
+ */
+ val = (4 << RDI_PIX_STORE_CFG0_MIN_HBI) | RDI_PIX_STORE_CFG0_EN;
+ writel(val, csid->base + CSID_RDI_PIX_STORE_CFG0(rdi));
+}
+
+static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 port, u8 vc)
+{
+ u8 lane_cnt = csid->phy.lane_cnt;
+ u32 val;
+
+ /* Source pads matching RDI channels on hardware.
+ * E.g. Pad 1 -> RDI0, Pad 2 -> RDI1, etc.
+ */
+ struct v4l2_mbus_framefmt *input_format = &csid->fmt[MSM_CSID_PAD_FIRST_SRC + port];
+ const struct csid_format_info *format = csid_get_fmt_entry(csid->res->formats->formats,
+ csid->res->formats->nformats,
+ input_format->code);
+
+ if (!lane_cnt)
+ lane_cnt = 4;
+
+ /*
+ * DT_ID is a two bit bitfield that is concatenated with
+ * the four least significant bits of the five bit VC
+ * bitfield to generate an internal CID value.
+ *
+ * CSID_RDI_CFG0(vc)
+ * DT_ID : 28:27
+ * VC : 26:22
+ * DT : 21:16
+ *
+ * CID : VC 3:0 << 2 | DT_ID 1:0
+ */
+ u8 dt_id = vc & 0x03;
+ u32 rdi_cfg0_offset = CSID_RDI_CFG0(port);
+ u32 rdi_cfg1_offset = CSID_RDI_CFG1(port);
+ u32 rdi_ctrl_offset = CSID_RDI_CTRL(port);
+
+ val = RDI_CFG0_TIMESTAMP_EN;
+ val |= RDI_CFG0_TIMESTAMP_STB_SEL;
+ val |= RDI_CFG0_RETIME_BS;
+
+ /* note: for non-RDI path, this should be format->decode_format */
+ val |= DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT;
+ val |= vc << RDI_CFG0_VC;
+ val |= format->data_type << RDI_CFG0_DT;
+ val |= dt_id << RDI_CFG0_DT_ID;
+ writel(val, csid->base + rdi_cfg0_offset);
+
+ val = RDI_CFG1_PACKING_FORMAT_MIPI;
+ writel(val, csid->base + rdi_cfg1_offset);
+
+ /* Configure pixel store using dedicated register in 980 */
+ if (!csid_is_lite(csid))
+ __csid_configure_rdi_pix_store(csid, port);
+
+ val = 0;
+ writel(val, csid->base + rdi_ctrl_offset);
+
+ val = readl(csid->base + rdi_cfg0_offset);
+
+ if (enable)
+ val |= RDI_CFG0_EN;
+
+ writel(val, csid->base + rdi_cfg0_offset);
+}
+
+static void csid_configure_stream(struct csid_device *csid, u8 enable)
+{
+ u8 i, k;
+
+ __csid_configure_rx(csid, &csid->phy);
+
+ for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_980; i++) {
+ if (csid->phy.en_vc & BIT(i)) {
+ __csid_configure_rdi_stream(csid, enable, i, 0);
+ __csid_configure_rx_vc(csid, 0);
+
+ for (k = 0; k < CAMSS_INIT_BUF_COUNT; k++) {
+ __csid_aup_update(csid, i);
+ __csid_rup_update(csid, i);
+ }
+
+ __csid_ctrl_rdi(csid, enable, i);
+ }
+ }
+}
+
+static int csid_configure_testgen_pattern(struct csid_device *csid, s32 val)
+{
+ return 0;
+}
+
+static void csid_subdev_reg_update(struct csid_device *csid, int port_id,
+ bool clear)
+{
+ if (clear)
+ __csid_aup_rup_clear(csid, port_id);
+ else
+ __csid_aup_update(csid, port_id);
+}
+
+/**
+ * csid_isr - CSID module interrupt service routine
+ * @irq: Interrupt line
+ * @dev: CSID device
+ *
+ * Return IRQ_HANDLED on success
+ */
+static irqreturn_t csid_isr(int irq, void *dev)
+{
+ struct csid_device *csid = dev;
+ u32 val, buf_done_val;
+ u8 reset_done;
+ int i;
+
+ val = readl(csid->base + CSID_TOP_IRQ_STATUS);
+ writel(val, csid->base + CSID_TOP_IRQ_CLEAR);
+
+ reset_done = val & INFO_RST_DONE;
+
+ buf_done_val = readl(csid->base + CSID_BUF_DONE_IRQ_STATUS);
+ writel(buf_done_val, csid->base + CSID_BUF_DONE_IRQ_CLEAR);
+
+ for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_980; i++) {
+ if (csid->phy.en_vc & BIT(i)) {
+ val = readl(csid->base + CSID_CSI2_RDIN_IRQ_STATUS(i));
+ writel(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(i));
+
+ if (val & INFO_RUP_DONE)
+ csid_subdev_reg_update(csid, i, true);
+
+ if (buf_done_val & BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i))
+ camss_buf_done(csid->camss, csid->id, i);
+ }
+ }
+
+ val = IRQ_CMD_CLEAR;
+ writel(val, csid->base + CSID_IRQ_CMD);
+
+ if (reset_done)
+ complete(&csid->reset_complete);
+
+ return IRQ_HANDLED;
+}
+
+/**
+ * csid_reset - Trigger reset on CSID module and wait to complete
+ * @csid: CSID device
+ *
+ * Return 0 on success or a negative error code otherwise
+ */
+static int csid_reset(struct csid_device *csid)
+{
+ unsigned long time;
+ u32 val;
+ int i;
+
+ reinit_completion(&csid->reset_complete);
+
+ val = INFO_RST_DONE | BUF_DONE_IRQ_STATUS;
+ writel(val, csid->base + CSID_TOP_IRQ_CLEAR);
+ writel(val, csid->base + CSID_TOP_IRQ_MASK);
+
+ val = 0;
+ for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_980; i++) {
+ if (csid->phy.en_vc & BIT(i)) {
+ /*
+ * Only need to clear buf done IRQ status here,
+ * RUP done IRQ status will be cleared once isr
+ * strobe generated by CSID_RST_CMD
+ */
+ val |= BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i);
+ }
+ }
+ writel(val, csid->base + CSID_BUF_DONE_IRQ_CLEAR);
+ writel(val, csid->base + CSID_BUF_DONE_IRQ_MASK);
+
+ /* Clear all IRQ status with CLEAR bits set */
+ val = IRQ_CMD_CLEAR;
+ writel(val, csid->base + CSID_IRQ_CMD);
+
+ val = RST_LOCATION | RST_MODE;
+ writel(val, csid->base + CSID_RST_CFG);
+
+ val = SELECT_HW_RST | SELECT_IRQ_RST;
+ writel(val, csid->base + CSID_RST_CMD);
+
+ time = wait_for_completion_timeout(&csid->reset_complete,
+ msecs_to_jiffies(CSID_RESET_TIMEOUT_MS));
+
+ if (!time) {
+ dev_err(csid->camss->dev, "CSID reset timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static void csid_subdev_init(struct csid_device *csid)
+{
+ csid->testgen.nmodes = CSID_PAYLOAD_MODE_DISABLED;
+}
+
+const struct csid_hw_ops csid_ops_980 = {
+ .configure_stream = csid_configure_stream,
+ .configure_testgen_pattern = csid_configure_testgen_pattern,
+ .hw_version = csid_hw_version,
+ .isr = csid_isr,
+ .reset = csid_reset,
+ .src_pad_code = csid_src_pad_code,
+ .subdev_init = csid_subdev_init,
+ .reg_update = csid_subdev_reg_update,
+};
+
diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media/platform/qcom/camss/camss-csid.h
index 4f31ad303c4e..8edf3548d692 100644
--- a/drivers/media/platform/qcom/camss/camss-csid.h
+++ b/drivers/media/platform/qcom/camss/camss-csid.h
@@ -222,6 +222,7 @@ extern const struct csid_hw_ops csid_ops_4_1;
extern const struct csid_hw_ops csid_ops_4_7;
extern const struct csid_hw_ops csid_ops_340;
extern const struct csid_hw_ops csid_ops_680;
+extern const struct csid_hw_ops csid_ops_980;
extern const struct csid_hw_ops csid_ops_gen2;
extern const struct csid_hw_ops csid_ops_gen3;
extern const struct csid_hw_ops csid_ops_gen4;
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 1ab1a0cd82d2..e0b181ff33aa 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -4477,6 +4477,79 @@ static const struct resources_icc icc_res_sa8775p[] = {
},
};
+static const struct camss_subdev_resources csid_res_sm8750[] = {
+ /* CSID0 */
+ {
+ .clock = { "csid", "csid_csiphy_rx" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000, 480000000 } },
+ .reg = { "csid0" },
+ .interrupt = { "csid0" },
+ .csid = {
+ .is_lite = false,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_980,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID1 */
+ {
+ .clock = { "csid", "csid_csiphy_rx" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000, 480000000 } },
+ .reg = { "csid1" },
+ .interrupt = { "csid1" },
+ .csid = {
+ .is_lite = false,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_980,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID2 */
+ {
+ .clock = { "csid", "csid_csiphy_rx" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000, 480000000 } },
+ .reg = { "csid2" },
+ .interrupt = { "csid2" },
+ .csid = {
+ .is_lite = false,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_980,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID_LITE0 */
+ {
+ .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000, 480000000 } },
+ .reg = { "csid_lite0" },
+ .interrupt = { "csid_lite0" },
+ .csid = {
+ .is_lite = true,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_980,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID_LITE1 */
+ {
+ .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000, 480000000 } },
+ .reg = { "csid_lite1" },
+ .interrupt = { "csid_lite1" },
+ .csid = {
+ .is_lite = true,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_980,
+ .formats = &csid_formats_gen2
+ }
+ }
+};
+
static const struct resources_icc icc_res_sm8750[] = {
{
.name = "ahb",
@@ -6086,8 +6159,10 @@ static const struct camss_resources sm8750_resources = {
.version = CAMSS_8750,
.pd_name = "top",
.csiphy_res = csiphy_res_kaanapali,
+ .csid_res = csid_res_sm8750,
.icc_res = icc_res_sm8750,
.csiphy_num = ARRAY_SIZE(csiphy_res_kaanapali),
+ .csid_num = ARRAY_SIZE(csid_res_sm8750),
.icc_path_num = ARRAY_SIZE(icc_res_sm8750),
};
--
2.34.1
--
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https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v6 6/7] media: qcom: camss: vfe: Add support for VFE 980
2026-07-21 12:45 [PATCH v6 0/7] media: qcom: camss: Add SM8750 support Hangxiang Ma
` (4 preceding siblings ...)
2026-07-21 12:46 ` [PATCH v6 5/7] media: qcom: camss: csid: Add support for CSID 980 Hangxiang Ma
@ 2026-07-21 12:46 ` Hangxiang Ma
2026-07-21 12:46 ` [PATCH v6 7/7] media: qcom: camss: tpg: Add support for v2.3.0 TPG Hangxiang Ma
2026-07-22 7:00 ` [PATCH v6 0/7] media: qcom: camss: Add SM8750 support Krzysztof Kozlowski
7 siblings, 0 replies; 15+ messages in thread
From: Hangxiang Ma @ 2026-07-21 12:46 UTC (permalink / raw)
To: Robert Foss, Todor Tomov, Bryan O'Donoghue,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Loic Poulain, Vinod Koul, Neil Armstrong
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, linux-phy,
jeyaprakash.soundrapandian, Vijay Kumar Tumati, Hangxiang Ma,
Atiya Kailany
Add support for Video Front End (VFE) that is on the SM8750 SoCs. VFE
gen4 has support for VFE 980. This change limits SM8750 VFE output lines
to 3 for now as constrained by the CAMSS driver framework.
The cpas_ahb and cpas_fast_ahb clocks are enabled here rather than in the
CSIPHY resources since they belong to the CPAS/VFE power path, matching
the Kaanapali layout.
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Co-developed-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
Signed-off-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
---
drivers/media/platform/qcom/camss/camss-vfe-gen4.c | 10 +++++++---
drivers/media/platform/qcom/camss/camss-vfe.c | 2 ++
drivers/media/platform/qcom/camss/camss.c | 2 ++
3 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/media/platform/qcom/camss/camss-vfe-gen4.c b/drivers/media/platform/qcom/camss/camss-vfe-gen4.c
index d73d70898710..46d8e61b9bac 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe-gen4.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe-gen4.c
@@ -13,8 +13,12 @@
#include "camss.h"
#include "camss-vfe.h"
-/* VFE-gen4 Bus Register Base Addresses */
-#define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x800 : 0x1000)
+#define IS_VFE_980(vfe) ((vfe)->camss->res->version == CAMSS_8750)
+
+#define BUS_REG_BASE_980 (vfe_is_lite(vfe) ? 0x200 : 0x800)
+#define BUS_REG_BASE_1080 (vfe_is_lite(vfe) ? 0x800 : 0x1000)
+#define BUS_REG_BASE \
+ (IS_VFE_980(vfe) ? BUS_REG_BASE_980 : BUS_REG_BASE_1080)
#define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08)
#define WM_CGC_OVERRIDE_ALL (0x7FFFFFF)
@@ -55,7 +59,7 @@
* DISPLAY_DS2_C 6
* FD_Y 7
* FD_C 8
- * PIXEL_RAW 9
+ * RAW_OUT(1080)/IR_OUT(980) 9
* STATS_AEC_BG 10
* STATS_AEC_BHIST 11
* STATS_TINTLESS_BG 12
diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
index 826ab85a44a1..ffa61ce021b4 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe.c
@@ -352,6 +352,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
case CAMSS_845:
case CAMSS_8550:
case CAMSS_8650:
+ case CAMSS_8750:
case CAMSS_8775P:
case CAMSS_KAANAPALI:
case CAMSS_X1E80100:
@@ -2016,6 +2017,7 @@ static int vfe_bpl_align_rdi(struct vfe_device *vfe)
case CAMSS_845:
case CAMSS_8550:
case CAMSS_8650:
+ case CAMSS_8750:
case CAMSS_8775P:
case CAMSS_KAANAPALI:
case CAMSS_X1E80100:
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index e0b181ff33aa..011ece0a7692 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -6160,9 +6160,11 @@ static const struct camss_resources sm8750_resources = {
.pd_name = "top",
.csiphy_res = csiphy_res_kaanapali,
.csid_res = csid_res_sm8750,
+ .vfe_res = vfe_res_kaanapali,
.icc_res = icc_res_sm8750,
.csiphy_num = ARRAY_SIZE(csiphy_res_kaanapali),
.csid_num = ARRAY_SIZE(csid_res_sm8750),
+ .vfe_num = ARRAY_SIZE(vfe_res_kaanapali),
.icc_path_num = ARRAY_SIZE(icc_res_sm8750),
};
--
2.34.1
--
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https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v6 7/7] media: qcom: camss: tpg: Add support for v2.3.0 TPG
2026-07-21 12:45 [PATCH v6 0/7] media: qcom: camss: Add SM8750 support Hangxiang Ma
` (5 preceding siblings ...)
2026-07-21 12:46 ` [PATCH v6 6/7] media: qcom: camss: vfe: Add support for VFE 980 Hangxiang Ma
@ 2026-07-21 12:46 ` Hangxiang Ma
2026-07-22 7:00 ` [PATCH v6 0/7] media: qcom: camss: Add SM8750 support Krzysztof Kozlowski
7 siblings, 0 replies; 15+ messages in thread
From: Hangxiang Ma @ 2026-07-21 12:46 UTC (permalink / raw)
To: Robert Foss, Todor Tomov, Bryan O'Donoghue,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Loic Poulain, Vinod Koul, Neil Armstrong
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, linux-phy,
jeyaprakash.soundrapandian, Vijay Kumar Tumati, Hangxiang Ma
Add support for the TPG found on SM8750. This TPG uses hardware version
2.3.0, which drives test-enable and reset through a separate
TPG_CTRL_CMD register instead of TPG_CTRL, and routes its output into
the CSID 980 RX via the CSI2 TPG mux.
The 2.3.0 and 2.4.0 (Kaanapali) TPGs share the same programming model,
so reuse the Kaanapali TPG resources for SM8750 and lower the hardware
version gate in the TPG gen1 driver from 2.4.0 to 2.3.0.
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
---
drivers/media/platform/qcom/camss/camss-csid-980.c | 15 +++++++++++++--
drivers/media/platform/qcom/camss/camss-tpg-gen1.c | 9 +++++----
drivers/media/platform/qcom/camss/camss.c | 2 ++
3 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/drivers/media/platform/qcom/camss/camss-csid-980.c b/drivers/media/platform/qcom/camss/camss-csid-980.c
index 6714b8aa8c2a..16184fe69398 100644
--- a/drivers/media/platform/qcom/camss/camss-csid-980.c
+++ b/drivers/media/platform/qcom/camss/camss-csid-980.c
@@ -68,6 +68,8 @@
#define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1
#define CSI2_RX_CFG0_DL0_INPUT_SEL 4
#define CSI2_RX_CFG0_PHY_NUM_SEL 20
+#define CSI2_RX_CFG0_TPG_MUX_EN BIT(27)
+#define CSI2_RX_CFG0_TPG_MUX_SEL GENMASK(29, 28)
#define CSID_CSI2_RX_CFG1 (csid_is_lite(csid) ? 0x204 : 0x404)
#define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0)
#define CSI2_RX_CFG1_VC_MODE BIT(2)
@@ -183,12 +185,21 @@ static void __csid_aup_rup_clear(struct csid_device *csid, int port_id)
static void __csid_configure_rx(struct csid_device *csid,
struct csid_phy_config *phy)
{
+ struct camss *camss = csid->camss;
int val;
val = (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES;
val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL;
- val |= (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX)
- << CSI2_RX_CFG0_PHY_NUM_SEL;
+
+ if (camss->tpg && csid->tpg_linked &&
+ camss->tpg[phy->csiphy_id].testgen.mode != TPG_PAYLOAD_MODE_DISABLED) {
+ val |= FIELD_PREP(CSI2_RX_CFG0_TPG_MUX_SEL, phy->csiphy_id + 1);
+ val |= CSI2_RX_CFG0_TPG_MUX_EN;
+ } else {
+ val |= (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX)
+ << CSI2_RX_CFG0_PHY_NUM_SEL;
+ }
+
writel(val, csid->base + CSID_CSI2_RX_CFG0);
val = CSI2_RX_CFG1_ECC_CORRECTION_EN;
diff --git a/drivers/media/platform/qcom/camss/camss-tpg-gen1.c b/drivers/media/platform/qcom/camss/camss-tpg-gen1.c
index 770a9e5d5ba5..5c452f7a412d 100644
--- a/drivers/media/platform/qcom/camss/camss-tpg-gen1.c
+++ b/drivers/media/platform/qcom/camss/camss-tpg-gen1.c
@@ -22,6 +22,7 @@
#define TPG_HW_VER_2_0_0 TPG_HW_VER(2, 0, 0)
#define TPG_HW_VER_2_1_0 TPG_HW_VER(2, 1, 0)
+#define TPG_HW_VER_2_3_0 TPG_HW_VER(2, 3, 0)
#define TPG_HW_VER_2_4_0 TPG_HW_VER(2, 4, 0)
#define TPG_HW_STATUS 0x4
@@ -170,7 +171,7 @@ static int tpg_stream_on(struct tpg_device *tpg)
val = FIELD_PREP(TPG_CTRL_NUM_ACTIVE_LANES, lane_cnt - 1) |
FIELD_PREP(TPG_CTRL_NUM_ACTIVE_VC, last_vc);
- if (tpg->hw_version >= TPG_HW_VER_2_4_0) {
+ if (tpg->hw_version >= TPG_HW_VER_2_3_0) {
writel(val, tpg->base + TPG_CTRL);
writel(TPG_CTRL_CMD_TEST_EN, tpg->base + TPG_CTRL_CMD);
} else {
@@ -184,10 +185,10 @@ static int tpg_stream_on(struct tpg_device *tpg)
static int tpg_reset(struct tpg_device *tpg)
{
/*
- * On TPG older than v2.4.0 test-enable lives in TPG_CTRL, so clear it
- * first; v2.4.0+ drives both test-enable and reset through TPG_CTRL_CMD.
+ * On TPG older than v2.3.0 test-enable lives in TPG_CTRL, so clear it
+ * first; v2.3.0+ drives both test-enable and reset through TPG_CTRL_CMD.
*/
- if (tpg->hw_version < TPG_HW_VER_2_4_0)
+ if (tpg->hw_version < TPG_HW_VER_2_3_0)
writel(0, tpg->base + TPG_CTRL);
writel(TPG_CTRL_CMD_HW_RESET, tpg->base + TPG_CTRL_CMD);
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 011ece0a7692..418deb74cd98 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -6159,10 +6159,12 @@ static const struct camss_resources sm8750_resources = {
.version = CAMSS_8750,
.pd_name = "top",
.csiphy_res = csiphy_res_kaanapali,
+ .tpg_res = tpg_res_x1e80100,
.csid_res = csid_res_sm8750,
.vfe_res = vfe_res_kaanapali,
.icc_res = icc_res_sm8750,
.csiphy_num = ARRAY_SIZE(csiphy_res_kaanapali),
+ .tpg_num = ARRAY_SIZE(tpg_res_x1e80100),
.csid_num = ARRAY_SIZE(csid_res_sm8750),
.vfe_num = ARRAY_SIZE(vfe_res_kaanapali),
.icc_path_num = ARRAY_SIZE(icc_res_sm8750),
--
2.34.1
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^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v6 0/7] media: qcom: camss: Add SM8750 support
2026-07-21 12:45 [PATCH v6 0/7] media: qcom: camss: Add SM8750 support Hangxiang Ma
` (6 preceding siblings ...)
2026-07-21 12:46 ` [PATCH v6 7/7] media: qcom: camss: tpg: Add support for v2.3.0 TPG Hangxiang Ma
@ 2026-07-22 7:00 ` Krzysztof Kozlowski
2026-07-22 8:02 ` Hangxiang Ma
7 siblings, 1 reply; 15+ messages in thread
From: Krzysztof Kozlowski @ 2026-07-22 7:00 UTC (permalink / raw)
To: Hangxiang Ma
Cc: Robert Foss, Todor Tomov, Bryan O'Donoghue,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Loic Poulain, Vinod Koul, Neil Armstrong, linux-media,
linux-arm-msm, devicetree, linux-kernel, linux-phy,
jeyaprakash.soundrapandian, Vijay Kumar Tumati,
Krzysztof Kozlowski, Atiya Kailany
On Tue, Jul 21, 2026 at 05:45:59AM -0700, Hangxiang Ma wrote:
> Add support for the RDI only CAMSS camera driver on SM8750. Enabling
> RDI path involves adding the support for a set of CSIPHY, CSID and TFE
> modules, with each TFE having multiple RDI ports. This hardware
> architecture requires 'qdss_debug_xo' clock for CAMNOC to be functional.
>
> SM8750 camera subsystem provides:
> - 6 x CSIPHY (CSI Physical Layer)
> - 3 x TPG (Test Pattern Generator)
> - 3 x CSID (CSI Decoder)
> - 2 x CSID Lite
> - 3 x VFE (Video Front End), 5 RDI per VFE
> - 2 x VFE Lite, 4 RDI per VFE Lite
>
> This series has been tested using the following commands with S5KJN5 sensor.
> - media-ctl --reset
> - media-ctl -V '"msm_csiphy2":0[fmt:SGBRG10/4096x3072]'
> - media-ctl -V '"msm_csid0":0[fmt:SGBRG10/4096x3072]'
> - media-ctl -V '"msm_vfe0_rdi0":0[fmt:SGBRG10/4096x3072]'
> - media-ctl -l '"msm_csiphy2":1->"msm_csid0":0[1]'
> - media-ctl -l '"msm_csid0":1->"msm_vfe0_rdi0":0[1]'
> - yavta --capture=20 -I -n 5 -f SGBRG10P -s 4096x3072 -F /dev/video0
>
> Dependencies:
> - https://lore.kernel.org/all/20260720-x1e-csi2-phy-v13-0-160c31958863@linaro.org/
> - https://lore.kernel.org/all/20260708-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v12-0-f8588da41f16@linaro.org/
> - https://lore.kernel.org/all/20260720-kaanapali-camss-v15-0-c0b1c1167c5d@oss.qualcomm.com/
None of these were cleared for merging. IOW, all received comments yet
you send work which depends on it.
This is exactly something Bjorn said a week ago or so. And then a few
other maintainers re-iterated. Exactly the same, nothing learnt.
Best regards,
Krzysztof
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^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v6 0/7] media: qcom: camss: Add SM8750 support
2026-07-22 7:00 ` [PATCH v6 0/7] media: qcom: camss: Add SM8750 support Krzysztof Kozlowski
@ 2026-07-22 8:02 ` Hangxiang Ma
2026-07-22 8:19 ` Krzysztof Kozlowski
0 siblings, 1 reply; 15+ messages in thread
From: Hangxiang Ma @ 2026-07-22 8:02 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Robert Foss, Todor Tomov, Bryan O'Donoghue,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Loic Poulain, Vinod Koul, Neil Armstrong, linux-media,
linux-arm-msm, devicetree, linux-kernel, linux-phy,
jeyaprakash.soundrapandian, Vijay Kumar Tumati,
Krzysztof Kozlowski, Atiya Kailany
On 7/22/2026 3:00 PM, Krzysztof Kozlowski wrote:
> On Tue, Jul 21, 2026 at 05:45:59AM -0700, Hangxiang Ma wrote:
>> Add support for the RDI only CAMSS camera driver on SM8750. Enabling
>> RDI path involves adding the support for a set of CSIPHY, CSID and TFE
>> modules, with each TFE having multiple RDI ports. This hardware
>> architecture requires 'qdss_debug_xo' clock for CAMNOC to be functional.
>>
>> SM8750 camera subsystem provides:
>> - 6 x CSIPHY (CSI Physical Layer)
>> - 3 x TPG (Test Pattern Generator)
>> - 3 x CSID (CSI Decoder)
>> - 2 x CSID Lite
>> - 3 x VFE (Video Front End), 5 RDI per VFE
>> - 2 x VFE Lite, 4 RDI per VFE Lite
>>
>> This series has been tested using the following commands with S5KJN5 sensor.
>> - media-ctl --reset
>> - media-ctl -V '"msm_csiphy2":0[fmt:SGBRG10/4096x3072]'
>> - media-ctl -V '"msm_csid0":0[fmt:SGBRG10/4096x3072]'
>> - media-ctl -V '"msm_vfe0_rdi0":0[fmt:SGBRG10/4096x3072]'
>> - media-ctl -l '"msm_csiphy2":1->"msm_csid0":0[1]'
>> - media-ctl -l '"msm_csid0":1->"msm_vfe0_rdi0":0[1]'
>> - yavta --capture=20 -I -n 5 -f SGBRG10P -s 4096x3072 -F /dev/video0
>>
>> Dependencies:
>> - https://lore.kernel.org/all/20260720-x1e-csi2-phy-v13-0-160c31958863@linaro.org/
>> - https://lore.kernel.org/all/20260708-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v12-0-f8588da41f16@linaro.org/
>> - https://lore.kernel.org/all/20260720-kaanapali-camss-v15-0-c0b1c1167c5d@oss.qualcomm.com/
>
> None of these were cleared for merging. IOW, all received comments yet
> you send work which depends on it.
>
> This is exactly something Bjorn said a week ago or so. And then a few
> other maintainers re-iterated. Exactly the same, nothing learnt.
>
> Best regards,
> Krzysztof
>
I understand the concern and agree that posting dependent work before
the prerequisite series has been fully reviewed and cleared for merging
is not ideal. The reason these series were posted at this stage was due
to internal planning requirements and the need to keep work on other
dependent platforms moving in parallel. The early review is aim to
avoiding blocking them too much. That's a dilemma that I was asked to
handle it in this way.
However, I understand that this can create additional review overhead
and confusion regarding the status of the prerequisite work. Will
transfer your concern internally to try to avoid other colleagues
posting more series that has much long chain dependencies.
Apologies for the inconvenience, and thanks for the feedback.
Best regards,
Hangxiang
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v6 0/7] media: qcom: camss: Add SM8750 support
2026-07-22 8:02 ` Hangxiang Ma
@ 2026-07-22 8:19 ` Krzysztof Kozlowski
0 siblings, 0 replies; 15+ messages in thread
From: Krzysztof Kozlowski @ 2026-07-22 8:19 UTC (permalink / raw)
To: Hangxiang Ma
Cc: Robert Foss, Todor Tomov, Bryan O'Donoghue,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Loic Poulain, Vinod Koul, Neil Armstrong, linux-media,
linux-arm-msm, devicetree, linux-kernel, linux-phy,
jeyaprakash.soundrapandian, Vijay Kumar Tumati,
Krzysztof Kozlowski, Atiya Kailany
On 22/07/2026 10:02, Hangxiang Ma wrote:
> On 7/22/2026 3:00 PM, Krzysztof Kozlowski wrote:
>> On Tue, Jul 21, 2026 at 05:45:59AM -0700, Hangxiang Ma wrote:
>>> Add support for the RDI only CAMSS camera driver on SM8750. Enabling
>>> RDI path involves adding the support for a set of CSIPHY, CSID and TFE
>>> modules, with each TFE having multiple RDI ports. This hardware
>>> architecture requires 'qdss_debug_xo' clock for CAMNOC to be functional.
>>>
>>> SM8750 camera subsystem provides:
>>> - 6 x CSIPHY (CSI Physical Layer)
>>> - 3 x TPG (Test Pattern Generator)
>>> - 3 x CSID (CSI Decoder)
>>> - 2 x CSID Lite
>>> - 3 x VFE (Video Front End), 5 RDI per VFE
>>> - 2 x VFE Lite, 4 RDI per VFE Lite
>>>
>>> This series has been tested using the following commands with S5KJN5 sensor.
>>> - media-ctl --reset
>>> - media-ctl -V '"msm_csiphy2":0[fmt:SGBRG10/4096x3072]'
>>> - media-ctl -V '"msm_csid0":0[fmt:SGBRG10/4096x3072]'
>>> - media-ctl -V '"msm_vfe0_rdi0":0[fmt:SGBRG10/4096x3072]'
>>> - media-ctl -l '"msm_csiphy2":1->"msm_csid0":0[1]'
>>> - media-ctl -l '"msm_csid0":1->"msm_vfe0_rdi0":0[1]'
>>> - yavta --capture=20 -I -n 5 -f SGBRG10P -s 4096x3072 -F /dev/video0
>>>
>>> Dependencies:
>>> - https://lore.kernel.org/all/20260720-x1e-csi2-phy-v13-0-160c31958863@linaro.org/
>>> - https://lore.kernel.org/all/20260708-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v12-0-f8588da41f16@linaro.org/
>>> - https://lore.kernel.org/all/20260720-kaanapali-camss-v15-0-c0b1c1167c5d@oss.qualcomm.com/
>>
>> None of these were cleared for merging. IOW, all received comments yet
>> you send work which depends on it.
>>
>> This is exactly something Bjorn said a week ago or so. And then a few
>> other maintainers re-iterated. Exactly the same, nothing learnt.
>>
>> Best regards,
>> Krzysztof
>>
> I understand the concern and agree that posting dependent work before
> the prerequisite series has been fully reviewed and cleared for merging
> is not ideal. The reason these series were posted at this stage was due
> to internal planning requirements and the need to keep work on other
But upstream open-source community does not care about your internal
planning requirements.
Your internal planning is not a valid reason to do anything here.
> dependent platforms moving in parallel. The early review is aim to
Then why isn't this marked as early review? How early review of
unfinished unmergeable work is supposed to be called? There is very
clear naming required for such work.
> avoiding blocking them too much. That's a dilemma that I was asked to
> handle it in this way.
Best regards,
Krzysztof
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^ permalink raw reply [flat|nested] 15+ messages in thread