[PATCH v3 0/6] Enable IPQ5018 PCI support

[PATCH v3 0/6] Enable IPQ5018 PCI support

[George Moussalem]

From: Sricharan Ramabadhran <quic_srichara@quicinc.com>

This patch series adds the relevant phy and controller
DT configurations for enabling PCI gen2 support
on IPQ5018. IPQ5018 has two phys and two controllers, 
one dual-lane and one single-lane.

Last patch series (v2) submitted dates back to August 27, 2024.
As I've worked to add IPQ5018 platform support in OpenWrt, I'm
continuing the efforts to add Linux kernel support.

v3:
  *) Depends on: https://patchwork.kernel.org/project/linux-arm-msm/cover/20250220094251.230936-1-quic_varada@quicinc.com/
  *) Added 8 MSI SPI and 1 global interrupts (Thanks Mani for confirming)
  *) Added hw revision (internal/synopsys) and nr of lanes in patch 4
     commit msg
  *) Sorted reg addresses and moved PCIe nodes accordingly
  *) Moved to GIC based interrupts
  *) Added rootport node in controller nodes
  *) Tested on Linksys devices (MX5500/SPNMX56)
  *) Link to v2: https://lore.kernel.org/all/20240827045757.1101194-1-quic_srichara@quicinc.com/

v2:
  Fixed all review comments from Krzysztof, Robert Marko,
  Dmitry Baryshkov, Manivannan Sadhasivam, Konrad Dybcio.
  Updated the respective patches for their changes.

v1:
 https://lore.kernel.org/lkml/32389b66-48f3-8ee8-e2f1-1613feed3cc7@gmail.com/T/

Sricharan Ramabadhran (6):
  dt-bindings: phy: qcom: uniphy-pcie: Add ipq5018 compatible
  phy: qualcomm: qcom-uniphy-pcie 28LP add support for IPQ5018
  dt-bindings: PCI: qcom: Add IPQ5018 SoC
  PCI: qcom: Add support for IPQ5018
  arm64: dts: qcom: ipq5018: Add PCIe related nodes
  arm64: dts: qcom: ipq5018: Enable PCIe

 .../devicetree/bindings/pci/qcom,pcie.yaml    |  49 ++++
 .../phy/qcom,ipq5332-uniphy-pcie-phy.yaml     |   3 +-
 .../arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts |  38 +++
 arch/arm64/boot/dts/qcom/ipq5018.dtsi         | 232 +++++++++++++++++-
 drivers/pci/controller/dwc/pcie-qcom.c        |   1 +
 .../phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c  |  45 ++++
 6 files changed, 365 insertions(+), 3 deletions(-)

-- 
2.48.1



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Re: [PATCH v3 0/6] Enable IPQ5018 PCI support

[Krzysztof Kozlowski]

On 05/03/2025 14:41, George Moussalem wrote:
> From: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> 
> This patch series adds the relevant phy and controller
> DT configurations for enabling PCI gen2 support
> on IPQ5018. IPQ5018 has two phys and two controllers, 
> one dual-lane and one single-lane.
> 
> Last patch series (v2) submitted dates back to August 27, 2024.
> As I've worked to add IPQ5018 platform support in OpenWrt, I'm
> continuing the efforts to add Linux kernel support.

Why is this changelog separate? We talked about this 5 revisions ago and
you keep doing the same mistakes.

Best regards,
Krzysztof

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Re: [PATCH v3 0/6] Enable IPQ5018 PCI support

[George Moussalem]

On 3/5/25 20:47, Krzysztof Kozlowski wrote:
> On 05/03/2025 14:41, George Moussalem wrote:
>> From: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>>
>> This patch series adds the relevant phy and controller
>> DT configurations for enabling PCI gen2 support
>> on IPQ5018. IPQ5018 has two phys and two controllers, 
>> one dual-lane and one single-lane.
>>
>> Last patch series (v2) submitted dates back to August 27, 2024.
>> As I've worked to add IPQ5018 platform support in OpenWrt, I'm
>> continuing the efforts to add Linux kernel support.
> Why is this changelog separate? We talked about this 5 revisions ago and
> you keep doing the same mistakes.
I've finally figured it out. It wasn't a git send-email bug I was running into.
I just analyzed the entire mail flow and found Outlook.com smtp servers replace the Message-ID
header value with the server name handling the email and places the actual Message-ID in another attribute
called X-Microsoft-Original-Message-ID. So when send-email sets the In-Reply-To header,
it uses the right one but the outlook.com mail servers replaced it with another value so threading breaks.

As a workaround, which I just tested, I will send the cover letter separately first, pick up the value
of Message-ID (which isn't the original one), and send the remaining patches with the --in-reply-to
argument of git send-email set to the newly replaced Message-ID.

This works. And apologies for the confusion/mess.
>
> Best regards,
> Krzysztof
Best regards,
George

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[PATCH v3 0/6] Enable IPQ5018 PCI support

[George Moussalem]

From: Sricharan Ramabadhran <quic_srichara@quicinc.com>

This patch series adds the relevant phy and controller
DT configurations for enabling PCI gen2 support
on IPQ5018. IPQ5018 has two phys and two controllers, 
one dual-lane and one single-lane.

Last patch series (v2) submitted dates back to August 27, 2024.
As I've worked to add IPQ5018 platform support in OpenWrt, I'm
continuing the efforts to add Linux kernel support.

v3:
  *) Depends on: https://patchwork.kernel.org/project/linux-arm-msm/cover/20250220094251.230936-1-quic_varada@quicinc.com/
  *) Added 8 MSI SPI and 1 global interrupts (Thanks Mani for confirming)
  *) Added hw revision (internal/synopsys) and nr of lanes in patch 4
     commit msg
  *) Sorted reg addresses and moved PCIe nodes accordingly
  *) Moved to GIC based interrupts
  *) Added rootport node in controller nodes
  *) Tested on Linksys devices (MX5500/SPNMX56)
  *) Link to v2: https://lore.kernel.org/all/20240827045757.1101194-1-quic_srichara@quicinc.com/

v2:
  Fixed all review comments from Krzysztof, Robert Marko,
  Dmitry Baryshkov, Manivannan Sadhasivam, Konrad Dybcio.
  Updated the respective patches for their changes.

v1:
 https://lore.kernel.org/lkml/32389b66-48f3-8ee8-e2f1-1613feed3cc7@gmail.com/T/

Sricharan Ramabadhran (6):
  dt-bindings: phy: qcom: uniphy-pcie: Add ipq5018 compatible
  phy: qualcomm: qcom-uniphy-pcie 28LP add support for IPQ5018
  dt-bindings: PCI: qcom: Add IPQ5018 SoC
  PCI: qcom: Add support for IPQ5018
  arm64: dts: qcom: ipq5018: Add PCIe related nodes
  arm64: dts: qcom: ipq5018: Enable PCIe

 .../devicetree/bindings/pci/qcom,pcie.yaml    |  49 ++++
 .../phy/qcom,ipq5332-uniphy-pcie-phy.yaml     |   3 +-
 .../arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts |  38 +++
 arch/arm64/boot/dts/qcom/ipq5018.dtsi         | 232 +++++++++++++++++-
 drivers/pci/controller/dwc/pcie-qcom.c        |   1 +
 .../phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c  |  45 ++++
 6 files changed, 365 insertions(+), 3 deletions(-)

-- 
2.48.1


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Re: [PATCH v3 0/6] Enable IPQ5018 PCI support

[Krzysztof Kozlowski]

On 05/03/2025 14:41, George Moussalem wrote:
> From: Sricharan Ramabadhran <quic_srichara@quicinc.com>

Not correct From. Cover letter should be written by you.

> 
> This patch series adds the relevant phy and controller
> DT configurations for enabling PCI gen2 support
> on IPQ5018. IPQ5018 has two phys and two controllers, 
> one dual-lane and one single-lane.
> 
> Last patch series (v2) submitted dates back to August 27, 2024.
> As I've worked to add IPQ5018 platform support in OpenWrt, I'm
> continuing the efforts to add Linux kernel support.
> 
> v3:
>   *) Depends on: https://patchwork.kernel.org/project/linux-arm-msm/cover/20250220094251.230936-1-quic_varada@quicinc.com/


Wasn't this applied, so why is it still a dependency?



>   *) Added 8 MSI SPI and 1 global interrupts (Thanks Mani for confirming)

Who did it? This v3 or other v3? Which v3 is this one here?


Best regards,
Krzysztof

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Re: [PATCH v3 0/6] Enable IPQ5018 PCI support

[George Moussalem]

> On 05/03/2025 14:41, George Moussalem wrote:
>> From: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> Not correct From. Cover letter should be written by you.
Noted. I thought I'd keep the original author included and added my v3 changes which you rightfully pointed out should have been v4 instead.
Will remove in next version.
>
>> This patch series adds the relevant phy and controller
>> DT configurations for enabling PCI gen2 support
>> on IPQ5018. IPQ5018 has two phys and two controllers, 
>> one dual-lane and one single-lane.
>>
>> Last patch series (v2) submitted dates back to August 27, 2024.
>> As I've worked to add IPQ5018 platform support in OpenWrt, I'm
>> continuing the efforts to add Linux kernel support.
>>
>> v3:
>>   *) Depends on: https://patchwork.kernel.org/project/linux-arm-msm/cover/20250220094251.230936-1-quic_varada@quicinc.com/
>
> Wasn't this applied, so why is it still a dependency?
I explicitly added it as ipq5332 has not made it to the master branch yet. Should I remove?
>
>
>
>>   *) Added 8 MSI SPI and 1 global interrupts (Thanks Mani for confirming)
> Who did it? This v3 or other v3? Which v3 is this one here?
As I mentioned, I overlooked the v3 submission and based this series as the next version of v2. Thanks for pointing it out.
>
>
> Best regards,
> Krzysztof
Cheers,
George

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Re: [PATCH v3 0/6] Enable IPQ5018 PCI support

[Krzysztof Kozlowski]

On 05/03/2025 17:59, George Moussalem wrote:
>> On 05/03/2025 14:41, George Moussalem wrote:
>>> From: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>> Not correct From. Cover letter should be written by you.
> Noted. I thought I'd keep the original author included and added my v3 changes which you rightfully pointed out should have been v4 instead.
> Will remove in next version.
>>
>>> This patch series adds the relevant phy and controller
>>> DT configurations for enabling PCI gen2 support
>>> on IPQ5018. IPQ5018 has two phys and two controllers, 
>>> one dual-lane and one single-lane.
>>>
>>> Last patch series (v2) submitted dates back to August 27, 2024.
>>> As I've worked to add IPQ5018 platform support in OpenWrt, I'm
>>> continuing the efforts to add Linux kernel support.
>>>
>>> v3:
>>>   *) Depends on: https://patchwork.kernel.org/project/linux-arm-msm/cover/20250220094251.230936-1-quic_varada@quicinc.com/
>>
>> Wasn't this applied, so why is it still a dependency?
> I explicitly added it as ipq5332 has not made it to the master branch yet. Should I remove?

If you treat something not yet released as dependency, then please stop
sending so many versions because nothing here can be applied for this cycle.

Why is this a dependency?

Best regards,
Krzysztof

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[PATCH V3 0/6] Enable IPQ5018 PCI support

[Sricharan R]

From: Sricharan Ramabadhran <quic_srichara@quicinc.com>

This patch series adds the relevant phy and controller
DT configurations for enabling PCI gen2 support
on IPQ5018.

v3:
  Added Reviewed-by tag for patch#1.
  Fixed dev_err_probe usage in patch#3.
  Added pinctrl/wak pins for pcie1 in patch#6.

v2:
  Fixed all review comments from Krzysztof, Robert Marko,
  Dmitry Baryshkov, Manivannan Sadhasivam, Konrad Dybcio.
  Updated the respective patches for their changes.

v1:
 https://lore.kernel.org/lkml/32389b66-48f3-8ee8-e2f1-1613feed3cc7@gmail.com/T/

Nitheesh Sekar (5):
  dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy
  dt-bindings: PCI: qcom: Add IPQ5108 SoC
  phy: qcom: Introduce PCIe UNIPHY 28LP driver
  arm64: dts: qcom: ipq5018: Add PCIe related nodes
  arm64: dts: qcom: ipq5018: Enable PCIe

Sricharan R (1):
  PCI: qcom: Add support for IPQ5018

 .../devicetree/bindings/pci/qcom,pcie.yaml    |  35 ++
 .../phy/qcom,ipq5018-uniphy-pcie.yaml         |  70 ++++
 .../arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts |  37 ++
 arch/arm64/boot/dts/qcom/ipq5018.dtsi         | 168 ++++++++-
 drivers/pci/controller/dwc/pcie-qcom.c        |   1 +
 drivers/phy/qualcomm/Kconfig                  |  12 +
 drivers/phy/qualcomm/Makefile                 |   1 +
 .../phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c  | 346 ++++++++++++++++++
 8 files changed, 668 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq5018-uniphy-pcie.yaml
 create mode 100644 drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c

-- 
2.34.1


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