From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: "Wenbin Yao (Consultant)" <quic_wenbyao@quicinc.com>,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: vkoul@kernel.org, kishon@kernel.org, p.zabel@pengutronix.de,
dmitry.baryshkov@linaro.org, abel.vesa@linaro.org,
quic_qianyu@quicinc.com, neil.armstrong@linaro.org,
quic_devipriy@quicinc.com, linux-arm-msm@vger.kernel.org,
linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 2/2] phy: qcom: qmp-pcie: Add PHY register retention support
Date: Mon, 24 Feb 2025 12:46:44 +0100 [thread overview]
Message-ID: <ea5de507-1252-4ff3-9b18-40981624afea@oss.qualcomm.com> (raw)
In-Reply-To: <7ffb09cd-9c77-4407-9087-3e789cd8bf44@quicinc.com>
On 24.02.2025 9:46 AM, Wenbin Yao (Consultant) wrote:
> On 2/24/2025 3:33 PM, Manivannan Sadhasivam wrote:
>> On Thu, Feb 20, 2025 at 06:22:53PM +0800, Wenbin Yao wrote:
>>> From: Qiang Yu <quic_qianyu@quicinc.com>
>>>
>>> Some QCOM PCIe PHYs support no_csr reset. Unlike BCR reset which resets the
>>> whole PHY (hardware and register), no_csr reset only resets PHY hardware
>>> but retains register values, which means PHY setting can be skipped during
>>> PHY init if PCIe link is enabled in booltloader and only no_csr is toggled
>>> after that.
>>>
>>> Hence, determine whether the PHY has been enabled in bootloader by
>>> verifying QPHY_START_CTRL register. If it's programmed and no_csr reset is
>>> available, skip BCR reset and PHY register setting to establish the PCIe
>>> link with bootloader - programmed PHY settings.
>>>
>>> Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
>>> Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com>
>> Some nitpicks below.
>>
>>> ---
[...]
>>
>>> + * In this way, no matter whether the PHY settings were initially
>>> + * programmed by bootloader or PHY driver itself, we can reuse them
>> It is really possible to have bootloader not programming the init sequence for
>> no_csr reset platforms? The comment sounds like it is possible. But I heard the
>> opposite.
>
> PCIe3 on X1E80100 QCP is disabled by default in UEFI. We need to enable it
> manually in UEFI shell if we want.
IIUC this will not be a concern going forward, and this is a special case
Konrad
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next prev parent reply other threads:[~2025-02-24 12:05 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-20 10:22 [PATCH v4 0/2] phy: qcom: qmp-pcie: Add PCIe PHY no_csr reset support Wenbin Yao
2025-02-20 10:22 ` [PATCH v4 1/2] phy: qcom: pcie: Determine has_nocsr_reset dynamically Wenbin Yao
2025-02-20 10:22 ` [PATCH v4 2/2] phy: qcom: qmp-pcie: Add PHY register retention support Wenbin Yao
2025-02-24 7:33 ` Manivannan Sadhasivam
2025-02-24 8:46 ` Wenbin Yao (Consultant)
2025-02-24 11:46 ` Konrad Dybcio [this message]
2025-02-24 12:24 ` Manivannan Sadhasivam
2025-02-25 8:06 ` Wenbin Yao (Consultant)
2025-02-25 8:17 ` Manivannan Sadhasivam
2025-02-25 10:08 ` Qiang Yu
2025-02-25 11:46 ` Dmitry Baryshkov
2025-02-26 3:12 ` Qiang Yu
2025-02-26 5:19 ` Dmitry Baryshkov
2025-02-26 5:31 ` Manivannan Sadhasivam
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