Re: [PATCH RFC v4 9/9] arm64: dts: qcom: glymur: Wire PCIe3a/3b to shared Gen5x8 PHY

From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Qiang Yu <qiang.yu@oss.qualcomm.com>
Cc: Vinod Koul <vkoul@kernel.org>,
	Neil Armstrong <neil.armstrong@linaro.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Bjorn Andersson <andersson@kernel.org>,
	Konrad Dybcio <konradybcio@kernel.org>,
	linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH RFC v4 9/9] arm64: dts: qcom: glymur: Wire PCIe3a/3b to shared Gen5x8 PHY
Date: Fri, 10 Jul 2026 15:25:37 +0200	[thread overview]
Message-ID: <f83556e7-dbb1-4926-a2a0-4690cdbad941@oss.qualcomm.com> (raw)
In-Reply-To: <alDvnSiplhEg2yhD@hu-qianyu-lv.qualcomm.com>

On 7/10/26 3:11 PM, Qiang Yu wrote:
> On Fri, Jul 10, 2026 at 10:44:20AM +0200, Konrad Dybcio wrote:
>> On 7/10/26 4:19 AM, Qiang Yu wrote:
>>> On Mon, Jun 29, 2026 at 11:20:07AM +0200, Konrad Dybcio wrote:
>>>> On 6/29/26 7:05 AM, Qiang Yu wrote:
>>>>> On Wed, Jun 17, 2026 at 01:19:49PM +0200, Konrad Dybcio wrote:
>>>>>> On 5/19/26 7:47 AM, Qiang Yu wrote:
>>>>>>> Glymur PCIe3 uses a single shared Gen5x8 QMP PHY block. Model PCIe3a and
>>>>>>> PCIe3b as consumers of that shared PHY provider instead of separate PHY
>>>>>>> nodes.

[...]

>>>>>>> +			linux,pci-domain = <3>;
>>>>>>> +			num-lanes = <8>;
>>>>>>
>>>>>> Is it fine to keep num-lanes 8 here even for configurations with
>>>>>> bifurcated PHY?
>>>>>>
>>>>>> I would assume so, given essentially this is a x8 host, whose 4
>>>>>> lanes may simply be effectively NC 
>>>>>>
>>>>> Actually, on existing platforms, the PCIe3a and PCIe3b controllers are
>>>>> never enabled at the same time. When PCIe3a is exposed, it is always in an
>>>>> x8 slot. But if we have a x4+x4 platform in future, we can simply override
>>>>> num-lanes to 4 in the board.dts.
>>>>
>>>> My question is whether that will be necessary - if yes, sure, we
>>>> can do it, but if not, we can conclude on this early and not have
>>>> to fight over it in a couple months
>>>>
>>> I think we do need to override it in that case. If both PCIe3a and PCIe3b
>>> are enabled in x4+x4 mode but PCIe3a keeps num-lanes = <8>, userspace
>>> will see an 8-lane slot. If an x8-capable EP is connected to that slot,
>>> both ends will advertise x8 support, but the link is up at x4. That looks
>>> like a genuine bug from the user's point of view.
>>
>> Do we know what's advertised on x86 PCs with bifurcated lanes?
>>
> On QCB, it advertise x8. On CRD, PCIe3a is hidden.

No no, I meant to ask whether we know what the userspace gets to see on
e.g. an AMD system with a bifurcated slot. I would expect that LnkCap
may report a different value, but not necessarily. I would assume we
should probably mimic whatever that does, unless the spec takes a
stance on what should be done.

Konrad

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