* Re: [PATCH v4 12/25] scsi: ufs: mediatek: Remove vendor kernel quirks cruft
From: Peter Wang (王信友) @ 2026-01-06 13:25 UTC (permalink / raw)
To: chu.stanley@gmail.com, robh@kernel.org,
Chunfeng Yun (云春峰), kishon@kernel.org,
James.Bottomley@HansenPartnership.com, bvanassche@acm.org,
AngeloGioacchino Del Regno, neil.armstrong@linaro.org,
conor+dt@kernel.org, Chaotian Jing (井朝天),
lgirdwood@gmail.com, nicolas.frattaroli@collabora.com,
vkoul@kernel.org, krzk+dt@kernel.org, p.zabel@pengutronix.de,
alim.akhtar@samsung.com, matthias.bgg@gmail.com,
avri.altman@wdc.com, martin.petersen@oracle.com,
broonie@kernel.org
Cc: linux-scsi@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-phy@lists.infradead.org, linux-mediatek@lists.infradead.org,
Louis-Alexis Eyraud, kernel@collabora.com
In-Reply-To: <20251218-mt8196-ufs-v4-12-ddec7a369dd2@collabora.com>
On Thu, 2025-12-18 at 13:55 +0100, Nicolas Frattaroli wrote:
>
> Both ufs_mtk_vreg_fix_vcc and ufs_mtk_vreg_fix_vccqx look like they
> are
> vendor kernel hacks to work around existing downstream device trees.
> Mainline does not need or want them, so remove them.
>
Hi Nicolas,
This is a flexible approach to implement one software supporting
multiple
hardware configurations. Because you cannot guarantee that your SOC
will
always use UFS 2.0 or UFS 3.0, or that the PMIC you use will only have
one set.
Thanks
Peter
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* Re: [PATCH v4 11/25] scsi: ufs: mediatek: Rework probe function
From: Peter Wang (王信友) @ 2026-01-06 13:23 UTC (permalink / raw)
To: chu.stanley@gmail.com, robh@kernel.org,
Chunfeng Yun (云春峰), kishon@kernel.org,
James.Bottomley@HansenPartnership.com, bvanassche@acm.org,
AngeloGioacchino Del Regno, neil.armstrong@linaro.org,
conor+dt@kernel.org, Chaotian Jing (井朝天),
lgirdwood@gmail.com, nicolas.frattaroli@collabora.com,
vkoul@kernel.org, krzk+dt@kernel.org, p.zabel@pengutronix.de,
alim.akhtar@samsung.com, matthias.bgg@gmail.com,
avri.altman@wdc.com, martin.petersen@oracle.com,
broonie@kernel.org
Cc: linux-scsi@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-phy@lists.infradead.org, linux-mediatek@lists.infradead.org,
Louis-Alexis Eyraud, kernel@collabora.com
In-Reply-To: <20251218-mt8196-ufs-v4-11-ddec7a369dd2@collabora.com>
On Thu, 2025-12-18 at 13:55 +0100, Nicolas Frattaroli wrote:
>
> Remove the ti,syscon-reset cruft.
>
Hi Nicolas,
Why do we need to remove the reset node? If an error occurs and the
host
does not perform a reset, it could lead to error recovery failure.
Thanks.
Peter
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* Re: [PATCH v4 09/25] scsi: ufs: mediatek: Rework the crypt-boost stuff
From: Peter Wang (王信友) @ 2026-01-06 13:22 UTC (permalink / raw)
To: chu.stanley@gmail.com, robh@kernel.org,
Chunfeng Yun (云春峰), kishon@kernel.org,
James.Bottomley@hansenpartnership.com, bvanassche@acm.org,
AngeloGioacchino Del Regno,
Chaotian Jing (井朝天), conor+dt@kernel.org,
lgirdwood@gmail.com, nicolas.frattaroli@collabora.com,
vkoul@kernel.org, krzk+dt@kernel.org, p.zabel@pengutronix.de,
alim.akhtar@samsung.com, neil.armstrong@linaro.org,
matthias.bgg@gmail.com, avri.altman@wdc.com, broonie@kernel.org,
martin.petersen@oracle.com
Cc: linux-scsi@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-phy@lists.infradead.org, linux-mediatek@lists.infradead.org,
Louis-Alexis Eyraud, kernel@collabora.com
In-Reply-To: <5038393.GXAFRqVoOG@workhorse>
On Mon, 2026-01-05 at 09:05 +0100, Nicolas Frattaroli wrote:
> On Wednesday, 24 December 2025 07:16:34 Central European Standard
> Time Peter Wang (王信友) wrote:
> > On Thu, 2025-12-18 at 13:54 +0100, Nicolas Frattaroli wrote:
> > > -
> > > -static void ufs_mtk_init_boost_crypt(struct ufs_hba *hba)
> > > +static int ufs_mtk_init_boost_crypt(struct ufs_hba *hba)
> > >
> >
> > Hi Nicolas,
> >
> > Please do not change the return type if you are not checking the
> > return
> > value.
> >
> >
> >
> >
> > Should free the cfg memory?
>
> It's a devres alloc. It'll get freed on driver removal automatically.
> Freeing it manually would be a double-free once the driver unloads.
Hi Nicolas,
Got it. Please feel free to add my review tag when you correct the
return type.
Thanks.
Peter
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* Re: [PATCH V3 0/4] Add UFS support for x1e80100 SoC
From: Pradeep Pragallapati @ 2026-01-06 13:03 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, martin.petersen,
andersson, konradybcio, taniya.das, manivannan.sadhasivam,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
nitin.rawat
In-Reply-To: <y7lm6zqgbhk4243diyotvox75tcmzhgbkypbkaskrtjcjbruwm@ar7kjmiyv2wr>
On 1/6/2026 3:50 AM, Dmitry Baryshkov wrote:
> On Mon, Jan 05, 2026 at 08:16:39PM +0530, Pradeep P V K wrote:
>> Add UFSPHY, UFSHC compatible binding names and UFS devicetree
>> enablement changes for Qualcomm x1e80100 SoC.
>>
>> Changes in V3:
>> - Update all dt-bindings commit messages with concise and informative
>> statements [Krzysztof]
>> - keep the QMP UFS PHY order by last compatible in numerical ascending
>> order [Krzysztof]
>> - Remove qcom,x1e80100-ufshc from select: enum: list of
>> qcom,sc7180-ufshc.yaml file [Krzysztof]
>> - Update subject prefix for all dt-bindings [Krzysztof]
>> - Add RB-by for SoC dtsi [Konrad, Abel, Taniya]
>> - Add RB-by for board dts [Konrad]
>> - Link to V2:
>> https://lore.kernel.org/all/20251231101951.1026163-1-pradeep.pragallapati@oss.qualcomm.com
>
> Where did the previous changelog go?
i missed to amend, i will update all changelog in my next patchset.
>
>>
>> ---
>> Pradeep P V K (4):
>> dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Add QMP UFS PHY
>> compatible
>> dt-bindings: ufs: qcom,sc7180-ufshc: Add UFSHC compatible for x1e80100
>> arm64: dts: qcom: hamoa: Add UFS nodes for x1e80100 SoC
>> arm64: dts: qcom: hamoa-iot-evk: Enable UFS
>>
>> .../phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 4 +
>> .../bindings/ufs/qcom,sc7180-ufshc.yaml | 37 +++---
>> arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 18 +++
>> arch/arm64/boot/dts/qcom/hamoa.dtsi | 123 +++++++++++++++++-
>> 4 files changed, 164 insertions(+), 18 deletions(-)
>>
>> --
>> 2.34.1
>>
>
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* Re: [PATCH V3 3/4] arm64: dts: qcom: hamoa: Add UFS nodes for x1e80100 SoC
From: Pradeep Pragallapati @ 2026-01-06 13:00 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, martin.petersen,
andersson, konradybcio, taniya.das, dmitry.baryshkov,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
nitin.rawat, Konrad Dybcio, Abel Vesa
In-Reply-To: <7gi7sh5psh5v4y5mrbgln6j2cjeu5mogdw2n3a6znjtqyjcyuk@kxpe566v57p3>
On 1/6/2026 1:36 PM, Manivannan Sadhasivam wrote:
> On Mon, Jan 05, 2026 at 08:16:42PM +0530, Pradeep P V K wrote:
>> Add UFS host controller and PHY nodes for x1e80100 SoC.
>>
>
> Minor nits below. With those fixed,
>
> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
>
>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
>> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
>> Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/hamoa.dtsi | 123 +++++++++++++++++++++++++++-
>> 1 file changed, 120 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
>> index f7d71793bc77..33899fa06aa4 100644
>> --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
>> @@ -835,9 +835,9 @@ gcc: clock-controller@100000 {
>> <0>,
>> <0>,
>> <0>,
>> - <0>,
>> - <0>,
>> - <0>;
>> + <&ufs_mem_phy 0>,
>> + <&ufs_mem_phy 1>,
>> + <&ufs_mem_phy 2>;
>>
>> power-domains = <&rpmhpd RPMHPD_CX>;
>> #clock-cells = <1>;
>> @@ -3848,6 +3848,123 @@ pcie4_phy: phy@1c0e000 {
>> status = "disabled";
>> };
>>
>> + ufs_mem_phy: phy@1d80000 {
>> + compatible = "qcom,x1e80100-qmp-ufs-phy",
>> + "qcom,sm8550-qmp-ufs-phy";
>> + reg = <0x0 0x01d80000 0x0 0x2000>;
>> +
>> + clocks = <&rpmhcc RPMH_CXO_CLK>,
>> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
>> + <&tcsr TCSR_UFS_PHY_CLKREF_EN>;
>> +
>> + clock-names = "ref",
>> + "ref_aux",
>> + "qref";
>> + resets = <&ufs_mem_hc 0>;
>> + reset-names = "ufsphy";
>> +
>> + power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>;
>> +
>> + #clock-cells = <1>;
>> + #phy-cells = <0>;
>> +
>> + status = "disabled";
>> + };
>> +
>> + ufs_mem_hc: ufs@1d84000 {
>
> ufshc@
ok, i will update in the next patchset.
>
>> + compatible = "qcom,x1e80100-ufshc",
>> + "qcom,sm8550-ufshc",
>> + "qcom,ufshc",
>> + "jedec,ufs-2.0";
>
> Drop jedec compatible as Qcom UFS controller cannot fallback to generic ufshc
> driver.
"jedec,ufs-2.0" was set to const in dt-bindings, dropping now will lead
to dtbs_check failures. is it ok, if i continue with it ?
>
> - Mani
>
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* Re: [PATCH] dt-bindings: phy: ti,control-phy-otghs: convert to DT schema
From: Charan Pedumuru @ 2026-01-06 12:23 UTC (permalink / raw)
To: Rob Herring
Cc: Vinod Koul, Neil Armstrong, Krzysztof Kozlowski, Conor Dooley,
linux-phy, devicetree, linux-kernel
In-Reply-To: <20260105220859.GA3498531-robh@kernel.org>
On 06-01-2026 03:38, Rob Herring wrote:
> On Sat, Jan 03, 2026 at 11:06:10AM +0000, Charan Pedumuru wrote:
>> Convert TI OMAP Control PHY and PIPE3 PHY binding to YAML format.
>> Changes during conversion:
>> - Define a new pattern 'pciephy'and 'control-phy' to match nodes
>> defined in DT.
>>
>> Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
>> ---
>> .../bindings/phy/ti,control-phy-otghs.yaml | 206 +++++++++++++++++++++
>> Documentation/devicetree/bindings/phy/ti-phy.txt | 98 ----------
>> 2 files changed, 206 insertions(+), 98 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/ti,control-phy-otghs.yaml b/Documentation/devicetree/bindings/phy/ti,control-phy-otghs.yaml
>> new file mode 100644
>> index 000000000000..830be2af5fb6
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/ti,control-phy-otghs.yaml
>> @@ -0,0 +1,206 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/phy/ti,control-phy-otghs.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: TI PHYs for TI Platforms (OMAP Control PHY and PIPE3 PHY)
>> +
>> +maintainers:
>> + - Vinod Koul <vkoul@kernel.org>
>
> No, this should be a TI person or someone with the h/w.
Okay, I will look into it.
>
>> +
>> +description:
>> + This device tree binding describes the TI PHYs used in TI platforms.
>> + Two types of PHYs are supported.
>> + 1. OMAP Control PHY - Simple control PHYs for power control
>> + 2. PIPE3 PHY - High-speed PIPE3 PHYs for USB3, SATA, PCIe
>> +
>> +properties:
>> + $nodename:
>> + pattern: "^(pciephy|control-phy|usb3phy|phy)(@[0-9a-fA-F]+)?$"
>
> Only phy, pcie-phy, or usb3-phy are valid node names.
Yeah, but control-phy was defined in DTS, so included it here.
>
> A-F is not valid for unit-addresses either.
Sure, I will remove it.
>
>> +
>> + compatible:
>> + oneOf:
>> + - description: OMAP Control PHY compatibles
>> + items:
>> + enum:
>> + - ti,control-phy-otghs
>> + - ti,control-phy-usb2
>> + - ti,control-phy-pipe3
>> + - ti,control-phy-pcie
>> + - ti,control-phy-usb2-dra7
>> + - ti,control-phy-usb2-am437
>> + - description: PIPE3 high-speed PHY compatibles
>> + items:
>> + enum:
>> + - ti,phy-usb3
>> + - ti,phy-pipe3-sata
>> + - ti,phy-pipe3-pcie
>> + - ti,omap-usb3
>
> IMO, these 2 bindings are completely unrelated and should be split to 2
> schema files.
Okay, I will create 2 bindings in 2 separate patches then.
>
>> +
>> + reg:
>> + minItems: 1
>> + maxItems: 4
>> +
>> + reg-names:
>> + oneOf:
>> + - description: OMAP Control PHY
>> + items:
>> + enum: [otghs_control, power, pcie_pcs, control_sma]
>> + - description: PIPE3 high-speed PHY
>> + items:
>> + enum: [phy_rx, phy_tx, pll_ctrl]
>
> Here's one example why.
>
>> +
>> + "#phy-cells":
>> + const: 0
>> +
>> + clocks:
>> + minItems: 2
>> + maxItems: 7
>> +
>> + clock-names:
>> + minItems: 2
>> + maxItems: 7
>> + items:
>> + enum: [wkupclk, sysclk, refclk, dpll_ref,
>> + dpll_ref_m2, phy-div, div-clk]
>> +
>> +# Optional Properties
>> + id:
>> + description:
>> + Instance ID for multiple instances of same PHY type.
>> + Used for multi-lane PCIe PHYs.
>> + $ref: /schemas/types.yaml#/definitions/uint32
>> + default: 1
>
> There aren't any users of this that I see. Drop it (and note that in the
> commit msg).
Sure.
>
>> +
>> + syscon-phy-power:
>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>> + description:
>> + Phandle/offset pair to system control module register for PHY
>> + power on/off.
>> +
>> + syscon-pllreset:
>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>> + description:
>> + Phandle/offset pair to CTRL_CORE_SMA_SW_0 register containing
>> + SATA_PLL_SOFT_RESET bit (SATA PHY only).
>> +
>> + syscon-pcs:
>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>> + description:
>> + Phandle/offset pair to system control module for writing PCS delay value.
>> +
>> + ctrl-module:
>> + $ref: /schemas/types.yaml#/definitions/phandle
>> + description:
>> + Phandle of control module for PHY power on.
>> + deprecated: true
>
> I believe all these phandle props only apply to the PIPE3 binding.
Yes, I will add them to PIPE3 binding seperately.
>
> Rob
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Best Regards,
Charan.
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* Re: [PATCH v7 0/7] Add ASPEED PCIe Root Complex support
From: Mikhail Rudenko @ 2026-01-06 9:58 UTC (permalink / raw)
To: Jacky Chou
Cc: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery,
Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Linus Walleij, Philipp Zabel,
Neil Armstrong, linux-aspeed, linux-pci, linux-phy, devicetree,
linux-arm-kernel, linux-kernel, Andrew Jeffery, openbmc,
linux-gpio, Mikhail Rudenko
In-Reply-To: <20251216-upstream_pcie_rc-v7-0-4aeb0f53c4ce@aspeedtech.com>
Hi Jacky,
On 2025-12-16 at 09:49 +08, Jacky Chou <jacky_chou@aspeedtech.com> wrote:
> This patch series adds support for the ASPEED PCIe Root Complex,
> including device tree bindings, pinctrl support, and the PCIe host controller
> driver. The patches introduce the necessary device tree nodes, pinmux groups,
> and driver implementation to enable PCIe functionality on ASPEED platforms.
> Currently, the ASPEED PCIe Root Complex only supports a single port.
>
> Summary of changes:
> - Add device tree binding documents for ASPEED PCIe PHY and PCIe RC
> - Update MAINTAINERS for new bindings and driver
> - Implement ASPEED PCIe PHY driver
> - Implement ASPEED PCIe Root Complex host controller driver
>
> This series has been tested on AST2600/AST2700 platforms and enables PCIe device
> enumeration and operation.
First of all, thank you for your efforts in getting this driver
upstreamed! I am trying to understand whether this driver supports
PCIe devices that have an I/O port BAR, where CPU access to I/O ports
is required for proper device operation.
If I understand correctly, this line in the Aspeed 2600 dtsi file
declares the I/O port range:
ranges = <0x01000000 0x0 0x00018000 0x00018000 0x0 0x00008000
During system initialization, the pci_remap_iospace() function in
arch/arm/mm/ioremap.c maps the physical address range
0x00018000-0x00020000 to the virtual address PCI_IO_VIRT_BASE
(0xfee00000). After this mapping, inb() and outb() calls work by
converting I/O port addresses to virtual addresses starting at
PCI_IO_VIRT_BASE, then performing reads and writes to those virtual
addresses.
What I don't understand is this: according to the Aspeed 2600
datasheet, the address range 0x00000000-0x0fffffff (which contains
0x00018000-0x00020000) is mapped to Firmware SPI Memory. This would
mean that outb() operations get routed to memory-mapped SPI flash
instead of PCIe.
It seems like there's a missing piece to this puzzle. Could you help
clarify how this is supposed to work?
--
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* Re: [PATCH V3 3/4] arm64: dts: qcom: hamoa: Add UFS nodes for x1e80100 SoC
From: Manivannan Sadhasivam @ 2026-01-06 8:06 UTC (permalink / raw)
To: Pradeep P V K
Cc: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, martin.petersen,
andersson, konradybcio, taniya.das, dmitry.baryshkov,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
nitin.rawat, Konrad Dybcio, Abel Vesa
In-Reply-To: <20260105144643.669344-4-pradeep.pragallapati@oss.qualcomm.com>
On Mon, Jan 05, 2026 at 08:16:42PM +0530, Pradeep P V K wrote:
> Add UFS host controller and PHY nodes for x1e80100 SoC.
>
Minor nits below. With those fixed,
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
> Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/hamoa.dtsi | 123 +++++++++++++++++++++++++++-
> 1 file changed, 120 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
> index f7d71793bc77..33899fa06aa4 100644
> --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
> +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
> @@ -835,9 +835,9 @@ gcc: clock-controller@100000 {
> <0>,
> <0>,
> <0>,
> - <0>,
> - <0>,
> - <0>;
> + <&ufs_mem_phy 0>,
> + <&ufs_mem_phy 1>,
> + <&ufs_mem_phy 2>;
>
> power-domains = <&rpmhpd RPMHPD_CX>;
> #clock-cells = <1>;
> @@ -3848,6 +3848,123 @@ pcie4_phy: phy@1c0e000 {
> status = "disabled";
> };
>
> + ufs_mem_phy: phy@1d80000 {
> + compatible = "qcom,x1e80100-qmp-ufs-phy",
> + "qcom,sm8550-qmp-ufs-phy";
> + reg = <0x0 0x01d80000 0x0 0x2000>;
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
> + <&tcsr TCSR_UFS_PHY_CLKREF_EN>;
> +
> + clock-names = "ref",
> + "ref_aux",
> + "qref";
> + resets = <&ufs_mem_hc 0>;
> + reset-names = "ufsphy";
> +
> + power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>;
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> + ufs_mem_hc: ufs@1d84000 {
ufshc@
> + compatible = "qcom,x1e80100-ufshc",
> + "qcom,sm8550-ufshc",
> + "qcom,ufshc",
> + "jedec,ufs-2.0";
Drop jedec compatible as Qcom UFS controller cannot fallback to generic ufshc
driver.
- Mani
--
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^ permalink raw reply
* Re: [PATCH V3 2/4] dt-bindings: ufs: qcom,sc7180-ufshc: Add UFSHC compatible for x1e80100
From: Manivannan Sadhasivam @ 2026-01-06 8:03 UTC (permalink / raw)
To: Pradeep P V K
Cc: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, martin.petersen,
andersson, konradybcio, taniya.das, dmitry.baryshkov,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
nitin.rawat
In-Reply-To: <20260105144643.669344-3-pradeep.pragallapati@oss.qualcomm.com>
On Mon, Jan 05, 2026 at 08:16:41PM +0530, Pradeep P V K wrote:
> Add UFS Host Controller (UFSHC) compatible for x1e80100 SoC. Use
> SM8550 as a fallback since x1e80100 is fully compatible with it.
>
> Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
- Mani
> ---
> .../bindings/ufs/qcom,sc7180-ufshc.yaml | 37 +++++++++++--------
> 1 file changed, 22 insertions(+), 15 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml b/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml
> index d94ef4e6b85a..c1085d178421 100644
> --- a/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml
> +++ b/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml
> @@ -31,21 +31,28 @@ select:
>
> properties:
> compatible:
> - items:
> - - enum:
> - - qcom,msm8998-ufshc
> - - qcom,qcs8300-ufshc
> - - qcom,sa8775p-ufshc
> - - qcom,sc7180-ufshc
> - - qcom,sc7280-ufshc
> - - qcom,sc8180x-ufshc
> - - qcom,sc8280xp-ufshc
> - - qcom,sm8250-ufshc
> - - qcom,sm8350-ufshc
> - - qcom,sm8450-ufshc
> - - qcom,sm8550-ufshc
> - - const: qcom,ufshc
> - - const: jedec,ufs-2.0
> + oneOf:
> + - items:
> + - enum:
> + - qcom,x1e80100-ufshc
> + - const: qcom,sm8550-ufshc
> + - const: qcom,ufshc
> + - const: jedec,ufs-2.0
> + - items:
> + - enum:
> + - qcom,msm8998-ufshc
> + - qcom,qcs8300-ufshc
> + - qcom,sa8775p-ufshc
> + - qcom,sc7180-ufshc
> + - qcom,sc7280-ufshc
> + - qcom,sc8180x-ufshc
> + - qcom,sc8280xp-ufshc
> + - qcom,sm8250-ufshc
> + - qcom,sm8350-ufshc
> + - qcom,sm8450-ufshc
> + - qcom,sm8550-ufshc
> + - const: qcom,ufshc
> + - const: jedec,ufs-2.0
>
> reg:
> maxItems: 1
> --
> 2.34.1
>
--
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^ permalink raw reply
* Re: [PATCH V3 2/4] dt-bindings: ufs: qcom,sc7180-ufshc: Add UFSHC compatible for x1e80100
From: Krzysztof Kozlowski @ 2026-01-06 7:34 UTC (permalink / raw)
To: Pradeep P V K
Cc: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, martin.petersen,
andersson, konradybcio, taniya.das, dmitry.baryshkov,
manivannan.sadhasivam, linux-arm-msm, linux-phy, devicetree,
linux-kernel, linux-scsi, nitin.rawat
In-Reply-To: <20260105144643.669344-3-pradeep.pragallapati@oss.qualcomm.com>
On Mon, Jan 05, 2026 at 08:16:41PM +0530, Pradeep P V K wrote:
> Add UFS Host Controller (UFSHC) compatible for x1e80100 SoC. Use
> SM8550 as a fallback since x1e80100 is fully compatible with it.
>
> Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
> ---
> .../bindings/ufs/qcom,sc7180-ufshc.yaml | 37 +++++++++++--------
> 1 file changed, 22 insertions(+), 15 deletions(-)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH V3 1/4] dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Add QMP UFS PHY compatible
From: Krzysztof Kozlowski @ 2026-01-06 7:32 UTC (permalink / raw)
To: Pradeep P V K
Cc: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, martin.petersen,
andersson, konradybcio, taniya.das, dmitry.baryshkov,
manivannan.sadhasivam, linux-arm-msm, linux-phy, devicetree,
linux-kernel, linux-scsi, nitin.rawat
In-Reply-To: <20260105144643.669344-2-pradeep.pragallapati@oss.qualcomm.com>
On Mon, Jan 05, 2026 at 08:16:40PM +0530, Pradeep P V K wrote:
> Document QMP UFS PHY compatible for x1e80100 SoC. Use SM8550 as a
> fallback since x1e80100 is fully compatible with it.
>
> Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
> ---
> .../devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
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* [PATCH v7 2/2] phy: eswin: Create eswin directory and add EIC7700 SATA PHY driver
From: Yulin Lu @ 2026-01-06 6:33 UTC (permalink / raw)
To: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, p.zabel,
linux-phy, devicetree, linux-kernel
Cc: ningyu, zhengyu, linmin, huangyifeng, fenglin, lianghujun,
Yulin Lu
In-Reply-To: <20260106062944.1529-1-luyulin@eswincomputing.com>
Created the eswin phy driver directory and added support for
the SATA phy driver on the EIC7700 SoC platform.
Signed-off-by: Yulin Lu <luyulin@eswincomputing.com>
---
drivers/phy/Kconfig | 1 +
drivers/phy/Makefile | 1 +
drivers/phy/eswin/Kconfig | 14 ++
drivers/phy/eswin/Makefile | 2 +
drivers/phy/eswin/phy-eic7700-sata.c | 221 +++++++++++++++++++++++++++
5 files changed, 239 insertions(+)
create mode 100644 drivers/phy/eswin/Kconfig
create mode 100644 drivers/phy/eswin/Makefile
create mode 100644 drivers/phy/eswin/phy-eic7700-sata.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 678dd0452f0a..6d50704917f0 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -105,6 +105,7 @@ source "drivers/phy/allwinner/Kconfig"
source "drivers/phy/amlogic/Kconfig"
source "drivers/phy/broadcom/Kconfig"
source "drivers/phy/cadence/Kconfig"
+source "drivers/phy/eswin/Kconfig"
source "drivers/phy/freescale/Kconfig"
source "drivers/phy/hisilicon/Kconfig"
source "drivers/phy/ingenic/Kconfig"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index bfb27fb5a494..482a143d3417 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -17,6 +17,7 @@ obj-y += allwinner/ \
amlogic/ \
broadcom/ \
cadence/ \
+ eswin/ \
freescale/ \
hisilicon/ \
ingenic/ \
diff --git a/drivers/phy/eswin/Kconfig b/drivers/phy/eswin/Kconfig
new file mode 100644
index 000000000000..37447cc3af63
--- /dev/null
+++ b/drivers/phy/eswin/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Phy drivers for ESWIN platforms
+#
+config PHY_EIC7700_SATA
+ tristate "eic7700 Sata SerDes/PHY driver"
+ depends on ARCH_ESWIN || COMPILE_TEST
+ depends on HAS_IOMEM
+ select GENERIC_PHY
+ help
+ Enable this to support SerDes/Phy found on ESWIN's
+ EIC7700 SoC.This Phy supports SATA 1.5 Gb/s,
+ SATA 3.0 Gb/s, SATA 6.0 Gb/s speeds.
+ It supports one SATA host port to accept one SATA device.
diff --git a/drivers/phy/eswin/Makefile b/drivers/phy/eswin/Makefile
new file mode 100644
index 000000000000..db08c66be812
--- /dev/null
+++ b/drivers/phy/eswin/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_PHY_EIC7700_SATA) += phy-eic7700-sata.o
diff --git a/drivers/phy/eswin/phy-eic7700-sata.c b/drivers/phy/eswin/phy-eic7700-sata.c
new file mode 100644
index 000000000000..96ae62a1b637
--- /dev/null
+++ b/drivers/phy/eswin/phy-eic7700-sata.c
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ESWIN SATA PHY driver
+ *
+ * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd..
+ * All rights reserved.
+ *
+ * Authors: Yulin Lu <luyulin@eswincomputing.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+#define SATA_AXI_LP_CTRL 0x08
+#define SATA_MPLL_CTRL 0x20
+#define SATA_P0_PHY_STAT 0x24
+#define SATA_PHY_CTRL0 0x28
+#define SATA_PHY_CTRL1 0x2c
+#define SATA_REF_CTRL 0x34
+#define SATA_REF_CTRL1 0x38
+#define SATA_LOS_IDEN 0x3c
+
+#define SATA_CLK_RST_SOURCE_PHY BIT(0)
+#define SATA_P0_PHY_TX_AMPLITUDE_GEN1_MASK GENMASK(6, 0)
+#define SATA_P0_PHY_TX_AMPLITUDE_GEN2_MASK GENMASK(14, 8)
+#define SATA_P0_PHY_TX_AMPLITUDE_GEN3_MASK GENMASK(22, 16)
+#define SATA_P0_PHY_TX_PREEMPH_GEN1_MASK GENMASK(5, 0)
+#define SATA_P0_PHY_TX_PREEMPH_GEN2_MASK GENMASK(13, 8)
+#define SATA_P0_PHY_TX_PREEMPH_GEN3_MASK GENMASK(21, 16)
+#define SATA_LOS_LEVEL_MASK GENMASK(4, 0)
+#define SATA_LOS_BIAS_MASK GENMASK(18, 16)
+#define SATA_M_CSYSREQ BIT(0)
+#define SATA_S_CSYSREQ BIT(16)
+#define SATA_REF_REPEATCLK_EN BIT(0)
+#define SATA_REF_USE_PAD BIT(20)
+#define SATA_MPLL_MULTIPLIER_MASK GENMASK(22, 16)
+#define SATA_P0_PHY_READY BIT(0)
+
+#define PLL_LOCK_SLEEP_US 10
+#define PLL_LOCK_TIMEOUT_US 1000
+
+struct eic7700_sata_phy {
+ struct reset_control *rst;
+ struct regmap *regmap;
+ struct clk *clk;
+ struct phy *phy;
+};
+
+static const struct regmap_config eic7700_sata_phy_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = SATA_LOS_IDEN,
+};
+
+static int wait_for_phy_ready(struct regmap *regmap, u32 reg, u32 checkbit,
+ u32 status)
+{
+ u32 val;
+ int ret;
+
+ ret = regmap_read_poll_timeout(regmap, reg, val,
+ (val & checkbit) == status,
+ PLL_LOCK_SLEEP_US, PLL_LOCK_TIMEOUT_US);
+
+ return ret;
+}
+
+static int eic7700_sata_phy_init(struct phy *phy)
+{
+ struct eic7700_sata_phy *sata_phy = phy_get_drvdata(phy);
+ u32 val;
+ int ret;
+
+ ret = clk_prepare_enable(sata_phy->clk);
+ if (ret)
+ return ret;
+
+ regmap_write(sata_phy->regmap, SATA_REF_CTRL1, SATA_CLK_RST_SOURCE_PHY);
+
+ val = FIELD_PREP(SATA_P0_PHY_TX_AMPLITUDE_GEN1_MASK, 0x42) |
+ FIELD_PREP(SATA_P0_PHY_TX_AMPLITUDE_GEN2_MASK, 0x46) |
+ FIELD_PREP(SATA_P0_PHY_TX_AMPLITUDE_GEN3_MASK, 0x73);
+ regmap_write(sata_phy->regmap, SATA_PHY_CTRL0, val);
+
+ val = FIELD_PREP(SATA_P0_PHY_TX_PREEMPH_GEN1_MASK, 0x5) |
+ FIELD_PREP(SATA_P0_PHY_TX_PREEMPH_GEN2_MASK, 0x5) |
+ FIELD_PREP(SATA_P0_PHY_TX_PREEMPH_GEN3_MASK, 0x8);
+ regmap_write(sata_phy->regmap, SATA_PHY_CTRL1, val);
+
+ val = FIELD_PREP(SATA_LOS_LEVEL_MASK, 0x9) |
+ FIELD_PREP(SATA_LOS_BIAS_MASK, 0x2);
+ regmap_write(sata_phy->regmap, SATA_LOS_IDEN, val);
+
+ val = SATA_M_CSYSREQ | SATA_S_CSYSREQ;
+ regmap_write(sata_phy->regmap, SATA_AXI_LP_CTRL, val);
+
+ val = SATA_REF_REPEATCLK_EN | SATA_REF_USE_PAD;
+ regmap_write(sata_phy->regmap, SATA_REF_CTRL, val);
+
+ val = FIELD_PREP(SATA_MPLL_MULTIPLIER_MASK, 0x3c);
+ regmap_write(sata_phy->regmap, SATA_MPLL_CTRL, val);
+
+ usleep_range(15, 20);
+
+ ret = reset_control_deassert(sata_phy->rst);
+ if (ret)
+ goto disable_clk;
+
+ ret = wait_for_phy_ready(sata_phy->regmap, SATA_P0_PHY_STAT,
+ SATA_P0_PHY_READY, 1);
+ if (ret < 0) {
+ dev_err(&sata_phy->phy->dev, "PHY READY check failed\n");
+ goto disable_clk;
+ }
+
+ return 0;
+
+disable_clk:
+ clk_disable_unprepare(sata_phy->clk);
+ return ret;
+}
+
+static int eic7700_sata_phy_exit(struct phy *phy)
+{
+ struct eic7700_sata_phy *sata_phy = phy_get_drvdata(phy);
+ int ret;
+
+ ret = reset_control_assert(sata_phy->rst);
+ if (ret)
+ return ret;
+
+ clk_disable_unprepare(sata_phy->clk);
+
+ return 0;
+}
+
+static const struct phy_ops eic7700_sata_phy_ops = {
+ .init = eic7700_sata_phy_init,
+ .exit = eic7700_sata_phy_exit,
+ .owner = THIS_MODULE,
+};
+
+static int eic7700_sata_phy_probe(struct platform_device *pdev)
+{
+ struct eic7700_sata_phy *sata_phy;
+ struct phy_provider *phy_provider;
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ void __iomem *regs;
+
+ sata_phy = devm_kzalloc(dev, sizeof(*sata_phy), GFP_KERNEL);
+ if (!sata_phy)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -ENOENT;
+
+ regs = devm_ioremap(dev, res->start, resource_size(res));
+ if (IS_ERR(regs))
+ return PTR_ERR(regs);
+
+ sata_phy->regmap = devm_regmap_init_mmio
+ (dev, regs, &eic7700_sata_phy_regmap_config);
+ if (IS_ERR(sata_phy->regmap))
+ return dev_err_probe(dev, PTR_ERR(sata_phy->regmap),
+ "failed to init regmap\n");
+
+ dev_set_drvdata(dev, sata_phy);
+
+ sata_phy->clk = devm_clk_get(dev, "phy");
+ if (IS_ERR(sata_phy->clk))
+ return PTR_ERR(sata_phy->clk);
+
+ sata_phy->rst = devm_reset_control_array_get_exclusive(dev);
+ if (IS_ERR(sata_phy->rst))
+ return dev_err_probe(dev, PTR_ERR(sata_phy->rst),
+ "failed to get reset control\n");
+
+ sata_phy->phy = devm_phy_create(dev, NULL, &eic7700_sata_phy_ops);
+ if (IS_ERR(sata_phy->phy))
+ return dev_err_probe(dev, PTR_ERR(sata_phy->phy),
+ "failed to create PHY\n");
+
+ phy_set_drvdata(sata_phy->phy, sata_phy);
+
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+ if (IS_ERR(phy_provider))
+ return dev_err_probe(dev, PTR_ERR(phy_provider),
+ "failed to register PHY provider\n");
+
+ return 0;
+}
+
+static const struct of_device_id eic7700_sata_phy_of_match[] = {
+ { .compatible = "eswin,eic7700-sata-phy" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, eic7700_sata_phy_of_match);
+
+static struct platform_driver eic7700_sata_phy_driver = {
+ .probe = eic7700_sata_phy_probe,
+ .driver = {
+ .of_match_table = eic7700_sata_phy_of_match,
+ .name = "eic7700-sata-phy",
+ }
+};
+module_platform_driver(eic7700_sata_phy_driver);
+
+MODULE_DESCRIPTION("SATA PHY driver for the ESWIN EIC7700 SoC");
+MODULE_AUTHOR("Yulin Lu <luyulin@eswincomputing.com>");
+MODULE_LICENSE("GPL");
--
2.25.1
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^ permalink raw reply related
* [PATCH v7 1/2] dt-bindings: phy: eswin: Document the EIC7700 SoC SATA PHY
From: Yulin Lu @ 2026-01-06 6:31 UTC (permalink / raw)
To: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, p.zabel,
linux-phy, devicetree, linux-kernel
Cc: ningyu, zhengyu, linmin, huangyifeng, fenglin, lianghujun,
Yulin Lu, Krzysztof Kozlowski
In-Reply-To: <20260106062944.1529-1-luyulin@eswincomputing.com>
Document the SATA PHY on the EIC7700 SoC platform,
describing its usage.
Signed-off-by: Yulin Lu <luyulin@eswincomputing.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../bindings/phy/eswin,eic7700-sata-phy.yaml | 58 +++++++++++++++++++
1 file changed, 58 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/eswin,eic7700-sata-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/eswin,eic7700-sata-phy.yaml b/Documentation/devicetree/bindings/phy/eswin,eic7700-sata-phy.yaml
new file mode 100644
index 000000000000..1b3f8e114ac7
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/eswin,eic7700-sata-phy.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/eswin,eic7700-sata-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Eswin EIC7700 SoC SATA PHY
+
+maintainers:
+ - Yulin Lu <luyulin@eswincomputing.com>
+ - Huan He <hehuan1@eswincomputing.com>
+
+properties:
+ compatible:
+ const: eswin,eic7700-sata-phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: phy
+
+ resets:
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: port
+ - const: phy
+
+ "#phy-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ sata-phy@50440300 {
+ compatible = "eswin,eic7700-sata-phy";
+ reg = <0x50440300 0x40>;
+ clocks = <&hspcrg 17>;
+ clock-names = "phy";
+ resets = <&hspcrg 0>, <&hspcrg 1>;
+ reset-names = "port", "phy";
+ #phy-cells = <0>;
+ };
--
2.25.1
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^ permalink raw reply related
* [PATCH v7 0/2] Add driver support for Eswin EIC7700 SoC SATA PHY
From: Yulin Lu @ 2026-01-06 6:29 UTC (permalink / raw)
To: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, p.zabel,
linux-phy, devicetree, linux-kernel
Cc: ningyu, zhengyu, linmin, huangyifeng, fenglin, lianghujun,
Yulin Lu
Updates:
v7 -> v6:
- phy-eic7700-sata.c
- Rename PHY_READY_TIMEOUT to PLL_LOCK_TIMEOUT_US with value 1000.
- Add macro PLL_LOCK_SLEEP_US set to 10.
- Add "goto disable_clk" in the eic7700_sata_phy_init function.
- Modify Copyright year from 2024 to 2026.
- Link to v6: https://lore.kernel.org/lkml/20251201060737.868-1-luyulin@eswincomputing.com/
v6 -> v5:
- eswin,eic7700-ahci.yaml
- Delete this file and it has already been applied in reply[1].
- eswin,eic7700-sata-phy.yaml
- Add clock and reset related properties.
- phy-eic7700-sata.c
- Map the io resource with platform_get_resource and devm_ioremap instead of
devm_platform_ioremap_resource API. Because the address region of sata-phy falls
into the region of hsp clock&reset which has been got by hsp clock&reset driver.
- Use regmap_read_poll_timeout in wait_for_phy_ready to replace the while loop check.
- Use devm_regmap_init_mmio and regmap_write to replace writel.
- Adapt to the clock and reset driver framework, replacing the original readl and writel.
Because we are implementing the HSP layer clock and reset drivers, the corresponding
clock and reset registers can be registered into the driver framework. And I have tested
on the Sifive HiFive Premier P550 board.
- Link to v5: https://lore.kernel.org/lkml/20250930083754.15-1-luyulin@eswincomputing.com/
v5 -> v4:
- eswin,eic7700-ahci.yaml
- Add "dt-bindings: ata:" prefix to the subject.
- Wrap at 80 characters in the YAML description field.
- Link to v4: https://lore.kernel.org/lkml/20250915125902.375-1-luyulin@eswincomputing.com/
v4 -> v3:
- eswin,eic7700-ahci.yaml
- Fix grammatical errors in patch subject and commit message
- Add an explanation in the commit message of patch 1 for retaining the
"ports-implemented" field, which Rob Herring suggested to remove
in the review comments on v2.
Link to Rob Herring's review:
https://lore.kernel.org/lkml/CAL_JsqKFotNLZZXwiy7S6K8qXLdGRAnsa-1zvZRDQBE39Gf5kg@mail.gmail.com/
Link to my question and Niklas Cassel's reply:
https://lore.kernel.org/lkml/aLBUC116MdJqDGIJ@flawful.org/
In this reply, Niklas Cassel mentioned his view:
If the ports-implemented register gets reset from
ahci_platform_assert_rsts(), then it seems acceptable to
retain the ports-implemented property in the device tree.
This aligns with our design.
Link to my reply:
https://lore.kernel.org/lkml/4ab70c6a.8be.198f47da494.Coremail.luyulin@eswincomputing.com/
Link to Niklas Cassel's question and my further explanation:
https://lore.kernel.org/lkml/aLlYkZWBaI5Yz6fo@ryzen/
https://lore.kernel.org/lkml/7206383a.d98.19918c22570.Coremail.luyulin@eswincomputing.com/
- eswin,eic7700-sata-phy.yaml
- Fix grammatical errors in patch subject and commit message
- Adjust the position of reg in the properties and required arrays
- Add reviewed-by tag of Krzysztof Kozlowski
- phy-eic7700-sata.c
- Correct the loop condition in wait_for_phy_ready() to use the current
jiffies instead of the fixed start time
- Change the return value from -EFAULT to -ETIMEDOUT to correctly
indicate a timeout condition
- Remove redundant clock disable handling in probe error path, as
SATA_SYS_CLK_EN is managed in phy_init() and phy_exit()
- Use dev_err_probe return in probe
- Reorder local variables to follow reverse Xmas tree order
- Wrap each line in the extended comments to 80 columns before splitting lines
- Adjust the position of `#include <linux/io.h>` for proper ordering
- Link to v3: https://lore.kernel.org/lkml/20250904063427.1954-1-luyulin@eswincomputing.com/
v2 -> v3:
- Use full name in "From" and "Signed-off-by" fields information
- eswin,eic7700-ahci.yaml
- Remove the introduction to the reg, interrupts, phys, and phy-names fields
- Modify the usage of the clocks field in the examples
- Correct the order of dt properties
- phy-eic7700-sata.c
- Register operations use the GENMASK macro and FIELD_PREP instead of
the original bit offset method, and add "#include <linux/bitfield.h>"
- Modify some macro definition names.
- Remove the redundant initialization assignments for "ret" and "val"
- Delete ".suppress_bind_attrs = true"
- Modify the driver name
- Add "#include <linux/io.h>" to fix the robot test issue
- Link to v2: https://lore.kernel.org/lkml/20250819134722.220-1-luyulin@eswincomputing.com/
v2 -> v1:
- Delete the original controller driver and use ahci_dwc.c instead
- Add eswin,eic7700-ahci.yaml
- Correct the descriptions of reset, interrupt and other
hardware resources for the sata controller on EIC7700 SoC
- The clocks for both sata controller and sata PHY are controlled
via a register bit in the HSP bus and are not registered in the
clock tree. Clock are managed within the PHY driver, therefore
it is not described in this document
- Add $ref: snps,dwc-ahci-common.yaml#.
- Add eswin,eic7700-sata-phy.yaml
- Add this file to include the description of the PHY on EIC7700 SoC
- Add an eswin directory under the PHY driver path, and include the SATA
PHY driver code for EIC7700 SoC
- Link to v1: https://lore.kernel.org/all/20250515085114.1692-1-hehuan1@eswincomputing.com/
Yulin Lu (2):
dt-bindings: phy: eswin: Document the EIC7700 SoC SATA PHY
phy: eswin: Create eswin directory and add EIC7700 SATA PHY driver
.../bindings/phy/eswin,eic7700-sata-phy.yaml | 58 +++++
drivers/phy/Kconfig | 1 +
drivers/phy/Makefile | 1 +
drivers/phy/eswin/Kconfig | 14 ++
drivers/phy/eswin/Makefile | 2 +
drivers/phy/eswin/phy-eic7700-sata.c | 221 ++++++++++++++++++
6 files changed, 297 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/eswin,eic7700-sata-phy.yaml
create mode 100644 drivers/phy/eswin/Kconfig
create mode 100644 drivers/phy/eswin/Makefile
create mode 100644 drivers/phy/eswin/phy-eic7700-sata.c
--
2.25.1
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^ permalink raw reply
* Re: [PATCH v2 2/4] dt-bindings: phy: qcom,m31-eusb2-phy: Document M31 eUSB2 PHY for Kaanapali
From: Krishna Kurapati @ 2026-01-06 5:09 UTC (permalink / raw)
To: Krzysztof Kozlowski, Jingyi Wang
Cc: aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang, linux-arm-msm,
linux-phy, devicetree, linux-kernel, linux-usb, Ronak Raheja,
Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Wesley Cheng,
Greg Kroah-Hartman
In-Reply-To: <41f71be9-595f-4a81-b089-27bdcc778c8a@kernel.org>
On 10/23/2025 9:09 PM, Krzysztof Kozlowski wrote:
> On 22/10/2025 08:50, Jingyi Wang wrote:
>> From: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
>>
>> Document M31 eUSB2 PHY for Kaanapali which handles the USB2 path. Use
>> fallback to indicate the compatibility of the M31 eUSB2 PHY on the
>> Kaanapali with that on the SM8750.
>>
>> Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
>> Co-developed-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>> ---
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
Hi Krzysztof,
Thanks for the RB.
I was about to rebase this series (phy binding patches).
And wanted to send the following after fixing conflicts (as glymur got
merged):
diff --git
a/Documentation/devicetree/bindings/phy/qcom,m31-eusb2-phy.yaml
b/Documentation/devicetree/bindings/phy/qcom,m31-eusb2-phy.yaml
index 409803874c97..cd6b84213a7c 100644
--- a/Documentation/devicetree/bindings/phy/qcom,m31-eusb2-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,m31-eusb2-phy.yaml
@@ -19,6 +19,7 @@ properties:
- items:
- enum:
- qcom,glymur-m31-eusb2-phy
+ - qcom,kaanapali-m31-eusb2-phy
- const: qcom,sm8750-m31-eusb2-phy
- const: qcom,sm8750-m31-eusb2-phy
Can I still retain your RB tag ?
Regards,
Krishna,
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^ permalink raw reply related
* Re: [PATCH] phy: socionext: usb2: Simplify with scoped for each OF child loop
From: Kunihiko Hayashi @ 2026-01-06 4:45 UTC (permalink / raw)
To: Krzysztof Kozlowski, Vinod Koul, Neil Armstrong, Masami Hiramatsu
Cc: linux-phy, linux-arm-kernel, linux-kernel
In-Reply-To: <20260102124848.64474-2-krzysztof.kozlowski@oss.qualcomm.com>
Hi Krzysztof,
On 2026/01/02 21:48, Krzysztof Kozlowski wrote:
> Use scoped for-each loop when iterating over device nodes to make code a
> bit simpler.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
> ---
> drivers/phy/socionext/phy-uniphier-usb2.c | 28 ++++++++---------------
> 1 file changed, 10 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/phy/socionext/phy-uniphier-usb2.c
> b/drivers/phy/socionext/phy-uniphier-usb2.c
> index 21c201717d95..c49d432e526b 100644
> --- a/drivers/phy/socionext/phy-uniphier-usb2.c
> +++ b/drivers/phy/socionext/phy-uniphier-usb2.c
> @@ -106,7 +106,7 @@ static const struct phy_ops uniphier_u2phy_ops = {
> static int uniphier_u2phy_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> - struct device_node *parent, *child;
> + struct device_node *parent;
> struct uniphier_u2phy_priv *priv = NULL, *next = NULL;
> struct phy_provider *phy_provider;
> struct regmap *regmap;
> @@ -129,34 +129,31 @@ static int uniphier_u2phy_probe(struct
> platform_device *pdev)
> return PTR_ERR(regmap);
> }
>
> - for_each_child_of_node(dev->of_node, child) {
> + for_each_child_of_node_scoped(dev->of_node, child) {
> priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> - if (!priv) {
> - ret = -ENOMEM;
> - goto out_put_child;
> - }
> + if (!priv)
> + return -ENOMEM;
> +
> priv->regmap = regmap;
>
> priv->vbus = devm_regulator_get_optional(dev, "vbus");
> if (IS_ERR(priv->vbus)) {
> - if (PTR_ERR(priv->vbus) == -EPROBE_DEFER) {
> - ret = PTR_ERR(priv->vbus);
> - goto out_put_child;
> - }
> + if (PTR_ERR(priv->vbus) == -EPROBE_DEFER)
> + return PTR_ERR(priv->vbus);
> +
> priv->vbus = NULL;
> }
>
> priv->phy = devm_phy_create(dev, child,
> &uniphier_u2phy_ops);
> if (IS_ERR(priv->phy)) {
> dev_err(dev, "Failed to create phy\n");
> - ret = PTR_ERR(priv->phy);
> - goto out_put_child;
> + return PTR_ERR(priv->phy);
> }
>
> ret = of_property_read_u32(child, "reg", &data_idx);
> if (ret) {
> dev_err(dev, "Failed to get reg property\n");
> - goto out_put_child;
> + return ret;
> }
>
> if (data_idx < ndatas)
> @@ -174,11 +171,6 @@ static int uniphier_u2phy_probe(struct
> platform_device *pdev)
> phy_provider = devm_of_phy_provider_register(dev,
>
> uniphier_u2phy_xlate);
> return PTR_ERR_OR_ZERO(phy_provider);
> -
> -out_put_child:
> - of_node_put(child);
> -
> - return ret;
> }
>
> static const struct uniphier_u2phy_soc_data uniphier_pro4_data[] = {
Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Thank you,
---
Best Regards
Kunihiko Hayashi
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^ permalink raw reply
* Re: [PATCH V3 0/4] Add UFS support for x1e80100 SoC
From: Dmitry Baryshkov @ 2026-01-05 22:20 UTC (permalink / raw)
To: Pradeep P V K
Cc: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, martin.petersen,
andersson, konradybcio, taniya.das, manivannan.sadhasivam,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
nitin.rawat
In-Reply-To: <20260105144643.669344-1-pradeep.pragallapati@oss.qualcomm.com>
On Mon, Jan 05, 2026 at 08:16:39PM +0530, Pradeep P V K wrote:
> Add UFSPHY, UFSHC compatible binding names and UFS devicetree
> enablement changes for Qualcomm x1e80100 SoC.
>
> Changes in V3:
> - Update all dt-bindings commit messages with concise and informative
> statements [Krzysztof]
> - keep the QMP UFS PHY order by last compatible in numerical ascending
> order [Krzysztof]
> - Remove qcom,x1e80100-ufshc from select: enum: list of
> qcom,sc7180-ufshc.yaml file [Krzysztof]
> - Update subject prefix for all dt-bindings [Krzysztof]
> - Add RB-by for SoC dtsi [Konrad, Abel, Taniya]
> - Add RB-by for board dts [Konrad]
> - Link to V2:
> https://lore.kernel.org/all/20251231101951.1026163-1-pradeep.pragallapati@oss.qualcomm.com
Where did the previous changelog go?
>
> ---
> Pradeep P V K (4):
> dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Add QMP UFS PHY
> compatible
> dt-bindings: ufs: qcom,sc7180-ufshc: Add UFSHC compatible for x1e80100
> arm64: dts: qcom: hamoa: Add UFS nodes for x1e80100 SoC
> arm64: dts: qcom: hamoa-iot-evk: Enable UFS
>
> .../phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 4 +
> .../bindings/ufs/qcom,sc7180-ufshc.yaml | 37 +++---
> arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 18 +++
> arch/arm64/boot/dts/qcom/hamoa.dtsi | 123 +++++++++++++++++-
> 4 files changed, 164 insertions(+), 18 deletions(-)
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
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^ permalink raw reply
* Re: [PATCH] dt-bindings: phy: ti,control-phy-otghs: convert to DT schema
From: Rob Herring @ 2026-01-05 22:08 UTC (permalink / raw)
To: Charan Pedumuru
Cc: Vinod Koul, Neil Armstrong, Krzysztof Kozlowski, Conor Dooley,
linux-phy, devicetree, linux-kernel
In-Reply-To: <20260103-ti-phy-v1-1-8c3f5e2cbd63@gmail.com>
On Sat, Jan 03, 2026 at 11:06:10AM +0000, Charan Pedumuru wrote:
> Convert TI OMAP Control PHY and PIPE3 PHY binding to YAML format.
> Changes during conversion:
> - Define a new pattern 'pciephy'and 'control-phy' to match nodes
> defined in DT.
>
> Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
> ---
> .../bindings/phy/ti,control-phy-otghs.yaml | 206 +++++++++++++++++++++
> Documentation/devicetree/bindings/phy/ti-phy.txt | 98 ----------
> 2 files changed, 206 insertions(+), 98 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/phy/ti,control-phy-otghs.yaml b/Documentation/devicetree/bindings/phy/ti,control-phy-otghs.yaml
> new file mode 100644
> index 000000000000..830be2af5fb6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/ti,control-phy-otghs.yaml
> @@ -0,0 +1,206 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/ti,control-phy-otghs.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: TI PHYs for TI Platforms (OMAP Control PHY and PIPE3 PHY)
> +
> +maintainers:
> + - Vinod Koul <vkoul@kernel.org>
No, this should be a TI person or someone with the h/w.
> +
> +description:
> + This device tree binding describes the TI PHYs used in TI platforms.
> + Two types of PHYs are supported.
> + 1. OMAP Control PHY - Simple control PHYs for power control
> + 2. PIPE3 PHY - High-speed PIPE3 PHYs for USB3, SATA, PCIe
> +
> +properties:
> + $nodename:
> + pattern: "^(pciephy|control-phy|usb3phy|phy)(@[0-9a-fA-F]+)?$"
Only phy, pcie-phy, or usb3-phy are valid node names.
A-F is not valid for unit-addresses either.
> +
> + compatible:
> + oneOf:
> + - description: OMAP Control PHY compatibles
> + items:
> + enum:
> + - ti,control-phy-otghs
> + - ti,control-phy-usb2
> + - ti,control-phy-pipe3
> + - ti,control-phy-pcie
> + - ti,control-phy-usb2-dra7
> + - ti,control-phy-usb2-am437
> + - description: PIPE3 high-speed PHY compatibles
> + items:
> + enum:
> + - ti,phy-usb3
> + - ti,phy-pipe3-sata
> + - ti,phy-pipe3-pcie
> + - ti,omap-usb3
IMO, these 2 bindings are completely unrelated and should be split to 2
schema files.
> +
> + reg:
> + minItems: 1
> + maxItems: 4
> +
> + reg-names:
> + oneOf:
> + - description: OMAP Control PHY
> + items:
> + enum: [otghs_control, power, pcie_pcs, control_sma]
> + - description: PIPE3 high-speed PHY
> + items:
> + enum: [phy_rx, phy_tx, pll_ctrl]
Here's one example why.
> +
> + "#phy-cells":
> + const: 0
> +
> + clocks:
> + minItems: 2
> + maxItems: 7
> +
> + clock-names:
> + minItems: 2
> + maxItems: 7
> + items:
> + enum: [wkupclk, sysclk, refclk, dpll_ref,
> + dpll_ref_m2, phy-div, div-clk]
> +
> +# Optional Properties
> + id:
> + description:
> + Instance ID for multiple instances of same PHY type.
> + Used for multi-lane PCIe PHYs.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + default: 1
There aren't any users of this that I see. Drop it (and note that in the
commit msg).
> +
> + syscon-phy-power:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description:
> + Phandle/offset pair to system control module register for PHY
> + power on/off.
> +
> + syscon-pllreset:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description:
> + Phandle/offset pair to CTRL_CORE_SMA_SW_0 register containing
> + SATA_PLL_SOFT_RESET bit (SATA PHY only).
> +
> + syscon-pcs:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description:
> + Phandle/offset pair to system control module for writing PCS delay value.
> +
> + ctrl-module:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + Phandle of control module for PHY power on.
> + deprecated: true
I believe all these phandle props only apply to the PIPE3 binding.
Rob
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^ permalink raw reply
* Re: (subset) [PATCH v15 0/6] pci: qcom: Add QCS8300 PCIe support
From: Bjorn Andersson @ 2026-01-05 19:16 UTC (permalink / raw)
To: konradybcio, robh, krzk+dt, conor+dt, jingoohan1, mani,
lpieralisi, kwilczynski, bhelgaas, johan+linaro, vkoul, kishon,
neil.armstrong, Abel Vesa, Ziyue Zhang
Cc: linux-arm-msm, devicetree, linux-kernel, linux-pci, linux-phy,
qiang.yu, quic_krichai, quic_vbadigan, Ziyue Zhang
In-Reply-To: <20251128104928.4070050-1-ziyue.zhang@oss.qualcomm.com>
On Fri, 28 Nov 2025 18:49:22 +0800, Ziyue Zhang wrote:
> This series adds document, phy, configs support for PCIe in QCS8300.
> It also adds 'link_down' reset for sa8775p.
>
> Have follwing changes:
> - Add dedicated schema for the PCIe controllers found on QCS8300.
> - Add compatible for qcs8300 platform.
> - Add configurations in devicetree for PCIe0, including registers, clocks, interrupts and phy setting sequence.
> - Add configurations in devicetree for PCIe1, including registers, clocks, interrupts and phy setting sequence.
>
> [...]
Applied, thanks!
[2/6] arm64: dts: qcom: qcs8300: enable pcie0
commit: 46a7c01e7e9d296ba09bad579ae0277cfb558b24
[3/6] arm64: dts: qcom: qcs8300-ride: enable pcie0 interface
commit: 33967eadb2153d92ea1de6e9c9ac8ade21c74d86
[4/6] arm64: dts: qcom: qcs8300: enable pcie1
commit: 7565ec0170201aca07c9e1c3b5b6f213c5024599
[5/6] arm64: dts: qcom: qcs8300-ride: enable pcie1 interface
commit: cdb613a84527197f88f8bff3c5ee015e611a8373
[6/6] arm64: dts: qcom: monaco-evk: Enable PCIe0 and PCIe1.
commit: 41e2424651f7c679382bb9e32225d3b541d4aa8d
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
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^ permalink raw reply
* Re: (subset) [PATCH v3 0/3] Add eusb2 repeater squelch detect parameter override
From: Bjorn Andersson @ 2026-01-05 19:16 UTC (permalink / raw)
To: Neil Armstrong, Vinod Koul, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Konrad Dybcio, Abel Vesa, Pengyu Luo, Johan Hovold,
Luca Weiss, Krishna Kurapati
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel
In-Reply-To: <20251219173108.2119296-1-krishna.kurapati@oss.qualcomm.com>
On Fri, 19 Dec 2025 23:01:05 +0530, Krishna Kurapati wrote:
> Add support for eusb2 repeater squelch detect parameter override via DT.
>
> Squelch detect parameter adjusts the voltage level for the threshold used
> to detect valid high-speed data.
>
> Changes in v3:
> - Moved status property to end of repeater node.
> - Updated commit text as per comments received in bindings patch.
> - Retained Krzysztof and Abel RB tags (since its upating commit text adding
> information in bindings code and moving status property in dt code)
>
> [...]
Applied, thanks!
[3/3] arm64: dts: qcom: sm8750-mtp: Add eusb2 repeater tuning parameters
commit: 09d87fdd83894bf3df4ecb79296d03c7a1ac24c3
Best regards,
--
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^ permalink raw reply
* Re: [PATCH RESEND v5 0/3] phy: qcom: edp: Add missing ref clock to x1e80100
From: Bjorn Andersson @ 2026-01-05 19:16 UTC (permalink / raw)
To: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Dmitry Baryshkov,
Konrad Dybcio, Sibi Sankar, Rajendra Nayak, Abel Vesa
Cc: Neil Armstrong, linux-arm-msm, linux-phy, devicetree,
linux-kernel, Krzysztof Kozlowski, Abel Vesa, stable,
Dmitry Baryshkov
In-Reply-To: <20251224-phy-qcom-edp-add-missing-refclk-v5-0-3f45d349b5ac@oss.qualcomm.com>
On Wed, 24 Dec 2025 12:53:26 +0200, Abel Vesa wrote:
> According to documentation, the DP PHY on x1e80100 has another clock
> called ref.
>
> The current X Elite devices supported upstream work fine without this
> clock, because the boot firmware leaves this clock enabled. But we should
> not rely on that. Also, when it comes to power management, this clock
> needs to be also disabled on suspend. So even though this change breaks
> the ABI, it is needed in order to make we disable this clock on runtime
> PM, when that is going to be enabled in the driver.
>
> [...]
Applied, thanks!
[1/3] dt-bindings: phy: qcom-edp: Add missing clock for X Elite
(no commit info)
[2/3] phy: qcom: edp: Make the number of clocks flexible
(no commit info)
[3/3] arm64: dts: qcom: x1e80100: Add missing TCSR ref clock to the DP PHYs
commit: 0907cab01ff9746ecf08592edd9bd85d2636be58
Best regards,
--
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^ permalink raw reply
* Re: (subset) [PATCH RESEND v5 3/3] arm64: dts: qcom: x1e80100: Add missing TCSR ref clock to the DP PHYs
From: Bjorn Andersson @ 2026-01-05 19:16 UTC (permalink / raw)
To: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Dmitry Baryshkov,
Konrad Dybcio, Sibi Sankar, Rajendra Nayak, Abel Vesa
Cc: Neil Armstrong, linux-arm-msm, linux-phy, devicetree,
linux-kernel, Krzysztof Kozlowski, Abel Vesa, stable
In-Reply-To: <20251224-phy-qcom-edp-add-missing-refclk-v5-3-3f45d349b5ac@oss.qualcomm.com>
On Wed, 24 Dec 2025 12:53:29 +0200, Abel Vesa wrote:
> The DP PHYs on X1E80100 need the ref clock which is provided by the
> TCSR CC.
>
> The current X Elite devices supported upstream work fine without this
> clock, because the boot firmware leaves this clock enabled. But we should
> not rely on that. Also, even though this change breaks the ABI, it is
> needed in order to make the driver disables this clock along with the
> other ones, for a proper bring-down of the entire PHY.
>
> [...]
Applied, thanks!
[3/3] arm64: dts: qcom: x1e80100: Add missing TCSR ref clock to the DP PHYs
commit: 0907cab01ff9746ecf08592edd9bd85d2636be58
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
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* Re: [PATCH 01/11] dt-bindings: phy: renesas: usb3-phy: add r8a77990 support
From: Marek Vasut @ 2026-01-05 18:13 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: linux-arm-kernel, Conor Dooley, Geert Uytterhoeven,
Krzysztof Kozlowski, Magnus Damm, Neil Armstrong, Rob Herring,
Vinod Koul, Yoshihiro Shimoda, devicetree, linux-phy,
linux-renesas-soc
In-Reply-To: <20260105-beneficial-seal-of-swiftness-1c5eeb@quoll>
On 1/5/26 9:31 AM, Krzysztof Kozlowski wrote:
> On Thu, Jan 01, 2026 at 09:35:48PM +0100, Marek Vasut wrote:
>> This patch adds support for r8a77990 (R-Car E3).
>
> Please do not use "This commit/patch/change", but imperative mood. See
> longer explanation here:
> https://elixir.bootlin.com/linux/v6.16/source/Documentation/process/submitting-patches.rst#L94
>
> Also, you cannot add support in bindings. You either document hardware
> or you add bindings for or simply you add hardware.
I'll reword it this way for V2, I hope this works ?
"
dt-bindings: phy: renesas: usb3-phy: Document R-Car E3 R8A77990 USB 3.0 PHY
Document USB 3.0 PHY present in Renesas R-Car E3 R8A77990 .
The PHY is compatible with R-Car H3/M3-W/M3-N PHY.
"
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* Re: [PATCH v5 2/7] phy: Add driver for EyeQ5 Ethernet PHY wrapper
From: Théo Lebrun @ 2026-01-05 16:24 UTC (permalink / raw)
To: Vinod Koul, Théo Lebrun
Cc: Vladimir Kondratiev, Grégory Clement, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kishon Vijay Abraham I,
Michael Turquette, Stephen Boyd, Philipp Zabel,
Thomas Bogendoerfer, Neil Armstrong, linux-mips, devicetree,
linux-kernel, linux-phy, linux-clk, Benoît Monin,
Tawfik Bayouk, Thomas Petazzoni, Luca Ceresoli
In-Reply-To: <aUq7E4yh0OgTfdxF@vaman>
Hello Vinod,
On Tue Dec 23, 2025 at 4:53 PM CET, Vinod Koul wrote:
> On 15-12-25, 17:26, Théo Lebrun wrote:
>> EyeQ5 embeds a system-controller called OLB. It features many unrelated
>> registers, and some of those are registers used to configure the
>> integration of the RGMII/SGMII Cadence PHY used by MACB/GEM instances.
>>
>> Wrap in a neat generic PHY provider, exposing two PHYs with standard
>> phy_init() / phy_set_mode() / phy_power_on() operations.
>>
>> Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
>> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
>> ---
>> MAINTAINERS | 1 +
>> drivers/phy/Kconfig | 13 +++
>> drivers/phy/Makefile | 1 +
>> drivers/phy/phy-eyeq5-eth.c | 249 ++++++++++++++++++++++++++++++++++++++++++++
>> 4 files changed, 264 insertions(+)
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 5b11839cba9d..2f67ec9fad57 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -17605,6 +17605,7 @@ F: arch/mips/boot/dts/mobileye/
>> F: arch/mips/configs/eyeq5_defconfig
>> F: arch/mips/mobileye/board-epm5.its.S
>> F: drivers/clk/clk-eyeq.c
>> +F: drivers/phy/phy-eyeq5-eth.c
>> F: drivers/pinctrl/pinctrl-eyeq5.c
>> F: drivers/reset/reset-eyeq.c
>> F: include/dt-bindings/clock/mobileye,eyeq5-clk.h
>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>> index 678dd0452f0a..1aa6eff12dbc 100644
>> --- a/drivers/phy/Kconfig
>> +++ b/drivers/phy/Kconfig
>> @@ -101,6 +101,19 @@ config PHY_NXP_PTN3222
>> schemes. It supports all three USB 2.0 data rates: Low Speed, Full
>> Speed and High Speed.
>>
>> +config PHY_EYEQ5_ETH
>
> sorted please
I wouldn't mind, but entries are currently (v6.19-rc4) not sorted:
$ diff -U100 <(grep ^config drivers/phy/Kconfig) \
<(grep ^config drivers/phy/Kconfig | sort)
--- /dev/fd/63 2026-01-05 15:55:53.891922890 +0100
+++ /dev/fd/62 2026-01-05 15:55:53.891922890 +0100
@@ -1,11 +1,11 @@
config GENERIC_PHY
config GENERIC_PHY_MIPI_DPHY
+config PHY_AIROHA_PCIE
+config PHY_CAN_TRANSCEIVER
+config PHY_EYEQ5_ETH
config PHY_LPC18XX_USB_OTG
+config PHY_NXP_PTN3222
config PHY_PISTACHIO_USB
config PHY_SNPS_EUSB2
config PHY_XGENE
config USB_LGM_PHY
-config PHY_CAN_TRANSCEIVER
-config PHY_AIROHA_PCIE
-config PHY_NXP_PTN3222
-config PHY_EYEQ5_ETH
This is why I appended. In V2, I'll send a first patch to reorder
entries to then be able to add PHY_EYEQ5_ETH in the correct location.
>> + tristate "Ethernet PHY Driver on EyeQ5"
>> + depends on OF
>> + depends on MACH_EYEQ5 || COMPILE_TEST
>> + select AUXILIARY_BUS
>> + select GENERIC_PHY
>> + default MACH_EYEQ5
>
> hmmm why should it be default? Maybe add this is respective defconfig for
> platform instead..?
We have been doing this for other parts of OLB. If you are doing a
config for EyeQ5, most probably you want this enabled.
One example usecase this default field makes config easier: when you
migrate an eyeq* config to eyeq5 without resetting the full config by
applying eyeq5_defconfig. With default field you get this driver
enabled, otherwise you don't and Ethernet doesn't work.
I'd prefer keeping this default but we can drop it if you lean strongly
against it.
>> + help
>> + Enable this to support the Ethernet PHY integrated on EyeQ5.
>> + It supports both RGMII and SGMII. Registers are located in a
>> + shared register region called OLB. If M is selected, the
>> + module will be called phy-eyeq5-eth.
>> +
>> source "drivers/phy/allwinner/Kconfig"
>> source "drivers/phy/amlogic/Kconfig"
>> source "drivers/phy/broadcom/Kconfig"
>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>> index bfb27fb5a494..8289497ece55 100644
>> --- a/drivers/phy/Makefile
>> +++ b/drivers/phy/Makefile
>> @@ -13,6 +13,7 @@ obj-$(CONFIG_PHY_SNPS_EUSB2) += phy-snps-eusb2.o
>> obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o
>> obj-$(CONFIG_PHY_AIROHA_PCIE) += phy-airoha-pcie.o
>> obj-$(CONFIG_PHY_NXP_PTN3222) += phy-nxp-ptn3222.o
>> +obj-$(CONFIG_PHY_EYEQ5_ETH) += phy-eyeq5-eth.o
>
> sorted please
Same as for Kconfig. Will do it in two steps: first sort, then add the
CONFIG_PHY_EYEQ5_ETH line.
$ diff -U100 <(grep ^obj-\\$ drivers/phy/Makefile) \
<(grep ^obj-\\$ drivers/phy/Makefile | sort)
--- /dev/fd/63 2026-01-05 16:11:10.977537425 +0100
+++ /dev/fd/62 2026-01-05 16:11:10.978537396 +0100
@@ -1,11 +1,11 @@
-obj-$(CONFIG_GENERIC_PHY) += phy-core.o
obj-$(CONFIG_GENERIC_PHY_MIPI_DPHY) += phy-core-mipi-dphy.o
+obj-$(CONFIG_GENERIC_PHY) += phy-core.o
+obj-$(CONFIG_PHY_AIROHA_PCIE) += phy-airoha-pcie.o
obj-$(CONFIG_PHY_CAN_TRANSCEIVER) += phy-can-transceiver.o
+obj-$(CONFIG_PHY_EYEQ5_ETH) += phy-eyeq5-eth.o
obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o
-obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
+obj-$(CONFIG_PHY_NXP_PTN3222) += phy-nxp-ptn3222.o
obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
obj-$(CONFIG_PHY_SNPS_EUSB2) += phy-snps-eusb2.o
+obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o
-obj-$(CONFIG_PHY_AIROHA_PCIE) += phy-airoha-pcie.o
-obj-$(CONFIG_PHY_NXP_PTN3222) += phy-nxp-ptn3222.o
-obj-$(CONFIG_PHY_EYEQ5_ETH) += phy-eyeq5-eth.o
[...]
>> +static int eq5_phy_exit(struct phy *phy)
>> +{
>> + struct eq5_phy_inst *inst = phy_get_drvdata(phy);
>> + struct eq5_phy_private *priv = inst->priv;
>> + struct device *dev = priv->dev;
>> +
>> + dev_dbg(dev, "phy_exit(inst=%td)\n", inst - priv->phys);
>> +
>> + writel(0, inst->gp);
>> + writel(0, inst->sgmii);
>> + udelay(5);
>
> this is same patter in init as well...?
Yes! phy_ops::init() must reinit the HW to ensure its config fields
are well taken into account. We might inherit an already initialised
PHY from the bootloader.
We could in theory move those three ops (writel+writel+udelay) into a
helper function but I feel like it would decrease readability without
increasing code quality.
>> +
>> + return 0;
>> +}
>> +
>> +static int eq5_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
>> +{
>> + struct eq5_phy_inst *inst = phy_get_drvdata(phy);
>> + struct eq5_phy_private *priv = inst->priv;
>> + struct device *dev = priv->dev;
>> +
>> + dev_dbg(dev, "phy_set_mode(inst=%td, mode=%d, submode=%d)\n",
>> + inst - priv->phys, mode, submode);
>
> these are good for debug but not for upstream, please drop
Ah this is surprising! They helped me debug this driver and fix one bug
or two so I thought I'd leave them in. They get compiled out by
default. And there is no ftrace events equivalent which would make
those dev_dbg() moot.
⟩ git grep -F dev_dbg\( drivers/ | wc -l
25174
⟩ git grep -F dev_dbg\( drivers/phy/ | wc -l
260
[...]
>> +static int eq5_phy_probe(struct auxiliary_device *adev,
>> + const struct auxiliary_device_id *id)
>> +{
>> + struct device *dev = &adev->dev;
>> + struct phy_provider *provider;
>> + struct eq5_phy_private *priv;
>> + void __iomem *base;
>> + int ret;
>> +
>> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
>> + if (!priv)
>> + return -ENOMEM;
>> +
>> + priv->dev = dev;
>> + dev_set_drvdata(dev, priv);
>> +
>> + base = (void __iomem *)dev_get_platdata(dev);
>
> no need to cast for void *
Yes! My initial goal was to prevent a sparse warning about the implicit
cast from `void *` as returned by dev_get_platdata() and
`void __iomem *base`.
But it does not matter in our case (and the correct solution for
explicit cast would have implied __force).
--
I'll wait for feedback on `default MACH_EYEQ5` and `dev_dbg()` before
sending the next revision.
Thanks for the review!
--
Théo Lebrun, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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* Re: [PATCH] phy: socionext: usb2: Simplify with scoped for each OF child loop
From: Neil Armstrong @ 2026-01-05 15:31 UTC (permalink / raw)
To: Krzysztof Kozlowski, Vinod Koul, Kunihiko Hayashi,
Masami Hiramatsu, linux-phy, linux-arm-kernel, linux-kernel
In-Reply-To: <20260102124848.64474-2-krzysztof.kozlowski@oss.qualcomm.com>
On 1/2/26 13:48, Krzysztof Kozlowski wrote:
> Use scoped for-each loop when iterating over device nodes to make code a
> bit simpler.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
> ---
> drivers/phy/socionext/phy-uniphier-usb2.c | 28 ++++++++---------------
> 1 file changed, 10 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/phy/socionext/phy-uniphier-usb2.c b/drivers/phy/socionext/phy-uniphier-usb2.c
> index 21c201717d95..c49d432e526b 100644
> --- a/drivers/phy/socionext/phy-uniphier-usb2.c
> +++ b/drivers/phy/socionext/phy-uniphier-usb2.c
> @@ -106,7 +106,7 @@ static const struct phy_ops uniphier_u2phy_ops = {
> static int uniphier_u2phy_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> - struct device_node *parent, *child;
> + struct device_node *parent;
> struct uniphier_u2phy_priv *priv = NULL, *next = NULL;
> struct phy_provider *phy_provider;
> struct regmap *regmap;
> @@ -129,34 +129,31 @@ static int uniphier_u2phy_probe(struct platform_device *pdev)
> return PTR_ERR(regmap);
> }
>
> - for_each_child_of_node(dev->of_node, child) {
> + for_each_child_of_node_scoped(dev->of_node, child) {
> priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> - if (!priv) {
> - ret = -ENOMEM;
> - goto out_put_child;
> - }
> + if (!priv)
> + return -ENOMEM;
> +
> priv->regmap = regmap;
>
> priv->vbus = devm_regulator_get_optional(dev, "vbus");
> if (IS_ERR(priv->vbus)) {
> - if (PTR_ERR(priv->vbus) == -EPROBE_DEFER) {
> - ret = PTR_ERR(priv->vbus);
> - goto out_put_child;
> - }
> + if (PTR_ERR(priv->vbus) == -EPROBE_DEFER)
> + return PTR_ERR(priv->vbus);
> +
> priv->vbus = NULL;
> }
>
> priv->phy = devm_phy_create(dev, child, &uniphier_u2phy_ops);
> if (IS_ERR(priv->phy)) {
> dev_err(dev, "Failed to create phy\n");
> - ret = PTR_ERR(priv->phy);
> - goto out_put_child;
> + return PTR_ERR(priv->phy);
> }
>
> ret = of_property_read_u32(child, "reg", &data_idx);
> if (ret) {
> dev_err(dev, "Failed to get reg property\n");
> - goto out_put_child;
> + return ret;
> }
>
> if (data_idx < ndatas)
> @@ -174,11 +171,6 @@ static int uniphier_u2phy_probe(struct platform_device *pdev)
> phy_provider = devm_of_phy_provider_register(dev,
> uniphier_u2phy_xlate);
> return PTR_ERR_OR_ZERO(phy_provider);
> -
> -out_put_child:
> - of_node_put(child);
> -
> - return ret;
> }
>
> static const struct uniphier_u2phy_soc_data uniphier_pro4_data[] = {
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Thanks,
Neil
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