* [PATCH 3/6] dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: document the Milos QMP UFS PHY
From: Luca Weiss @ 2026-01-07 8:05 UTC (permalink / raw)
To: Herbert Xu, David S. Miller, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Alim Akhtar, Avri Altman,
Bart Van Assche, Vinod Koul, Neil Armstrong, Konrad Dybcio
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm,
linux-crypto, devicetree, linux-kernel, linux-scsi, linux-phy,
Luca Weiss
In-Reply-To: <20260107-milos-ufs-v1-0-6982ab20d0ac@fairphone.com>
Document the QMP UFS PHY on the Milos SoC.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
index fba7b2549dde..0b59b21b024c 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
@@ -29,6 +29,7 @@ properties:
- qcom,kaanapali-qmp-ufs-phy
- const: qcom,sm8750-qmp-ufs-phy
- enum:
+ - qcom,milos-qmp-ufs-phy
- qcom,msm8996-qmp-ufs-phy
- qcom,msm8998-qmp-ufs-phy
- qcom,sa8775p-qmp-ufs-phy
@@ -98,6 +99,7 @@ allOf:
compatible:
contains:
enum:
+ - qcom,milos-qmp-ufs-phy
- qcom,msm8998-qmp-ufs-phy
- qcom,sa8775p-qmp-ufs-phy
- qcom,sc7180-qmp-ufs-phy
--
2.52.0
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* [PATCH 2/6] scsi: ufs: qcom,sc7180-ufshc: dt-bindings: Document the Milos UFS Controller
From: Luca Weiss @ 2026-01-07 8:05 UTC (permalink / raw)
To: Herbert Xu, David S. Miller, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Alim Akhtar, Avri Altman,
Bart Van Assche, Vinod Koul, Neil Armstrong, Konrad Dybcio
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm,
linux-crypto, devicetree, linux-kernel, linux-scsi, linux-phy,
Luca Weiss
In-Reply-To: <20260107-milos-ufs-v1-0-6982ab20d0ac@fairphone.com>
Document the UFS Controller on the Milos SoC.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml b/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml
index d94ef4e6b85a..c85f126e52a0 100644
--- a/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml
+++ b/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml
@@ -15,6 +15,7 @@ select:
compatible:
contains:
enum:
+ - qcom,milos-ufshc
- qcom,msm8998-ufshc
- qcom,qcs8300-ufshc
- qcom,sa8775p-ufshc
@@ -33,6 +34,7 @@ properties:
compatible:
items:
- enum:
+ - qcom,milos-ufshc
- qcom,msm8998-ufshc
- qcom,qcs8300-ufshc
- qcom,sa8775p-ufshc
--
2.52.0
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* [PATCH 1/6] dt-bindings: crypto: qcom,inline-crypto-engine: document the Milos ICE
From: Luca Weiss @ 2026-01-07 8:05 UTC (permalink / raw)
To: Herbert Xu, David S. Miller, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Alim Akhtar, Avri Altman,
Bart Van Assche, Vinod Koul, Neil Armstrong, Konrad Dybcio
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm,
linux-crypto, devicetree, linux-kernel, linux-scsi, linux-phy,
Luca Weiss
In-Reply-To: <20260107-milos-ufs-v1-0-6982ab20d0ac@fairphone.com>
Document the Inline Crypto Engine (ICE) on the Milos SoC.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
index c3408dcf5d20..061ff718b23d 100644
--- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
@@ -14,6 +14,7 @@ properties:
items:
- enum:
- qcom,kaanapali-inline-crypto-engine
+ - qcom,milos-inline-crypto-engine
- qcom,qcs8300-inline-crypto-engine
- qcom,sa8775p-inline-crypto-engine
- qcom,sc7180-inline-crypto-engine
--
2.52.0
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* [PATCH 0/6] Enable UFS support on Milos
From: Luca Weiss @ 2026-01-07 8:05 UTC (permalink / raw)
To: Herbert Xu, David S. Miller, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Alim Akhtar, Avri Altman,
Bart Van Assche, Vinod Koul, Neil Armstrong, Konrad Dybcio
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm,
linux-crypto, devicetree, linux-kernel, linux-scsi, linux-phy,
Luca Weiss
Add inline-crypto-engine and UFS bindings & driver parts, then add them
to milos dtsi and enable the UFS storage on Fairphone (Gen. 6).
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
Luca Weiss (6):
dt-bindings: crypto: qcom,inline-crypto-engine: document the Milos ICE
scsi: ufs: qcom,sc7180-ufshc: dt-bindings: Document the Milos UFS Controller
dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: document the Milos QMP UFS PHY
phy: qcom-qmp-ufs: Add Milos support
arm64: dts: qcom: milos: Add UFS nodes
arm64: dts: qcom: milos-fairphone-fp6: Enable UFS
.../bindings/crypto/qcom,inline-crypto-engine.yaml | 1 +
.../bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 2 +
.../devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml | 2 +
arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts | 18 +++
arch/arm64/boot/dts/qcom/milos.dtsi | 127 ++++++++++++++++++++-
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 96 ++++++++++++++++
6 files changed, 243 insertions(+), 3 deletions(-)
---
base-commit: ef1c7b875741bef0ff37ae8ab8a9aaf407dc141c
change-id: 20260106-milos-ufs-7bfbd774ca7c
Best regards,
--
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* Re: [PATCH V4 2/4] dt-bindings: ufs: qcom,sc7180-ufshc: Add UFSHC compatible for x1e80100
From: Krzysztof Kozlowski @ 2026-01-07 7:41 UTC (permalink / raw)
To: Pradeep P V K
Cc: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, martin.petersen,
andersson, konradybcio, taniya.das, dmitry.baryshkov,
manivannan.sadhasivam, linux-arm-msm, linux-phy, devicetree,
linux-kernel, linux-scsi, nitin.rawat
In-Reply-To: <20260106154207.1871487-3-pradeep.pragallapati@oss.qualcomm.com>
On Tue, Jan 06, 2026 at 09:12:05PM +0530, Pradeep P V K wrote:
> Add UFS Host Controller (UFSHC) compatible for x1e80100 SoC. Use
> SM8550 as a fallback since x1e80100 is fully compatible with it.
>
> Qualcomm UFSHC is no longer compatible with JEDEC UFS-2.0 binding.
> Avoid using the "jedec,ufs-2.0" string in the compatible property.
>
> Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
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* Re: [PATCH V3 0/4] Add UFS support for x1e80100 SoC
From: Pradeep Pragallapati @ 2026-01-07 5:51 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Dmitry Baryshkov, vkoul, neil.armstrong, robh, krzk+dt, conor+dt,
martin.petersen, konradybcio, taniya.das, manivannan.sadhasivam,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
nitin.rawat
In-Reply-To: <l67bnlyrrirb3rnz7izqpe4soqjuvkbi2xawit5w2wrcc74vdo@exo4mbpac244>
On 1/6/2026 10:11 PM, Bjorn Andersson wrote:
> On Tue, Jan 06, 2026 at 06:33:19PM +0530, Pradeep Pragallapati wrote:
>>
>>
>> On 1/6/2026 3:50 AM, Dmitry Baryshkov wrote:
>>> On Mon, Jan 05, 2026 at 08:16:39PM +0530, Pradeep P V K wrote:
>>>> Add UFSPHY, UFSHC compatible binding names and UFS devicetree
>>>> enablement changes for Qualcomm x1e80100 SoC.
>>>>
>>>> Changes in V3:
>>>> - Update all dt-bindings commit messages with concise and informative
>>>> statements [Krzysztof]
>>>> - keep the QMP UFS PHY order by last compatible in numerical ascending
>>>> order [Krzysztof]
>>>> - Remove qcom,x1e80100-ufshc from select: enum: list of
>>>> qcom,sc7180-ufshc.yaml file [Krzysztof]
>>>> - Update subject prefix for all dt-bindings [Krzysztof]
>>>> - Add RB-by for SoC dtsi [Konrad, Abel, Taniya]
>>>> - Add RB-by for board dts [Konrad]
>>>> - Link to V2:
>>>> https://lore.kernel.org/all/20251231101951.1026163-1-pradeep.pragallapati@oss.qualcomm.com
>>>
>>> Where did the previous changelog go?
>> i missed to amend, i will update all changelog in my next patchset.
>
> Please just adopt b4, go/upstream provides the documentation you need.
sure, i will adopt to b4 going forward.
>
> Regards,
> Bjorn
>
>>>
>>>>
>>>> ---
>>>> Pradeep P V K (4):
>>>> dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Add QMP UFS PHY
>>>> compatible
>>>> dt-bindings: ufs: qcom,sc7180-ufshc: Add UFSHC compatible for x1e80100
>>>> arm64: dts: qcom: hamoa: Add UFS nodes for x1e80100 SoC
>>>> arm64: dts: qcom: hamoa-iot-evk: Enable UFS
>>>>
>>>> .../phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 4 +
>>>> .../bindings/ufs/qcom,sc7180-ufshc.yaml | 37 +++---
>>>> arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 18 +++
>>>> arch/arm64/boot/dts/qcom/hamoa.dtsi | 123 +++++++++++++++++-
>>>> 4 files changed, 164 insertions(+), 18 deletions(-)
>>>>
>>>> --
>>>> 2.34.1
>>>>
>>>
>>
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* [PATCH v7 0/7] Add ASPEED PCIe Root Complex support
From: Jacky Chou @ 2026-01-07 2:28 UTC (permalink / raw)
To: Mikhail Rudenko
Cc: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery,
Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Linus Walleij, Philipp Zabel,
Neil Armstrong, linux-aspeed@lists.ozlabs.org,
linux-pci@vger.kernel.org, linux-phy@lists.infradead.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Andrew Jeffery,
openbmc@lists.ozlabs.org, linux-gpio@vger.kernel.org
In-Reply-To: <875x9fuj7i.fsf@gmail.com>
Hi Mikhail Rudenko,
> First of all, thank you for your efforts in getting this driver upstreamed! I am
> trying to understand whether this driver supports PCIe devices that have an I/O
> port BAR, where CPU access to I/O ports is required for proper device
> operation.
>
> If I understand correctly, this line in the Aspeed 2600 dtsi file declares the I/O
> port range:
>
> ranges = <0x01000000 0x0 0x00018000 0x00018000 0x0 0x00008000
>
> During system initialization, the pci_remap_iospace() function in
> arch/arm/mm/ioremap.c maps the physical address range
> 0x00018000-0x00020000 to the virtual address PCI_IO_VIRT_BASE
> (0xfee00000). After this mapping, inb() and outb() calls work by converting I/O
> port addresses to virtual addresses starting at PCI_IO_VIRT_BASE, then
> performing reads and writes to those virtual addresses.
>
> What I don't understand is this: according to the Aspeed 2600 datasheet, the
> address range 0x00000000-0x0fffffff (which contains
> 0x00018000-0x00020000) is mapped to Firmware SPI Memory. This would
> mean that outb() operations get routed to memory-mapped SPI flash instead of
> PCIe.
>
> It seems like there's a missing piece to this puzzle. Could you help clarify how
> this is supposed to work?
>
Thank you for pointing this out, and sorry for the confusion.
You are correct that, as things stand, this does not make sense from a real hardware perspective.
In fact, the I/O addressing support you noticed was something we experimented with internally
only. There is no actual hardware design on AST2600 that supports PCIe I/O port addressing in
this way. To enable those experiments, we modified our internal kernel accordingly, but this was
never intended to represent real, supported hardware behavior.
This is our mistake for leaving this description in the DTS, as it can indeed be misleading. We
will remove this part to avoid further confusion.
Thank you again for your careful review and for bringing this to our attention.
Thanks,
Jacky
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* Re: [PATCH v2 net-next 07/10] net: phy: air_en8811h: deprecate "airoha,pnswap-rx" and "airoha,pnswap-tx"
From: Vladimir Oltean @ 2026-01-06 22:16 UTC (permalink / raw)
To: Bjørn Mork
Cc: netdev, devicetree, linux-phy, linux-kernel, linux-arm-kernel,
linux-mediatek, Daniel Golle, Horatiu Vultur, Andrew Lunn,
Heiner Kallweit, Russell King, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vinod Koul, Neil Armstrong, Matthias Brugger,
AngeloGioacchino Del Regno, Eric Woudstra, Marek Behún,
Lee Jones, Patrice Chotard
In-Reply-To: <87qzs2a7hl.fsf@miraculix.mork.no>
On Tue, Jan 06, 2026 at 08:03:50PM +0100, Bjørn Mork wrote:
> Vladimir Oltean <vladimir.oltean@nxp.com> writes:
>
> > diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
> > index a7ade7b95a2e..7b73332a13d9 100644
> > --- a/drivers/net/phy/Kconfig
> > +++ b/drivers/net/phy/Kconfig
> > @@ -98,6 +98,7 @@ config AS21XXX_PHY
> >
> > config AIR_EN8811H_PHY
> > tristate "Airoha EN8811H 2.5 Gigabit PHY"
> > + select PHY_COMMON_PROPS
>
> GENERIC_PHY_COMMON_PROPS maybe?
Thanks for pointing out the inconsistency with patch 05/10.
Yes, this should have been GENERIC_PHY_COMMON_PROPS.
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* Re: [PATCH v2 net-next 07/10] net: phy: air_en8811h: deprecate "airoha,pnswap-rx" and "airoha,pnswap-tx"
From: Bjørn Mork @ 2026-01-06 19:03 UTC (permalink / raw)
To: Vladimir Oltean
Cc: netdev, devicetree, linux-phy, linux-kernel, linux-arm-kernel,
linux-mediatek, Daniel Golle, Horatiu Vultur, Andrew Lunn,
Heiner Kallweit, Russell King, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vinod Koul, Neil Armstrong, Matthias Brugger,
AngeloGioacchino Del Regno, Eric Woudstra, Marek Behún,
Lee Jones, Patrice Chotard
In-Reply-To: <20260103210403.438687-8-vladimir.oltean@nxp.com>
Vladimir Oltean <vladimir.oltean@nxp.com> writes:
> diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
> index a7ade7b95a2e..7b73332a13d9 100644
> --- a/drivers/net/phy/Kconfig
> +++ b/drivers/net/phy/Kconfig
> @@ -98,6 +98,7 @@ config AS21XXX_PHY
>
> config AIR_EN8811H_PHY
> tristate "Airoha EN8811H 2.5 Gigabit PHY"
> + select PHY_COMMON_PROPS
GENERIC_PHY_COMMON_PROPS maybe?
Bjørn
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* Re: [PATCH v2 1/2] dt-bindings: phy: Add PHY_TYPE_XAUI definition
From: Rob Herring (Arm) @ 2026-01-06 18:29 UTC (permalink / raw)
To: Siddharth Vadapalli
Cc: conor+dt, linux-kernel, krzk, linux-arm-kernel, krzk+dt,
devicetree, rogerq, sjakhade, vkoul, srk, linux-phy,
neil.armstrong
In-Reply-To: <20260104114422.2868321-2-s-vadapalli@ti.com>
On Sun, 04 Jan 2026 17:14:17 +0530, Siddharth Vadapalli wrote:
> From: Swapnil Jakhade <sjakhade@cadence.com>
>
> XAUI (eXtended Attachment Unit Interface) is a high-speed serial interface
> standard for 10 Gigabit Ethernet (10GbE). It uses four lanes with each
> lane operating at 3.125 Gbps (totaling 10 Gbps), to extend the XGMII
> interface across circuit boards, commonly used in backplanes for
> networking switches and high-performance computing. XAUI is defined as a
> standardized instantiation of XGMII Extender in the IEEE 802.3
> specification.
>
> Add definition for XAUI PHY type.
>
> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
> [s-vadapalli: added detailed description of XAUI in the commit message]
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
>
> v1 of this patch is at:
> https://lore.kernel.org/r/20251224054905.763399-2-s-vadapalli@ti.com/
> Changes since v1:
> - The commit message has been updated to provide a detailed description of
> XAUI based on feedback from Krzysztof at:
> https://lore.kernel.org/r/20251227-airborne-energetic-kingfisher-adc4fb@quoll/
>
> Regards,
> Siddharth.
>
> include/dt-bindings/phy/phy.h | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
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* Re: [PATCH v2 net-next 08/10] dt-bindings: net: pcs: mediatek,sgmiisys: deprecate "mediatek,pnswap"
From: Rob Herring (Arm) @ 2026-01-06 18:24 UTC (permalink / raw)
To: Vladimir Oltean
Cc: Marek Behún, Daniel Golle, Matthias Brugger, linux-kernel,
Paolo Abeni, Vinod Koul, Eric Woudstra, David S. Miller,
Heiner Kallweit, Andrew Lunn, Patrice Chotard,
Krzysztof Kozlowski, netdev, devicetree, Conor Dooley,
linux-arm-kernel, Russell King, linux-mediatek, Horatiu Vultur,
Neil Armstrong, Jakub Kicinski, Lee Jones,
AngeloGioacchino Del Regno, linux-phy, Eric Dumazet,
Bjørn Mork
In-Reply-To: <20260103210403.438687-9-vladimir.oltean@nxp.com>
On Sat, 03 Jan 2026 23:04:01 +0200, Vladimir Oltean wrote:
> Reference the common PHY properties, and update the example to use them.
> Note that a PCS subnode exists, and it seems a better container of the
> polarity description than the SGMIISYS node that hosts "mediatek,pnswap".
> So use that.
>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> ---
> v1->v2: none
>
> .../devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
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* Re: [PATCH v2 net-next 02/10] dt-bindings: phy-common-props: create a reusable "protocol-names" definition
From: Rob Herring (Arm) @ 2026-01-06 18:23 UTC (permalink / raw)
To: Vladimir Oltean
Cc: Daniel Golle, Matthias Brugger, Bjørn Mork,
AngeloGioacchino Del Regno, Krzysztof Kozlowski, Eric Woudstra,
Lee Jones, devicetree, Eric Dumazet, linux-mediatek,
Marek Behún, Russell King, Vinod Koul, linux-phy,
Neil Armstrong, linux-kernel, Conor Dooley, David S. Miller,
Paolo Abeni, Horatiu Vultur, Patrice Chotard, Heiner Kallweit,
Andrew Lunn, netdev, Jakub Kicinski, linux-arm-kernel
In-Reply-To: <20260103210403.438687-3-vladimir.oltean@nxp.com>
On Sat, 03 Jan 2026 23:03:55 +0200, Vladimir Oltean wrote:
> Other properties also need to be defined per protocol than just
> tx-p2p-microvolt-names. Create a common definition to avoid copying a 55
> line property.
>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> ---
> v1->v2: none
>
> .../bindings/phy/phy-common-props.yaml | 34 +++++++++++--------
> 1 file changed, 19 insertions(+), 15 deletions(-)
>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
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* Re: [PATCH v2 net-next 03/10] dt-bindings: phy-common-props: ensure protocol-names are unique
From: Rob Herring (Arm) @ 2026-01-06 18:22 UTC (permalink / raw)
To: Vladimir Oltean
Cc: Conor Dooley, Eric Dumazet, Russell King, netdev, linux-phy,
linux-mediatek, AngeloGioacchino Del Regno, David S. Miller,
linux-kernel, Eric Woudstra, devicetree, Neil Armstrong,
Lee Jones, Vinod Koul, Daniel Golle, Jakub Kicinski,
Bjørn Mork, linux-arm-kernel, Patrice Chotard,
Marek Behún, Matthias Brugger, Paolo Abeni,
Krzysztof Kozlowski, Horatiu Vultur, Heiner Kallweit, Andrew Lunn
In-Reply-To: <20260103210403.438687-4-vladimir.oltean@nxp.com>
On Sat, 03 Jan 2026 23:03:56 +0200, Vladimir Oltean wrote:
> Rob Herring points out that "The default for .*-names is the entries
> don't have to be unique.":
> https://lore.kernel.org/linux-phy/20251204155219.GA1533839-robh@kernel.org/
>
> Let's use uniqueItems: true to make sure the schema enforces this. It
> doesn't make sense in this case to have duplicate properties for the
> same SerDes protocol.
>
> Note that this can only be done with the $defs + $ref pattern as
> established by the previous commit. When the tx-p2p-microvolt-names
> constraints were expressed directly under "properties", it would have
> been validated by the string-array meta-schema, which does not support
> the 'uniqueItems' keyword as can be seen below.
>
> properties:tx-p2p-microvolt-names: Additional properties are not allowed ('uniqueItems' was unexpected)
> from schema $id: http://devicetree.org/meta-schemas/string-array.yaml
>
> Suggested-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> ---
> v1->v2: patch is new
>
> Documentation/devicetree/bindings/phy/phy-common-props.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
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* Re: [PATCH V3 0/4] Add UFS support for x1e80100 SoC
From: Bjorn Andersson @ 2026-01-06 16:41 UTC (permalink / raw)
To: Pradeep Pragallapati
Cc: Dmitry Baryshkov, vkoul, neil.armstrong, robh, krzk+dt, conor+dt,
martin.petersen, konradybcio, taniya.das, manivannan.sadhasivam,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
nitin.rawat
In-Reply-To: <0689ae93-0684-4bf8-9bce-f9f32e56fe06@oss.qualcomm.com>
On Tue, Jan 06, 2026 at 06:33:19PM +0530, Pradeep Pragallapati wrote:
>
>
> On 1/6/2026 3:50 AM, Dmitry Baryshkov wrote:
> > On Mon, Jan 05, 2026 at 08:16:39PM +0530, Pradeep P V K wrote:
> > > Add UFSPHY, UFSHC compatible binding names and UFS devicetree
> > > enablement changes for Qualcomm x1e80100 SoC.
> > >
> > > Changes in V3:
> > > - Update all dt-bindings commit messages with concise and informative
> > > statements [Krzysztof]
> > > - keep the QMP UFS PHY order by last compatible in numerical ascending
> > > order [Krzysztof]
> > > - Remove qcom,x1e80100-ufshc from select: enum: list of
> > > qcom,sc7180-ufshc.yaml file [Krzysztof]
> > > - Update subject prefix for all dt-bindings [Krzysztof]
> > > - Add RB-by for SoC dtsi [Konrad, Abel, Taniya]
> > > - Add RB-by for board dts [Konrad]
> > > - Link to V2:
> > > https://lore.kernel.org/all/20251231101951.1026163-1-pradeep.pragallapati@oss.qualcomm.com
> >
> > Where did the previous changelog go?
> i missed to amend, i will update all changelog in my next patchset.
Please just adopt b4, go/upstream provides the documentation you need.
Regards,
Bjorn
> >
> > >
> > > ---
> > > Pradeep P V K (4):
> > > dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Add QMP UFS PHY
> > > compatible
> > > dt-bindings: ufs: qcom,sc7180-ufshc: Add UFSHC compatible for x1e80100
> > > arm64: dts: qcom: hamoa: Add UFS nodes for x1e80100 SoC
> > > arm64: dts: qcom: hamoa-iot-evk: Enable UFS
> > >
> > > .../phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 4 +
> > > .../bindings/ufs/qcom,sc7180-ufshc.yaml | 37 +++---
> > > arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 18 +++
> > > arch/arm64/boot/dts/qcom/hamoa.dtsi | 123 +++++++++++++++++-
> > > 4 files changed, 164 insertions(+), 18 deletions(-)
> > >
> > > --
> > > 2.34.1
> > >
> >
>
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* [PATCH V4 4/4] arm64: dts: qcom: hamoa-iot-evk: Enable UFS
From: Pradeep P V K @ 2026-01-06 15:42 UTC (permalink / raw)
To: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, martin.petersen,
andersson, konradybcio, taniya.das, dmitry.baryshkov,
manivannan.sadhasivam
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
nitin.rawat, Pradeep P V K, Konrad Dybcio
In-Reply-To: <20260106154207.1871487-1-pradeep.pragallapati@oss.qualcomm.com>
Enable UFS for HAMOA-IOT-EVK board.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts
index 88e3e7bed998..23cd913b05f5 100644
--- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts
+++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts
@@ -1253,6 +1253,24 @@ &uart21 {
status = "okay";
};
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l3i_0p8>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 238 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l17b_2p5>;
+ vcc-max-microamp = <1300000>;
+ vccq-supply = <&vreg_l2i_1p2>;
+ vccq-max-microamp = <1200000>;
+
+ status = "okay";
+};
+
&usb_1_ss0_dwc3_hs {
remote-endpoint = <&pmic_glink_ss0_hs_in>;
};
--
2.34.1
--
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* [PATCH V4 3/4] arm64: dts: qcom: hamoa: Add UFS nodes for x1e80100 SoC
From: Pradeep P V K @ 2026-01-06 15:42 UTC (permalink / raw)
To: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, martin.petersen,
andersson, konradybcio, taniya.das, dmitry.baryshkov,
manivannan.sadhasivam
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
nitin.rawat, Pradeep P V K, Konrad Dybcio, Abel Vesa,
Manivannan Sadhasivam
In-Reply-To: <20260106154207.1871487-1-pradeep.pragallapati@oss.qualcomm.com>
Add UFS host controller and PHY nodes for x1e80100 SoC.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/hamoa.dtsi | 122 +++++++++++++++++++++++++++-
1 file changed, 119 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
index f7d71793bc77..25c838102280 100644
--- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
+++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
@@ -835,9 +835,9 @@ gcc: clock-controller@100000 {
<0>,
<0>,
<0>,
- <0>,
- <0>,
- <0>;
+ <&ufs_mem_phy 0>,
+ <&ufs_mem_phy 1>,
+ <&ufs_mem_phy 2>;
power-domains = <&rpmhpd RPMHPD_CX>;
#clock-cells = <1>;
@@ -3848,6 +3848,122 @@ pcie4_phy: phy@1c0e000 {
status = "disabled";
};
+ ufs_mem_phy: phy@1d80000 {
+ compatible = "qcom,x1e80100-qmp-ufs-phy",
+ "qcom,sm8550-qmp-ufs-phy";
+ reg = <0x0 0x01d80000 0x0 0x2000>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+ <&tcsr TCSR_UFS_PHY_CLKREF_EN>;
+
+ clock-names = "ref",
+ "ref_aux",
+ "qref";
+ resets = <&ufs_mem_hc 0>;
+ reset-names = "ufsphy";
+
+ power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>;
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ ufs_mem_hc: ufshc@1d84000 {
+ compatible = "qcom,x1e80100-ufshc",
+ "qcom,sm8550-ufshc",
+ "qcom,ufshc";
+ reg = <0x0 0x01d84000 0x0 0x3000>;
+
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>,
+ <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+ <&rpmhcc RPMH_LN_BB_CLK3>,
+ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+ clock-names = "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk",
+ "rx_lane1_sync_clk";
+
+ operating-points-v2 = <&ufs_opp_table>;
+
+ resets = <&gcc GCC_UFS_PHY_BCR>;
+ reset-names = "rst";
+
+ interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "ufs-ddr",
+ "cpu-ufs";
+
+ power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ iommus = <&apps_smmu 0x1a0 0>;
+ dma-coherent;
+
+ lanes-per-direction = <2>;
+
+ phys = <&ufs_mem_phy>;
+ phy-names = "ufsphy";
+
+ #reset-cells = <1>;
+
+ status = "disabled";
+
+ ufs_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-75000000 {
+ opp-hz = /bits/ 64 <75000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <75000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-150000000 {
+ opp-hz = /bits/ 64 <150000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <150000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <300000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
cryptobam: dma-controller@1dc4000 {
compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
reg = <0x0 0x01dc4000 0x0 0x28000>;
--
2.34.1
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* [PATCH V4 2/4] dt-bindings: ufs: qcom,sc7180-ufshc: Add UFSHC compatible for x1e80100
From: Pradeep P V K @ 2026-01-06 15:42 UTC (permalink / raw)
To: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, martin.petersen,
andersson, konradybcio, taniya.das, dmitry.baryshkov,
manivannan.sadhasivam
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
nitin.rawat, Pradeep P V K
In-Reply-To: <20260106154207.1871487-1-pradeep.pragallapati@oss.qualcomm.com>
Add UFS Host Controller (UFSHC) compatible for x1e80100 SoC. Use
SM8550 as a fallback since x1e80100 is fully compatible with it.
Qualcomm UFSHC is no longer compatible with JEDEC UFS-2.0 binding.
Avoid using the "jedec,ufs-2.0" string in the compatible property.
Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
---
.../bindings/ufs/qcom,sc7180-ufshc.yaml | 36 +++++++++++--------
1 file changed, 21 insertions(+), 15 deletions(-)
diff --git a/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml b/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml
index d94ef4e6b85a..fe18e41ebac7 100644
--- a/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml
+++ b/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml
@@ -31,21 +31,27 @@ select:
properties:
compatible:
- items:
- - enum:
- - qcom,msm8998-ufshc
- - qcom,qcs8300-ufshc
- - qcom,sa8775p-ufshc
- - qcom,sc7180-ufshc
- - qcom,sc7280-ufshc
- - qcom,sc8180x-ufshc
- - qcom,sc8280xp-ufshc
- - qcom,sm8250-ufshc
- - qcom,sm8350-ufshc
- - qcom,sm8450-ufshc
- - qcom,sm8550-ufshc
- - const: qcom,ufshc
- - const: jedec,ufs-2.0
+ oneOf:
+ - items:
+ - enum:
+ - qcom,x1e80100-ufshc
+ - const: qcom,sm8550-ufshc
+ - const: qcom,ufshc
+ - items:
+ - enum:
+ - qcom,msm8998-ufshc
+ - qcom,qcs8300-ufshc
+ - qcom,sa8775p-ufshc
+ - qcom,sc7180-ufshc
+ - qcom,sc7280-ufshc
+ - qcom,sc8180x-ufshc
+ - qcom,sc8280xp-ufshc
+ - qcom,sm8250-ufshc
+ - qcom,sm8350-ufshc
+ - qcom,sm8450-ufshc
+ - qcom,sm8550-ufshc
+ - const: qcom,ufshc
+ - const: jedec,ufs-2.0
reg:
maxItems: 1
--
2.34.1
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* [PATCH V4 1/4] dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Add QMP UFS PHY compatible
From: Pradeep P V K @ 2026-01-06 15:42 UTC (permalink / raw)
To: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, martin.petersen,
andersson, konradybcio, taniya.das, dmitry.baryshkov,
manivannan.sadhasivam
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
nitin.rawat, Pradeep P V K, Krzysztof Kozlowski
In-Reply-To: <20260106154207.1871487-1-pradeep.pragallapati@oss.qualcomm.com>
Document QMP UFS PHY compatible for x1e80100 SoC. Use SM8550 as a
fallback since x1e80100 is fully compatible with it.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
---
.../devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
index fba7b2549dde..166e3787db58 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
@@ -20,6 +20,10 @@ properties:
- enum:
- qcom,qcs615-qmp-ufs-phy
- const: qcom,sm6115-qmp-ufs-phy
+ - items:
+ - enum:
+ - qcom,x1e80100-qmp-ufs-phy
+ - const: qcom,sm8550-qmp-ufs-phy
- items:
- enum:
- qcom,qcs8300-qmp-ufs-phy
--
2.34.1
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* [PATCH V4 0/4] Add UFS support for x1e80100 SoC
From: Pradeep P V K @ 2026-01-06 15:42 UTC (permalink / raw)
To: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, martin.petersen,
andersson, konradybcio, taniya.das, dmitry.baryshkov,
manivannan.sadhasivam
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
nitin.rawat, Pradeep P V K
Add UFSPHY, UFSHC compatible binding names and UFS devicetree
enablement changes for Qualcomm x1e80100 SoC.
Changes in V4:
- Update ufs@ with ufshc@ in SoC dtsi [Mani]
- Retain complete change history in cover letter [Dmitry]
- Remove "jedec,ufs-2.0" compatible from ufshc dt-bindings
and SoC dtsi files [Krzysztof, Mani]
- Remove RB-by tag from Krzysztof and AB-by tag from Mani on
UFSHC dt-binding file as it has changes and needs re-review.
- Add RB-by for QMP UFS PHY dt-binding [Krzysztof]
- Add RB-by for SoC dtsi [Konrad, Abel, Taniya, Mani]
- Add RB-by for board dts [Konrad]
- Link to V3:
https://lore.kernel.org/all/0689ae93-0684-4bf8-9bce-f9f32e56fe06@oss.qualcomm.com
Changes in V3:
- Update all dt-bindings commit messages with concise and informative
statements [Krzysztof]
- keep the QMP UFS PHY order by last compatible in numerical ascending
order [Krzysztof]
- Remove qcom,x1e80100-ufshc from select: enum: list of
qcom,sc7180-ufshc.yaml file [Krzysztof]
- Update subject prefix for all dt-bindings [Krzysztof]
- Add RB-by for SoC dtsi [Konrad, Abel, Taniya]
- Add RB-by for board dts [Konrad]
- Link to V2:
https://lore.kernel.org/all/20251231101951.1026163-1-pradeep.pragallapati@oss.qualcomm.com
Changes in V2:
- Update all dt-bindings commit messages to explain fallback
to SM8550 [Krzysztof]
- Pad register addresses to 8-digit hex format [Konrad]
- Place one compatible string per line [Konrad]
- Replace chip codenames with numeric identifiers throughout [Konrad]
- Fix dt_binding_check error in UFSHC dt-bindings [Rob]
- This series is rebased on GCC bindings and driver changes:
https://lore.kernel.org/lkml/20251230-ufs_symbol_clk-v1-0-47d46b24c087@oss.qualcomm.com/
- This series address issues and gaps noticed on:
https://lore.kernel.org/linux-devicetree/20250814005904.39173-2-harrison.vanderbyl@gmail.com/
https://lore.kernel.org/linux-devicetree/p3mhtj2rp6y2ezuwpd2gu7dwx5cbckfu4s4pazcudi4j2wogtr@4yecb2bkeyms/
- Link to V1:
https://lore.kernel.org/linux-phy/20251229060642.2807165-1-pradeep.pragallapati@oss.qualcomm.com/
---
Pradeep P V K (4):
dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Add QMP UFS PHY
compatible
dt-bindings: ufs: qcom,sc7180-ufshc: Add UFSHC compatible for x1e80100
arm64: dts: qcom: hamoa: Add UFS nodes for x1e80100 SoC
arm64: dts: qcom: hamoa-iot-evk: Enable UFS
.../phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 4 +
.../bindings/ufs/qcom,sc7180-ufshc.yaml | 37 +++---
arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 18 +++
arch/arm64/boot/dts/qcom/hamoa.dtsi | 123 +++++++++++++++++-
4 files changed, 164 insertions(+), 18 deletions(-)
--
2.34.1
--
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* RE: [PATCH] phy/marvell/phy-mvebu-cp110-utmi: fix dr_mode property read from dts
From: Aleksandar Gerasimovski @ 2026-01-06 15:28 UTC (permalink / raw)
To: linux-kernel@vger.kernel.org, vkoul@kernel.org, kishon@kernel.org
Cc: kostap@marvell.com, linux-phy@lists.infradead.org
In-Reply-To: <20260106150643.922110-1-aleksandar.gerasimovski@belden.com>
-----Original Message-----
From: Aleksandar Gerasimovski <aleksandar.gerasimovski@belden.com>
Sent: Tuesday, January 6, 2026 4:07 PM
To: linux-kernel@vger.kernel.org; vkoul@kernel.org; kishon@kernel.org; Aleksandar Gerasimovski <Aleksandar.Gerasimovski@belden.com>
Subject: [PATCH] phy/marvell/phy-mvebu-cp110-utmi: fix dr_mode property read from dts
The problem with the current implementation is that it does not consider that the USB controller can have multiple PHY handles with different arguments count, as for example we have in our cn9131 based platform:
"phys = <&cp0_comphy1 0>, <&cp0_utmi0>;".
In such case calling "of_usb_get_dr_mode_by_phy" with -1 (no phy-cells) leads to not proper phy detection, taking the "marvell,cp110-utmi-phy"
dts definition we can call the "of_usb_get_dr_mode_by_phy" with 0 (#phy-cells = <0>) and safely look for that phy.
Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@belden.com>
---
drivers/phy/marvell/phy-mvebu-cp110-utmi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/marvell/phy-mvebu-cp110-utmi.c b/drivers/phy/marvell/phy-mvebu-cp110-utmi.c
index 59903f86b13f..dd3e515a8e86 100644
--- a/drivers/phy/marvell/phy-mvebu-cp110-utmi.c
+++ b/drivers/phy/marvell/phy-mvebu-cp110-utmi.c
@@ -338,7 +338,7 @@ static int mvebu_cp110_utmi_phy_probe(struct platform_device *pdev)
return -ENOMEM;
}
- port->dr_mode = of_usb_get_dr_mode_by_phy(child, -1);
+ port->dr_mode = of_usb_get_dr_mode_by_phy(child, 0);
if ((port->dr_mode != USB_DR_MODE_HOST) &&
(port->dr_mode != USB_DR_MODE_PERIPHERAL)) {
dev_err(&pdev->dev,
--
2.34.1
**********************************************************************
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* Re: [PATCH V3 3/4] arm64: dts: qcom: hamoa: Add UFS nodes for x1e80100 SoC
From: Pradeep Pragallapati @ 2026-01-06 14:11 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, martin.petersen,
andersson, konradybcio, taniya.das, dmitry.baryshkov,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
nitin.rawat, Konrad Dybcio, Abel Vesa
In-Reply-To: <dbkrbec6t2agwk2swe7olz6zkhyphpbcl7dpmlwie4esvbbvro@s7ybpmaod3d5>
On 1/6/2026 7:22 PM, Manivannan Sadhasivam wrote:
> On Tue, Jan 06, 2026 at 06:30:05PM +0530, Pradeep Pragallapati wrote:
>>
>>
>> On 1/6/2026 1:36 PM, Manivannan Sadhasivam wrote:
>>> On Mon, Jan 05, 2026 at 08:16:42PM +0530, Pradeep P V K wrote:
>>>> Add UFS host controller and PHY nodes for x1e80100 SoC.
>>>>
>>>
>>> Minor nits below. With those fixed,
>>>
>>> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
>>>
>>>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>>> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
>>>> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
>>>> Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
>>>> ---
>>>> arch/arm64/boot/dts/qcom/hamoa.dtsi | 123 +++++++++++++++++++++++++++-
>>>> 1 file changed, 120 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
>>>> index f7d71793bc77..33899fa06aa4 100644
>>>> --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
>>>> @@ -835,9 +835,9 @@ gcc: clock-controller@100000 {
>>>> <0>,
>>>> <0>,
>>>> <0>,
>>>> - <0>,
>>>> - <0>,
>>>> - <0>;
>>>> + <&ufs_mem_phy 0>,
>>>> + <&ufs_mem_phy 1>,
>>>> + <&ufs_mem_phy 2>;
>>>> power-domains = <&rpmhpd RPMHPD_CX>;
>>>> #clock-cells = <1>;
>>>> @@ -3848,6 +3848,123 @@ pcie4_phy: phy@1c0e000 {
>>>> status = "disabled";
>>>> };
>>>> + ufs_mem_phy: phy@1d80000 {
>>>> + compatible = "qcom,x1e80100-qmp-ufs-phy",
>>>> + "qcom,sm8550-qmp-ufs-phy";
>>>> + reg = <0x0 0x01d80000 0x0 0x2000>;
>>>> +
>>>> + clocks = <&rpmhcc RPMH_CXO_CLK>,
>>>> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
>>>> + <&tcsr TCSR_UFS_PHY_CLKREF_EN>;
>>>> +
>>>> + clock-names = "ref",
>>>> + "ref_aux",
>>>> + "qref";
>>>> + resets = <&ufs_mem_hc 0>;
>>>> + reset-names = "ufsphy";
>>>> +
>>>> + power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>;
>>>> +
>>>> + #clock-cells = <1>;
>>>> + #phy-cells = <0>;
>>>> +
>>>> + status = "disabled";
>>>> + };
>>>> +
>>>> + ufs_mem_hc: ufs@1d84000 {
>>>
>>> ufshc@
>> ok, i will update in the next patchset.
>>>
>>>> + compatible = "qcom,x1e80100-ufshc",
>>>> + "qcom,sm8550-ufshc",
>>>> + "qcom,ufshc",
>>>> + "jedec,ufs-2.0";
>>>
>>> Drop jedec compatible as Qcom UFS controller cannot fallback to generic ufshc
>>> driver.
>> "jedec,ufs-2.0" was set to const in dt-bindings, dropping now will lead to
>> dtbs_check failures. is it ok, if i continue with it ?
>
> I was implying that you need to drop it from both binding and dts. It was
> incorrect from the start anyway, so there is no ABI breakage. But make sure you
> justify it in the description.
>
sure, i will update in my next patchset.
> - Mani
>
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^ permalink raw reply
* Re: [PATCH V3 3/4] arm64: dts: qcom: hamoa: Add UFS nodes for x1e80100 SoC
From: Manivannan Sadhasivam @ 2026-01-06 13:52 UTC (permalink / raw)
To: Pradeep Pragallapati
Cc: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, martin.petersen,
andersson, konradybcio, taniya.das, dmitry.baryshkov,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
nitin.rawat, Konrad Dybcio, Abel Vesa
In-Reply-To: <e396bef2-e5bf-4e6d-98f4-37977d5d93ec@oss.qualcomm.com>
On Tue, Jan 06, 2026 at 06:30:05PM +0530, Pradeep Pragallapati wrote:
>
>
> On 1/6/2026 1:36 PM, Manivannan Sadhasivam wrote:
> > On Mon, Jan 05, 2026 at 08:16:42PM +0530, Pradeep P V K wrote:
> > > Add UFS host controller and PHY nodes for x1e80100 SoC.
> > >
> >
> > Minor nits below. With those fixed,
> >
> > Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
> >
> > > Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> > > Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> > > Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
> > > Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
> > > ---
> > > arch/arm64/boot/dts/qcom/hamoa.dtsi | 123 +++++++++++++++++++++++++++-
> > > 1 file changed, 120 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
> > > index f7d71793bc77..33899fa06aa4 100644
> > > --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
> > > @@ -835,9 +835,9 @@ gcc: clock-controller@100000 {
> > > <0>,
> > > <0>,
> > > <0>,
> > > - <0>,
> > > - <0>,
> > > - <0>;
> > > + <&ufs_mem_phy 0>,
> > > + <&ufs_mem_phy 1>,
> > > + <&ufs_mem_phy 2>;
> > > power-domains = <&rpmhpd RPMHPD_CX>;
> > > #clock-cells = <1>;
> > > @@ -3848,6 +3848,123 @@ pcie4_phy: phy@1c0e000 {
> > > status = "disabled";
> > > };
> > > + ufs_mem_phy: phy@1d80000 {
> > > + compatible = "qcom,x1e80100-qmp-ufs-phy",
> > > + "qcom,sm8550-qmp-ufs-phy";
> > > + reg = <0x0 0x01d80000 0x0 0x2000>;
> > > +
> > > + clocks = <&rpmhcc RPMH_CXO_CLK>,
> > > + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
> > > + <&tcsr TCSR_UFS_PHY_CLKREF_EN>;
> > > +
> > > + clock-names = "ref",
> > > + "ref_aux",
> > > + "qref";
> > > + resets = <&ufs_mem_hc 0>;
> > > + reset-names = "ufsphy";
> > > +
> > > + power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>;
> > > +
> > > + #clock-cells = <1>;
> > > + #phy-cells = <0>;
> > > +
> > > + status = "disabled";
> > > + };
> > > +
> > > + ufs_mem_hc: ufs@1d84000 {
> >
> > ufshc@
> ok, i will update in the next patchset.
> >
> > > + compatible = "qcom,x1e80100-ufshc",
> > > + "qcom,sm8550-ufshc",
> > > + "qcom,ufshc",
> > > + "jedec,ufs-2.0";
> >
> > Drop jedec compatible as Qcom UFS controller cannot fallback to generic ufshc
> > driver.
> "jedec,ufs-2.0" was set to const in dt-bindings, dropping now will lead to
> dtbs_check failures. is it ok, if i continue with it ?
I was implying that you need to drop it from both binding and dts. It was
incorrect from the start anyway, so there is no ABI breakage. But make sure you
justify it in the description.
- Mani
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* Re: [PATCH V3 3/4] arm64: dts: qcom: hamoa: Add UFS nodes for x1e80100 SoC
From: Pradeep Pragallapati @ 2026-01-06 13:51 UTC (permalink / raw)
To: Krzysztof Kozlowski, Manivannan Sadhasivam
Cc: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, martin.petersen,
andersson, konradybcio, taniya.das, dmitry.baryshkov,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
nitin.rawat, Konrad Dybcio, Abel Vesa
In-Reply-To: <67fd0c34-0ea4-461c-8586-4eaca678ccb3@kernel.org>
On 1/6/2026 7:10 PM, Krzysztof Kozlowski wrote:
> On 06/01/2026 14:00, Pradeep Pragallapati wrote:
>>>
>>>> + compatible = "qcom,x1e80100-ufshc",
>>>> + "qcom,sm8550-ufshc",
>>>> + "qcom,ufshc",
>>>> + "jedec,ufs-2.0";
>>>
>>> Drop jedec compatible as Qcom UFS controller cannot fallback to generic ufshc
>>> driver.
>> "jedec,ufs-2.0" was set to const in dt-bindings, dropping now will lead
>> to dtbs_check failures. is it ok, if i continue with it ?
>
> No, it is not ok. You cannot have errors/warnings and I think it is
> obvious that you need to fix everything, not only DTS.
sure, i will update in my next patchset.
>
> Best regards,
> Krzysztof
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* Re: [PATCH V3 3/4] arm64: dts: qcom: hamoa: Add UFS nodes for x1e80100 SoC
From: Krzysztof Kozlowski @ 2026-01-06 13:40 UTC (permalink / raw)
To: Pradeep Pragallapati, Manivannan Sadhasivam
Cc: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, martin.petersen,
andersson, konradybcio, taniya.das, dmitry.baryshkov,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
nitin.rawat, Konrad Dybcio, Abel Vesa
In-Reply-To: <e396bef2-e5bf-4e6d-98f4-37977d5d93ec@oss.qualcomm.com>
On 06/01/2026 14:00, Pradeep Pragallapati wrote:
>>
>>> + compatible = "qcom,x1e80100-ufshc",
>>> + "qcom,sm8550-ufshc",
>>> + "qcom,ufshc",
>>> + "jedec,ufs-2.0";
>>
>> Drop jedec compatible as Qcom UFS controller cannot fallback to generic ufshc
>> driver.
> "jedec,ufs-2.0" was set to const in dt-bindings, dropping now will lead
> to dtbs_check failures. is it ok, if i continue with it ?
No, it is not ok. You cannot have errors/warnings and I think it is
obvious that you need to fix everything, not only DTS.
Best regards,
Krzysztof
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* Re: [PATCH v4 12/25] scsi: ufs: mediatek: Remove vendor kernel quirks cruft
From: Peter Wang (王信友) @ 2026-01-06 13:25 UTC (permalink / raw)
To: chu.stanley@gmail.com, robh@kernel.org,
Chunfeng Yun (云春峰), kishon@kernel.org,
James.Bottomley@HansenPartnership.com, bvanassche@acm.org,
AngeloGioacchino Del Regno, neil.armstrong@linaro.org,
conor+dt@kernel.org, Chaotian Jing (井朝天),
lgirdwood@gmail.com, nicolas.frattaroli@collabora.com,
vkoul@kernel.org, krzk+dt@kernel.org, p.zabel@pengutronix.de,
alim.akhtar@samsung.com, matthias.bgg@gmail.com,
avri.altman@wdc.com, martin.petersen@oracle.com,
broonie@kernel.org
Cc: linux-scsi@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-phy@lists.infradead.org, linux-mediatek@lists.infradead.org,
Louis-Alexis Eyraud, kernel@collabora.com
In-Reply-To: <20251218-mt8196-ufs-v4-12-ddec7a369dd2@collabora.com>
On Thu, 2025-12-18 at 13:55 +0100, Nicolas Frattaroli wrote:
>
> Both ufs_mtk_vreg_fix_vcc and ufs_mtk_vreg_fix_vccqx look like they
> are
> vendor kernel hacks to work around existing downstream device trees.
> Mainline does not need or want them, so remove them.
>
Hi Nicolas,
This is a flexible approach to implement one software supporting
multiple
hardware configurations. Because you cannot guarantee that your SOC
will
always use UFS 2.0 or UFS 3.0, or that the PMIC you use will only have
one set.
Thanks
Peter
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