* Re: [PATCH v2 2/4] dt-bindings: usb: dwc2: Add support for Canaan K230 SoC
From: Rob Herring (Arm) @ 2026-01-15 8:30 UTC (permalink / raw)
To: Jiayu Du
Cc: vkoul, linux-usb, conor+dt, krzk+dt, linux-kernel, cyy, alex, pjw,
kingxukai, conor, aou, linux-riscv, palmer, neil.armstrong,
gaohan, linux-phy, gregkh, 18771902331, devicetree,
TroyMitchell988
In-Reply-To: <20260115064223.21926-3-jiayu.riscv@isrc.iscas.ac.cn>
On Thu, 15 Jan 2026 14:42:20 +0800, Jiayu Du wrote:
> Add 'canaan,k230-usb' compatible string with 'snps,dwc2' as fallback
> for the DWC2 IP which is used by Canaan K230.
>
> Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
> ---
> Documentation/devicetree/bindings/usb/dwc2.yaml | 3 +++
> 1 file changed, 3 insertions(+)
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/phy/canaan,k230-usb-phy.example.dtb: usb-phy@91585000 (canaan,k230-usb-phy): reg: [[0, 2438483968], [0, 1024]] is too long
from schema $id: http://devicetree.org/schemas/phy/canaan,k230-usb-phy.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.kernel.org/project/devicetree/patch/20260115064223.21926-3-jiayu.riscv@isrc.iscas.ac.cn
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
--
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^ permalink raw reply
* [PATCH v2 4/4] riscv: dts: canaan: Add syscon and USB nodes for K230
From: Jiayu Du @ 2026-01-15 6:42 UTC (permalink / raw)
To: conor
Cc: vkoul, neil.armstrong, gregkh, robh, krzk+dt, conor+dt, pjw,
palmer, aou, alex, jiayu.riscv, 18771902331, cyy, TroyMitchell988,
kingxukai, linux-phy, linux-usb, devicetree, linux-kernel,
linux-riscv, gaohan
In-Reply-To: <20260115064223.21926-1-jiayu.riscv@isrc.iscas.ac.cn>
Add top syscon and USB PHY subdevice nodes, USB0/USB1 dwc2 controller
to K230 DTSI, and enable UART0 and USB0/USB1 in DshanPI DT.
Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
---
.../boot/dts/canaan/k230-canmv-dshanpi.dts | 17 +++++++++
arch/riscv/boot/dts/canaan/k230.dtsi | 35 +++++++++++++++++++
2 files changed, 52 insertions(+)
diff --git a/arch/riscv/boot/dts/canaan/k230-canmv-dshanpi.dts b/arch/riscv/boot/dts/canaan/k230-canmv-dshanpi.dts
index 4f95b534ee87..55197cfc25b4 100644
--- a/arch/riscv/boot/dts/canaan/k230-canmv-dshanpi.dts
+++ b/arch/riscv/boot/dts/canaan/k230-canmv-dshanpi.dts
@@ -80,3 +80,20 @@ &uart0 {
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
+
+&usb0 {
+ vusb_d-supply = <&vdd_3v3>;
+ vusb_a-supply = <&vdd_1v8>;
+ status = "okay";
+};
+
+&usb1 {
+ dr_mode = "host";
+ vusb_d-supply = <&vdd_3v3>;
+ vusb_a-supply = <&vdd_1v8>;
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/canaan/k230.dtsi b/arch/riscv/boot/dts/canaan/k230.dtsi
index b815a65e02b9..6dcb086f7046 100644
--- a/arch/riscv/boot/dts/canaan/k230.dtsi
+++ b/arch/riscv/boot/dts/canaan/k230.dtsi
@@ -148,5 +148,40 @@ uart4: serial@91404000 {
reg-shift = <2>;
status = "disabled";
};
+
+ usb0: usb@91500000 {
+ compatible = "canaan,k230-usb", "snps,dwc2";
+ reg = <0x0 0x91500000 0x0 0x40000>;
+ interrupts = <173 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sysclk K230_HS_USB0_AHB_GATE>;
+ clock-names = "otg";
+ g-rx-fifo-size = <512>;
+ g-np-tx-fifo-size = <64>;
+ g-tx-fifo-size = <512 1024 64 64 64 64>;
+ phys = <&usbphy 0>;
+ phy-names = "usb2-phy";
+ status = "disabled";
+ };
+
+ usb1: usb@91540000 {
+ compatible = "canaan,k230-usb", "snps,dwc2";
+ reg = <0x0 0x91540000 0x0 0x40000>;
+ interrupts = <174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sysclk K230_HS_USB1_AHB_GATE>;
+ clock-names = "otg";
+ g-rx-fifo-size = <512>;
+ g-np-tx-fifo-size = <64>;
+ g-tx-fifo-size = <512 1024 64 64 64 64>;
+ phys = <&usbphy 1>;
+ phy-names = "usb2-phy";
+ status = "disabled";
+ };
+
+ usbphy: usb-phy@91585000 {
+ compatible = "canaan,k230-usb-phy";
+ reg = <0x0 0x91585000 0x0 0x400>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
};
};
--
2.52.0
--
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^ permalink raw reply related
* [PATCH v2 3/4] phy: usb: Add driver for Canaan K230 USB 2.0 PHY
From: Jiayu Du @ 2026-01-15 6:42 UTC (permalink / raw)
To: conor
Cc: vkoul, neil.armstrong, gregkh, robh, krzk+dt, conor+dt, pjw,
palmer, aou, alex, jiayu.riscv, 18771902331, cyy, TroyMitchell988,
kingxukai, linux-phy, linux-usb, devicetree, linux-kernel,
linux-riscv, gaohan
In-Reply-To: <20260115064223.21926-1-jiayu.riscv@isrc.iscas.ac.cn>
Add driver for the USB 2.0 PHY in Canaan K230 SoC, which supports PHY
initialization and power management.
Add Kconfig/Makefile under drivers/phy/canaan/.
Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
---
drivers/phy/Kconfig | 1 +
drivers/phy/Makefile | 1 +
drivers/phy/canaan/Kconfig | 14 ++
drivers/phy/canaan/Makefile | 2 +
drivers/phy/canaan/phy-k230-usb.c | 271 ++++++++++++++++++++++++++++++
5 files changed, 289 insertions(+)
create mode 100644 drivers/phy/canaan/Kconfig
create mode 100644 drivers/phy/canaan/Makefile
create mode 100644 drivers/phy/canaan/phy-k230-usb.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 678dd0452f0a..95e630749350 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -105,6 +105,7 @@ source "drivers/phy/allwinner/Kconfig"
source "drivers/phy/amlogic/Kconfig"
source "drivers/phy/broadcom/Kconfig"
source "drivers/phy/cadence/Kconfig"
+source "drivers/phy/canaan/Kconfig"
source "drivers/phy/freescale/Kconfig"
source "drivers/phy/hisilicon/Kconfig"
source "drivers/phy/ingenic/Kconfig"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index bfb27fb5a494..f07c68f2e283 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -17,6 +17,7 @@ obj-y += allwinner/ \
amlogic/ \
broadcom/ \
cadence/ \
+ canaan/ \
freescale/ \
hisilicon/ \
ingenic/ \
diff --git a/drivers/phy/canaan/Kconfig b/drivers/phy/canaan/Kconfig
new file mode 100644
index 000000000000..1ff8831846d5
--- /dev/null
+++ b/drivers/phy/canaan/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Phy drivers for Canaan platforms
+#
+config PHY_CANAAN_USB
+ tristate "Canaan USB2 PHY Driver"
+ depends on (ARCH_CANAAN || COMPILE_TEST) && OF
+ select GENERIC_PHY
+ help
+ Enable this driver to support the USB 2.0 PHY controller
+ on Canaan K230 RISC-V SoCs. This PHY controller
+ provides physical layer functionality for USB 2.0 devices.
+ If you have a Canaan K230 board and need USB 2.0 support,
+ say Y or M here.
diff --git a/drivers/phy/canaan/Makefile b/drivers/phy/canaan/Makefile
new file mode 100644
index 000000000000..d73857ba284e
--- /dev/null
+++ b/drivers/phy/canaan/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_PHY_CANAAN_USB) += phy-k230-usb.o
diff --git a/drivers/phy/canaan/phy-k230-usb.c b/drivers/phy/canaan/phy-k230-usb.c
new file mode 100644
index 000000000000..e4bd98aa4e89
--- /dev/null
+++ b/drivers/phy/canaan/phy-k230-usb.c
@@ -0,0 +1,271 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Canaan usb PHY driver
+ *
+ * Copyright (C) 2025 Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/io.h>
+#include <linux/of_address.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+
+#define CTL0_OFFSET 0x00
+#define CTL1_OFFSET 0x04
+#define TEST_CTL3_OFFSET 0x0c
+
+#define USB_IDPULLUP0 BIT(4)
+#define USB_DMPULLDOWN0 BIT(8)
+#define USB_DPPULLDOWN0 BIT(9)
+
+#define MAX_PHYS 2
+
+/* USB control register 0 in HiSysConfig system controller */
+/* PLL Integral Path Tune */
+#define USB_CTL0_PLLITUNE_MASK GENMASK(23, 22)
+
+/* PLL Proportional Path Tune */
+#define USB_CTL0_PLLPTUNE_MASK GENMASK(21, 18)
+
+/* PLL Bandwidth Adjustment */
+#define USB_CTL0_PLLBTUNE_MASK GENMASK(17, 17)
+
+/* VReg18 Bypass Control */
+#define USB_CTL0_VREGBYPASS_MASK GENMASK(16, 16)
+
+/* Retention Mode Enable */
+#define USB_CTL0_RETENABLEN_MASK GENMASK(15, 15)
+
+/* Reserved Request Input */
+#define USB_CTL0_RESREQIN_MASK GENMASK(14, 14)
+
+/* External VBUS Valid Select */
+#define USB_CTL0_VBUSVLDEXTSEL0_MASK GENMASK(13, 13)
+
+/* OTG Block Disable Control */
+#define USB_CTL0_OTGDISABLE0_MASK GENMASK(12, 12)
+
+/* Drive VBUS Enable */
+#define USB_CTL0_DRVVBUS0_MASK GENMASK(11, 11)
+
+/* Autoresume Mode Enable */
+#define USB_CTL0_AUTORSMENB0_MASK GENMASK(10, 10)
+
+/* HS Transceiver Asynchronous Control */
+#define USB_CTL0_HSXCVREXTCTL0_MASK GENMASK(9, 9)
+
+/* USB 1.1 Transmit Data */
+#define USB_CTL0_FSDATAEXT0_MASK GENMASK(8, 8)
+
+/* USB 1.1 SE0 Generation */
+#define USB_CTL0_FSSE0EXT0_MASK GENMASK(7, 7)
+
+/* USB 1.1 Data Enable */
+#define USB_CTL0_TXENABLEN0_MASK GENMASK(6, 6)
+
+/* Disconnect Threshold */
+#define USB_CTL0_COMPDISTUNE0_MASK GENMASK(5, 3)
+
+/* Squelch Threshold */
+#define USB_CTL0_SQRXTUNE0_MASK GENMASK(2, 0)
+
+/* USB control register 1 in HiSysConfig system controller */
+/* Data Detect Voltage */
+#define USB_CTL1_VDATREFTUNE0_MASK GENMASK(23, 22)
+
+/* VBUS Valid Threshold */
+#define USB_CTL1_OTGTUNE0_MASK GENMASK(21, 19)
+
+/* Transmitter High-Speed Crossover */
+#define USB_CTL1_TXHSXVTUNE0_MASK GENMASK(18, 17)
+
+/* FS/LS Source Impedance */
+#define USB_CTL1_TXFSLSTUNE0_MASK GENMASK(16, 13)
+
+/* HS DC Voltage Level */
+#define USB_CTL1_TXVREFTUNE0_MASK GENMASK(12, 9)
+
+/* HS Transmitter Rise/Fall Time */
+#define USB_CTL1_TXRISETUNE0_MASK GENMASK(8, 7)
+
+/* USB Source Impedance */
+#define USB_CTL1_TXRESTUNE0_MASK GENMASK(6, 5)
+
+/* HS Transmitter Pre-Emphasis Current Control */
+#define USB_CTL1_TXPREEMPAMPTUNE0_MASK GENMASK(4, 3)
+
+/* HS Transmitter Pre-Emphasis Duration Control */
+#define USB_CTL1_TXPREEMPPULSETUNE0_MASK GENMASK(2, 2)
+
+/* charging detection */
+#define USB_CTL1_CHRGSRCPUENB0_MASK GENMASK(1, 0)
+
+#define K230_PHY_CTL0_VAL \
+( \
+ FIELD_PREP(USB_CTL0_PLLITUNE_MASK, 0x0) | \
+ FIELD_PREP(USB_CTL0_PLLPTUNE_MASK, 0xc) | \
+ FIELD_PREP(USB_CTL0_PLLBTUNE_MASK, 0x1) | \
+ FIELD_PREP(USB_CTL0_VREGBYPASS_MASK, 0x1) | \
+ FIELD_PREP(USB_CTL0_RETENABLEN_MASK, 0x1) | \
+ FIELD_PREP(USB_CTL0_RESREQIN_MASK, 0x0) | \
+ FIELD_PREP(USB_CTL0_VBUSVLDEXTSEL0_MASK, 0x0) | \
+ FIELD_PREP(USB_CTL0_OTGDISABLE0_MASK, 0x0) | \
+ FIELD_PREP(USB_CTL0_DRVVBUS0_MASK, 0x1) | \
+ FIELD_PREP(USB_CTL0_AUTORSMENB0_MASK, 0x0) | \
+ FIELD_PREP(USB_CTL0_HSXCVREXTCTL0_MASK, 0x0) | \
+ FIELD_PREP(USB_CTL0_FSDATAEXT0_MASK, 0x0) | \
+ FIELD_PREP(USB_CTL0_FSSE0EXT0_MASK, 0x0) | \
+ FIELD_PREP(USB_CTL0_TXENABLEN0_MASK, 0x0) | \
+ FIELD_PREP(USB_CTL0_COMPDISTUNE0_MASK, 0x3) | \
+ FIELD_PREP(USB_CTL0_SQRXTUNE0_MASK, 0x3) \
+)
+
+#define K230_PHY_CTL1_VAL \
+( \
+ FIELD_PREP(USB_CTL1_VDATREFTUNE0_MASK, 0x1) | \
+ FIELD_PREP(USB_CTL1_OTGTUNE0_MASK, 0x3) | \
+ FIELD_PREP(USB_CTL1_TXHSXVTUNE0_MASK, 0x3) | \
+ FIELD_PREP(USB_CTL1_TXFSLSTUNE0_MASK, 0x3) | \
+ FIELD_PREP(USB_CTL1_TXVREFTUNE0_MASK, 0x3) | \
+ FIELD_PREP(USB_CTL1_TXRISETUNE0_MASK, 0x1) | \
+ FIELD_PREP(USB_CTL1_TXRESTUNE0_MASK, 0x1) | \
+ FIELD_PREP(USB_CTL1_TXPREEMPAMPTUNE0_MASK, 0x0) | \
+ FIELD_PREP(USB_CTL1_TXPREEMPPULSETUNE0_MASK, 0x0) | \
+ FIELD_PREP(USB_CTL1_CHRGSRCPUENB0_MASK, 0x0) \
+)
+struct k230_usb_phy_global {
+ u32 reg_test_offset[MAX_PHYS];
+ u32 reg_ctl_offset[MAX_PHYS];
+ void __iomem *base;
+};
+
+struct k230_usb_phy_instance {
+ struct k230_usb_phy_global *global;
+ int index;
+};
+
+static int k230_usb_phy_power_on(struct phy *_phy)
+{
+ struct k230_usb_phy_instance *phy_inst = phy_get_drvdata(_phy);
+ struct k230_usb_phy_global *global = phy_inst->global;
+ u32 val;
+
+ writel(K230_PHY_CTL0_VAL, global->base +
+ global->reg_ctl_offset[phy_inst->index] + CTL0_OFFSET);
+
+ writel(K230_PHY_CTL1_VAL, global->base +
+ global->reg_ctl_offset[phy_inst->index] + CTL1_OFFSET);
+
+ val = readl(global->base +
+ global->reg_test_offset[phy_inst->index] +
+ TEST_CTL3_OFFSET);
+
+ val |= USB_IDPULLUP0;
+ if (phy_inst->index == 1)
+ val |= (USB_DMPULLDOWN0 | USB_DPPULLDOWN0);
+ else
+ val &= ~(USB_DMPULLDOWN0 | USB_DPPULLDOWN0);
+
+ writel(val, global->base +
+ global->reg_test_offset[phy_inst->index] +
+ TEST_CTL3_OFFSET);
+
+ return 0;
+}
+
+static int k230_usb_phy_power_off(struct phy *_phy)
+{
+ struct k230_usb_phy_instance *phy_inst = phy_get_drvdata(_phy);
+ struct k230_usb_phy_global *global = phy_inst->global;
+ u32 val;
+
+ val = readl(global->base +
+ global->reg_test_offset[phy_inst->index] +
+ TEST_CTL3_OFFSET);
+
+ val &= ~(USB_DMPULLDOWN0 | USB_DPPULLDOWN0);
+
+ writel(val, global->base +
+ global->reg_test_offset[phy_inst->index] +
+ TEST_CTL3_OFFSET);
+
+ return 0;
+}
+
+static const struct phy_ops k230_usb_phy_ops = {
+ .power_on = k230_usb_phy_power_on,
+ .power_off = k230_usb_phy_power_off,
+ .owner = THIS_MODULE,
+};
+
+static struct phy *k230_usb_phy_xlate(struct device *dev,
+ const struct of_phandle_args *args)
+{
+ struct k230_usb_phy_global *global = dev_get_drvdata(dev);
+ struct k230_usb_phy_instance *phy_inst;
+ struct phy *phy;
+
+ if (args->args[0] >= MAX_PHYS)
+ return ERR_PTR(-EINVAL);
+
+ phy_inst = devm_kzalloc(dev, sizeof(*phy_inst), GFP_KERNEL);
+ if (!phy_inst)
+ return ERR_PTR(-ENOMEM);
+
+ phy_inst->global = global;
+ phy_inst->index = args->args[0];
+
+ phy = devm_phy_create(dev, NULL, &k230_usb_phy_ops);
+ if (IS_ERR(phy))
+ return ERR_PTR(PTR_ERR(phy));
+
+ phy_set_drvdata(phy, phy_inst);
+
+ return phy;
+}
+
+static int k230_usb_phy_probe(struct platform_device *pdev)
+{
+ struct k230_usb_phy_global *global;
+ struct device *dev = &pdev->dev;
+ struct phy_provider *provider;
+
+ global = devm_kzalloc(dev, sizeof(*global), GFP_KERNEL);
+ if (!global)
+ return -ENOMEM;
+ dev_set_drvdata(dev, global);
+
+ global->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(global->base))
+ return dev_err_probe(dev, PTR_ERR(global->base),
+ "ioremap failed\n");
+
+ global->reg_test_offset[0] = 0x70;
+ global->reg_ctl_offset[0] = 0xb0;
+ global->reg_test_offset[1] = 0x90;
+ global->reg_ctl_offset[1] = 0xb8;
+
+ provider = devm_of_phy_provider_register(dev, k230_usb_phy_xlate);
+
+ return 0;
+}
+
+static const struct of_device_id k230_usb_phy_of_match[] = {
+ { .compatible = "canaan,k230-usb-phy" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, k230_usb_phy_of_match);
+
+static struct platform_driver k230_usb_phy_driver = {
+ .probe = k230_usb_phy_probe,
+ .driver = {
+ .name = "k230-usb-phy",
+ .of_match_table = k230_usb_phy_of_match,
+ },
+};
+module_platform_driver(k230_usb_phy_driver);
+
+MODULE_DESCRIPTION("Canaan Kendryte K230 USB 2.0 PHY driver");
+MODULE_AUTHOR("Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>");
+MODULE_LICENSE("GPL");
--
2.52.0
--
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^ permalink raw reply related
* [PATCH v2 2/4] dt-bindings: usb: dwc2: Add support for Canaan K230 SoC
From: Jiayu Du @ 2026-01-15 6:42 UTC (permalink / raw)
To: conor
Cc: vkoul, neil.armstrong, gregkh, robh, krzk+dt, conor+dt, pjw,
palmer, aou, alex, jiayu.riscv, 18771902331, cyy, TroyMitchell988,
kingxukai, linux-phy, linux-usb, devicetree, linux-kernel,
linux-riscv, gaohan
In-Reply-To: <20260115064223.21926-1-jiayu.riscv@isrc.iscas.ac.cn>
Add 'canaan,k230-usb' compatible string with 'snps,dwc2' as fallback
for the DWC2 IP which is used by Canaan K230.
Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
---
Documentation/devicetree/bindings/usb/dwc2.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml
index 6c3a10991b8b..352487c6392a 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.yaml
+++ b/Documentation/devicetree/bindings/usb/dwc2.yaml
@@ -17,6 +17,9 @@ properties:
compatible:
oneOf:
- const: brcm,bcm2835-usb
+ - items:
+ - const: canaan,k230-usb
+ - const: snps,dwc2
- const: hisilicon,hi6220-usb
- const: ingenic,jz4775-otg
- const: ingenic,jz4780-otg
--
2.52.0
--
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^ permalink raw reply related
* [PATCH v2 1/4] dt-bindings: phy: Add Canaan K230 USB PHY
From: Jiayu Du @ 2026-01-15 6:42 UTC (permalink / raw)
To: conor
Cc: vkoul, neil.armstrong, gregkh, robh, krzk+dt, conor+dt, pjw,
palmer, aou, alex, jiayu.riscv, 18771902331, cyy, TroyMitchell988,
kingxukai, linux-phy, linux-usb, devicetree, linux-kernel,
linux-riscv, gaohan
In-Reply-To: <20260115064223.21926-1-jiayu.riscv@isrc.iscas.ac.cn>
K230 SoC USB PHY requires configuring registers for control and
configuration. Add USB phy bindings for K230 SoC.
Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
---
.../bindings/phy/canaan,k230-usb-phy.yaml | 35 +++++++++++++++++++
1 file changed, 35 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/canaan,k230-usb-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/canaan,k230-usb-phy.yaml b/Documentation/devicetree/bindings/phy/canaan,k230-usb-phy.yaml
new file mode 100644
index 000000000000..be54efd612ac
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/canaan,k230-usb-phy.yaml
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/canaan,k230-usb-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Canaan K230 USB2.0 PHY
+
+maintainers:
+ - Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
+
+properties:
+ compatible:
+ const: canaan,k230-usb-phy
+
+ reg:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ usbphy: usb-phy@91585000 {
+ compatible = "canaan,k230-usb-phy";
+ reg = <0x0 0x91585000 0x0 0x400>;
+ #phy-cells = <1>;
+ };
--
2.52.0
--
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^ permalink raw reply related
* [PATCH v2 0/4] Add USB support for Canaan K230
From: Jiayu Du @ 2026-01-15 6:42 UTC (permalink / raw)
To: conor
Cc: vkoul, neil.armstrong, gregkh, robh, krzk+dt, conor+dt, pjw,
palmer, aou, alex, jiayu.riscv, 18771902331, cyy, TroyMitchell988,
kingxukai, linux-phy, linux-usb, devicetree, linux-kernel,
linux-riscv, gaohan
Add support for the USB PHY and DWC2 IP which is used by Canaan K230,
and made relevant changes to the DTS.
This series is based on the initial 100ask K230 DshanPi series [1] which
is based on the clock and pinctrl series. Check the details in the link.
Link: https://lore.kernel.org/all/20260115060801.16819-1-jiayu.riscv@isrc.iscas.ac.cn/ [1]
Changes in v2:
- Fold the child into the parent in dtsi.
- Define one usbphy with phy-cells=1.
- Delete the clock of the usbphy as it is not needed.
- Link to v1: https://lore.kernel.org/all/20251230023725.15966-1-jiayu.riscv@isrc.iscas.ac.cn/
Jiayu Du (4):
dt-bindings: phy: Add Canaan K230 USB PHY
dt-bindings: usb: dwc2: Add support for Canaan K230 SoC
phy: usb: Add driver for Canaan K230 USB 2.0 PHY
riscv: dts: canaan: Add syscon and USB nodes for K230
.../bindings/phy/canaan,k230-usb-phy.yaml | 35 +++
.../devicetree/bindings/usb/dwc2.yaml | 3 +
.../boot/dts/canaan/k230-canmv-dshanpi.dts | 17 ++
arch/riscv/boot/dts/canaan/k230.dtsi | 35 +++
drivers/phy/Kconfig | 1 +
drivers/phy/Makefile | 1 +
drivers/phy/canaan/Kconfig | 14 +
drivers/phy/canaan/Makefile | 2 +
drivers/phy/canaan/phy-k230-usb.c | 271 ++++++++++++++++++
9 files changed, 379 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/canaan,k230-usb-phy.yaml
create mode 100644 drivers/phy/canaan/Kconfig
create mode 100644 drivers/phy/canaan/Makefile
create mode 100644 drivers/phy/canaan/phy-k230-usb.c
--
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^ permalink raw reply
* Re: [PATCH v2 1/2] dt-bindings: phy: ti,phy-usb3: convert to DT schema
From: Vinod Koul @ 2026-01-15 4:41 UTC (permalink / raw)
To: Charan Pedumuru
Cc: Neil Armstrong, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Kishon Vijay Abraham I, linux-phy, devicetree, linux-kernel
In-Reply-To: <b86695e3-9d61-4e9b-aed2-d2585d8646b5@gmail.com>
On 14-01-26, 20:16, Charan Pedumuru wrote:
>
>
> On 14-01-2026 19:46, Vinod Koul wrote:
> > On 07-01-26, 16:11, Charan Pedumuru wrote:
> >> Convert TI PIPE3 PHY binding to DT schema.
> >> Changes during conversion:
> >> - Define a new pattern 'pciephy' to match nodes defined in DT.
> >> - Drop obsolete "id" property from the schema.
> >>
> >> Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
> >> ---
> >> .../devicetree/bindings/phy/ti,phy-usb3.yaml | 127 +++++++++++++++++++++
> >> 1 file changed, 127 insertions(+)
> >>
> >> diff --git a/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml b/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml
> >> new file mode 100644
> >> index 000000000000..41b3828723ae
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml
> >> @@ -0,0 +1,127 @@
> >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> >> +%YAML 1.2
> >> +---
> >> +$id: http://devicetree.org/schemas/phy/ti,phy-usb3.yaml#
> >> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >> +
> >> +title: TI PIPE3 PHY Module
> >> +
> >> +maintainers:
> >> + - Kishon Vijay Abraham I <kishon@ti.com>
> >
> > That is not correct, please check the current people on TI for this.
>
> I checked the driver author and MAINTAINERS, I couldn't find anyone.
> No one seems to have updated the MAINTAINER.
Please chekc in git log about recent contributions from TI people
--
~Vinod
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^ permalink raw reply
* [PATCH v9 3/3] MAINTAINERS: Add ASPEED PCIe PHY driver
From: Jacky Chou @ 2026-01-15 3:35 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Joel Stanley, Andrew Jeffery
Cc: linux-aspeed, linux-phy, devicetree, linux-arm-kernel,
linux-kernel, Jacky Chou
In-Reply-To: <20260115-upstream_pcie_rc-v9-0-d6c82a1556a7@aspeedtech.com>
Add maintainer entry for ASPEED PCIe PHY driver.
Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
---
MAINTAINERS | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index cf755238c429..a1979c574759 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3844,6 +3844,14 @@ S: Maintained
F: Documentation/devicetree/bindings/crypto/aspeed,*
F: drivers/crypto/aspeed/
+ASPEED PCIE PHY DRIVER
+M: Jacky Chou <jacky_chou@aspeedtech.com>
+L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
+L: linux-phy@lists.infradead.org
+S: Maintained
+F: Documentation/devicetree/bindings/phy/aspeed,ast2600-pcie-phy.yaml
+F: drivers/phy/aspeed/pcie-phy-aspeed.c
+
ASPEED PECI CONTROLLER
M: Iwona Winiarska <iwona.winiarska@intel.com>
L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
--
2.34.1
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^ permalink raw reply related
* [PATCH v9 2/3] phy: aspeed: Add ASPEED PCIe PHY driver
From: Jacky Chou @ 2026-01-15 3:35 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Joel Stanley, Andrew Jeffery
Cc: linux-aspeed, linux-phy, devicetree, linux-arm-kernel,
linux-kernel, Jacky Chou
In-Reply-To: <20260115-upstream_pcie_rc-v9-0-d6c82a1556a7@aspeedtech.com>
Introduce support for Aspeed PCIe PHY controller available in
AST2600/2700.
Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
---
drivers/phy/Kconfig | 1 +
drivers/phy/Makefile | 1 +
drivers/phy/aspeed/Kconfig | 14 +++
drivers/phy/aspeed/Makefile | 2 +
drivers/phy/aspeed/phy-aspeed-pcie.c | 194 +++++++++++++++++++++++++++++++++++
5 files changed, 212 insertions(+)
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 678dd0452f0a..f6a8f06fd244 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -103,6 +103,7 @@ config PHY_NXP_PTN3222
source "drivers/phy/allwinner/Kconfig"
source "drivers/phy/amlogic/Kconfig"
+source "drivers/phy/aspeed/Kconfig"
source "drivers/phy/broadcom/Kconfig"
source "drivers/phy/cadence/Kconfig"
source "drivers/phy/freescale/Kconfig"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index bfb27fb5a494..18990c87dfb0 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_PHY_AIROHA_PCIE) += phy-airoha-pcie.o
obj-$(CONFIG_PHY_NXP_PTN3222) += phy-nxp-ptn3222.o
obj-y += allwinner/ \
amlogic/ \
+ aspeed/ \
broadcom/ \
cadence/ \
freescale/ \
diff --git a/drivers/phy/aspeed/Kconfig b/drivers/phy/aspeed/Kconfig
new file mode 100644
index 000000000000..f7aad553f3fd
--- /dev/null
+++ b/drivers/phy/aspeed/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Phy drivers for Aspeed platforms
+#
+config PHY_ASPEED_PCIE
+ tristate "ASPEED PCIe PHY driver"
+ select GENERIC_PHY
+ depends on ARCH_ASPEED
+ help
+ This option enables support for the ASPEED PCIe PHY driver.
+ The driver provides the necessary interface to control and
+ configure the PCIe PHY hardware found on ASPEED SoCs.
+ It is required for proper operation of PCIe devices on
+ platforms using ASPEED chips.
diff --git a/drivers/phy/aspeed/Makefile b/drivers/phy/aspeed/Makefile
new file mode 100644
index 000000000000..3edce7f522e1
--- /dev/null
+++ b/drivers/phy/aspeed/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_PHY_ASPEED_PCIE) += phy-aspeed-pcie.o
diff --git a/drivers/phy/aspeed/phy-aspeed-pcie.c b/drivers/phy/aspeed/phy-aspeed-pcie.c
new file mode 100644
index 000000000000..0f8ca7bf69b5
--- /dev/null
+++ b/drivers/phy/aspeed/phy-aspeed-pcie.c
@@ -0,0 +1,194 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 Aspeed Technology Inc.
+ */
+
+#include <linux/phy/pcie.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+
+/* AST2600 PCIe Host Controller Registers */
+#define PEHR_GLOBAL 0x30
+#define AST2600_PORT_TYPE_MASK GENMASK(5, 4)
+#define AST2600_PORT_TYPE(x) FIELD_PREP(AST2600_PORT_TYPE_MASK, x)
+#define PEHR_LOCK 0x7c
+#define PCIE_UNLOCK 0xa8
+
+/* AST2700 PEHR */
+#define PEHR_MISC_58 0x58
+#define LOCAL_SCALE_SUP BIT(0)
+#define PEHR_MISC_5C 0x5c
+#define CONFIG_RC_DEVICE BIT(30)
+#define PEHR_MISC_60 0x60
+#define AST2700_PORT_TYPE_MASK GENMASK(7, 4)
+#define PORT_TYPE_ROOT 0x4
+#define PEHR_MISC_70 0x70
+#define POSTED_DATA_CREDITS(x) FIELD_PREP(GENMASK(15, 0), x)
+#define POSTED_HEADER_CREDITS(x) FIELD_PREP(GENMASK(27, 16), x)
+#define PEHR_MISC_78 0x78
+#define COMPLETION_DATA_CREDITS(x) FIELD_PREP(GENMASK(15, 0), x)
+#define COMPLETION_HEADER_CREDITS(x) FIELD_PREP(GENMASK(27, 16), x)
+
+/**
+ * struct aspeed_pcie_phy - PCIe PHY information
+ * @dev: pointer to device structure
+ * @reg: PCIe host register base address
+ * @phy: pointer to PHY structure
+ * @platform: platform specific information
+ */
+struct aspeed_pcie_phy {
+ struct device *dev;
+ void __iomem *reg;
+ struct phy *phy;
+ const struct aspeed_pcie_phy_platform *platform;
+};
+
+/**
+ * struct aspeed_pcie_phy_platform - Platform information
+ * @phy_ops: phy operations
+ */
+struct aspeed_pcie_phy_platform {
+ const struct phy_ops *phy_ops;
+};
+
+static int ast2600_phy_init(struct phy *phy)
+{
+ struct aspeed_pcie_phy *pcie_phy = phy_get_drvdata(phy);
+
+ writel(PCIE_UNLOCK, pcie_phy->reg + PEHR_LOCK);
+
+ return 0;
+}
+
+static int ast2600_phy_set_mode(struct phy *phy, enum phy_mode mode,
+ int submode)
+{
+ struct aspeed_pcie_phy *pcie_phy = phy_get_drvdata(phy);
+
+ switch (submode) {
+ case PHY_MODE_PCIE_RC:
+ writel(AST2600_PORT_TYPE(0x3), pcie_phy->reg + PEHR_GLOBAL);
+ break;
+ default:
+ dev_err(&phy->dev, "Unsupported submode %d\n", submode);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct phy_ops ast2600_phy_ops = {
+ .init = ast2600_phy_init,
+ .set_mode = ast2600_phy_set_mode,
+ .owner = THIS_MODULE,
+};
+
+static int ast2700_phy_init(struct phy *phy)
+{
+ struct aspeed_pcie_phy *pcie_phy = phy_get_drvdata(phy);
+
+ writel(POSTED_DATA_CREDITS(0xc0) | POSTED_HEADER_CREDITS(0xa),
+ pcie_phy->reg + PEHR_MISC_70);
+ writel(COMPLETION_DATA_CREDITS(0x30) | COMPLETION_HEADER_CREDITS(0x8),
+ pcie_phy->reg + PEHR_MISC_78);
+ writel(LOCAL_SCALE_SUP, pcie_phy->reg + PEHR_MISC_58);
+
+ return 0;
+}
+
+static int ast2700_phy_set_mode(struct phy *phy, enum phy_mode mode,
+ int submode)
+{
+ struct aspeed_pcie_phy *pcie_phy = phy_get_drvdata(phy);
+ u32 cfg_val;
+
+ switch (submode) {
+ case PHY_MODE_PCIE_RC:
+ writel(CONFIG_RC_DEVICE, pcie_phy->reg + PEHR_MISC_5C);
+ cfg_val = readl(pcie_phy->reg + PEHR_MISC_60);
+ FIELD_MODIFY(AST2700_PORT_TYPE_MASK, &cfg_val,
+ PORT_TYPE_ROOT);
+ writel(cfg_val, pcie_phy->reg + PEHR_MISC_60);
+ break;
+ default:
+ dev_err(&phy->dev, "Unsupported submode %d\n", submode);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct phy_ops ast2700_phy_ops = {
+ .init = ast2700_phy_init,
+ .set_mode = ast2700_phy_set_mode,
+ .owner = THIS_MODULE,
+};
+
+const struct aspeed_pcie_phy_platform pcie_phy_ast2600 = {
+ .phy_ops = &ast2600_phy_ops,
+};
+
+const struct aspeed_pcie_phy_platform pcie_phy_ast2700 = {
+ .phy_ops = &ast2700_phy_ops,
+};
+
+static int aspeed_pcie_phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct phy_provider *phy_provider;
+ struct aspeed_pcie_phy *pcie_phy;
+ const struct aspeed_pcie_phy_platform *md;
+
+ md = of_device_get_match_data(dev);
+ if (!md)
+ return -ENODEV;
+
+ pcie_phy = devm_kzalloc(dev, sizeof(*pcie_phy), GFP_KERNEL);
+ if (!pcie_phy)
+ return -ENOMEM;
+
+ pcie_phy->reg = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(pcie_phy->reg))
+ return PTR_ERR(pcie_phy->reg);
+
+ pcie_phy->dev = dev;
+ pcie_phy->platform = md;
+
+ pcie_phy->phy = devm_phy_create(dev, dev->of_node,
+ pcie_phy->platform->phy_ops);
+ if (IS_ERR(pcie_phy->phy))
+ return dev_err_probe(dev, PTR_ERR(pcie_phy->phy),
+ "failed to create PHY\n");
+
+ phy_set_drvdata(pcie_phy->phy, pcie_phy);
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+ return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct of_device_id aspeed_pcie_phy_of_match_table[] = {
+ {
+ .compatible = "aspeed,ast2600-pcie-phy",
+ .data = &pcie_phy_ast2600,
+ },
+ {
+ .compatible = "aspeed,ast2700-pcie-phy",
+ .data = &pcie_phy_ast2700,
+ },
+ { },
+};
+MODULE_DEVICE_TABLE(of, aspeed_pcie_phy_of_match_table);
+
+static struct platform_driver aspeed_pcie_driver = {
+ .probe = aspeed_pcie_phy_probe,
+ .driver = {
+ .name = "aspeed-pcie-phy",
+ .of_match_table = aspeed_pcie_phy_of_match_table,
+ },
+};
+
+module_platform_driver(aspeed_pcie_driver);
+
+MODULE_AUTHOR("Jacky Chou <jacky_chou@aspeedtech.com>");
+MODULE_DESCRIPTION("ASPEED PCIe PHY");
+MODULE_LICENSE("GPL");
--
2.34.1
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^ permalink raw reply related
* [PATCH v9 1/3] dt-bindings: phy: aspeed: Add ASPEED PCIe PHY
From: Jacky Chou @ 2026-01-15 3:35 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Joel Stanley, Andrew Jeffery
Cc: linux-aspeed, linux-phy, devicetree, linux-arm-kernel,
linux-kernel, Jacky Chou
In-Reply-To: <20260115-upstream_pcie_rc-v9-0-d6c82a1556a7@aspeedtech.com>
Introduce device-binding for ASPEED AST2600/2700 PCIe PHY.
The PCIe PHY is used for PCIe RC to configure as RC mode.
Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
---
.../bindings/phy/aspeed,ast2600-pcie-phy.yaml | 42 ++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/aspeed,ast2600-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/aspeed,ast2600-pcie-phy.yaml
new file mode 100644
index 000000000000..71a5cd91fb3f
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/aspeed,ast2600-pcie-phy.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/aspeed,ast2600-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ASPEED PCIe PHY
+
+maintainers:
+ - Jacky Chou <jacky_chou@aspeedtech.com>
+
+description:
+ The ASPEED PCIe PHY provides the physical layer functionality for PCIe
+ controllers in the SoC.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - aspeed,ast2600-pcie-phy
+ - aspeed,ast2700-pcie-phy
+
+ reg:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ phy@1e6ed200 {
+ compatible = "aspeed,ast2600-pcie-phy";
+ reg = <0x1e6ed200 0x100>;
+ #phy-cells = <0>;
+ };
--
2.34.1
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^ permalink raw reply related
* [PATCH v9 0/3] Add ASPEED PCIe PHY support
From: Jacky Chou @ 2026-01-15 3:35 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Joel Stanley, Andrew Jeffery
Cc: linux-aspeed, linux-phy, devicetree, linux-arm-kernel,
linux-kernel, Jacky Chou
This patch series adds support for the ASPEED PCIe PHY,
including device tree bindings and PCIe PHY driver.
The patches introduce the necessary device tree nodes.
Summary of changes:
- Add device tree binding documents for ASPEED PCIe PHY
- Update MAINTAINERS for new bindings and driver
- Implement ASPEED PCIe PHY driver
This series has been tested on AST2600/AST2700 platforms and enables PCIe device
enumeration and operation.
Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
---
Changes in v9:
- Remove '[v8,2/4] ARM: dts: aspeed-g6: Add PCIe RC and PCIe PHY node'
and send it separately.
- Use FIELD_MODIFY to configure register.
- Link to v8: https://lore.kernel.org/r/20251230-upstream_pcie_rc-v8-0-03598cdd80cd@aspeedtech.com
Changes in v8:
- Update the title of cover letter
- Remove 'default y' from Kconfig
- Change 'PHY:' to 'phy:' in the title of ASPEED PCIe PHY commit.
- Remove unnecessary headers from phy-aspeed-pcie.c.
- Add ASPEED PCIe PHY MAINTAINERS
- Remove applied patches
[v7,2/7] dt-bindings: PCI: Add ASPEED PCIe RC support
[v7,5/7] PCI: Add FMT, TYPE and CPL status definition for TLP header
[v7,6/7] PCI: aspeed: Add ASPEED PCIe RC driver
[v7,7/7] MAINTAINERS: Add ASPEED PCIe RC driver
- Link to v7: https://lore.kernel.org/r/20251216-upstream_pcie_rc-v7-0-4aeb0f53c4ce@aspeedtech.com
Changes in v7:
- Add PCIe port into aspeed,ast2600-pci.yaml.
- Remove aspeed_pcie_init_ports() and merge aspeed_pcie_port_init() to
aspeed_pcie_parse_port()
- Refactor aspeed remap pcie addr to aspeed_pcie_map_ranges()
- Link to v6: https://lore.kernel.org/r/20251201-upstream_pcie_rc-v6-0-8c8800c56b16@aspeedtech.com
Changes in v6:
- Refer to pci-cpi-bridge.yaml to update aspeed,ast2600-pcie.yaml and
the pcie node of aspeed-g6.dtsi.
- 'dt-bindings: pinctrl: aspeed,ast2600-pinctrl: Add PCIe RC PERST#
group' have applied, remove it from this version.
- Adjust the defnitions in pci.h.
- Link to v5: https://lore.kernel.org/r/20251117-upstream_pcie_rc-v5-0-b4a198576acf@aspeedtech.com
Changes in v5:
- Remove legacy-interrupt-controller and the INTx points to pcie node itself.
- Correct bar mapping description and implementation to PCIe address
configuration in pcie-aspeed.c driver.
- Link to v4: https://lore.kernel.org/r/20251027095825.181161-1-jacky_chou@aspeedtech.com/
Changes in v4:
- Remove aspeed,ast2700-pcie-cfg.yaml
- Add more descriptions for AST2600 PCIe RC in aspeed,ast2600-pcie.yaml
- Change interrupt-controller to legacy-interrupt-controller in yaml
and dtsi
- Remove msi-parent property in yaml and dtsi
- Modify the bus range to starting from 0x00 in aspeed-g6.dtsi
- Fixed the typo on MODULE_DEVICE_TABLE() in phy-aspeed-pcie.c
- Add PCIE_CPL_STS_SUCCESS definition in pci/pci.h
- Add prefix ASPEED_ for register definition in RC driver
- Add a flag to indicate clear msi status twice for AST2700 workaround
- Remove getting domain number
- Remove scanning AST2600 HOST bridge on device number 0
- Remove all codes about CONFIG_PCI_MSI
- Get root but number from resouce list by IORESOURCE_BUS
- Change module_platform_driver to builtin_platform_driver
- Link to v3: https://lore.kernel.org/r/20250901055922.1553550-1-jacky_chou@aspeedtech.com/
Changes in v3:
- Add ASPEED PCIe PHY driver
- Remove the aspeed,pciecfg property from AST2600 RC node, merged into RC node
- Update the binding doc for aspeed,ast2700-pcie-cfg to reflect the changes
- Update the binding doc for aspeed,ast2600-pcie to reflect the changes
- Update the binding doc for aspeed,ast2600-pinctrl to reflect the changes
- Update the device tree source to reflect the changes
- Adjusted the use of mutex in RC drivers to use GRAND
- Updated from reviewer comments
- Link to v2: https://lore.kernel.org/r/20250715034320.2553837-1-jacky_chou@aspeedtech.com/
Changes in v2:
- Moved ASPEED PCIe PHY yaml binding to `soc/aspeed` directory and
changed it as syscon
- Added `MAINTAINERS` entry for the new PCIe RC driver
- Updated device tree bindings to reflect the new structure
- Refactored configuration read and write functions to main bus and
child bus ops
- Refactored initialization to implement multiple ports support
- Added PCIe FMT and TYPE definitions for TLP header in
`include/uapi/linux/pci_regs.h`
- Updated from reviewer comments
- Link to v1: https://lore.kernel.org/r/20250613033001.3153637-1-jacky_chou@aspeedtech.com/
---
Jacky Chou (3):
dt-bindings: phy: aspeed: Add ASPEED PCIe PHY
phy: aspeed: Add ASPEED PCIe PHY driver
MAINTAINERS: Add ASPEED PCIe PHY driver
.../bindings/phy/aspeed,ast2600-pcie-phy.yaml | 42 +++++
MAINTAINERS | 8 +
drivers/phy/Kconfig | 1 +
drivers/phy/Makefile | 1 +
drivers/phy/aspeed/Kconfig | 14 ++
drivers/phy/aspeed/Makefile | 2 +
drivers/phy/aspeed/phy-aspeed-pcie.c | 194 +++++++++++++++++++++
7 files changed, 262 insertions(+)
---
base-commit: 944aacb68baf7624ab8d277d0ebf07f025ca137c
change-id: 20251103-upstream_pcie_rc-8445759db813
Best regards,
--
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^ permalink raw reply
* Re: [PATCH 0/5] PCI: qcom: Add link retention support
From: Qiang Yu @ 2026-01-15 2:16 UTC (permalink / raw)
To: Krishna Chaitanya Chundru
Cc: Vinod Koul, Neil Armstrong, Philipp Zabel, Jingoo Han,
Manivannan Sadhasivam, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas,
linux-arm-msm, linux-phy, linux-kernel, linux-pci
In-Reply-To: <20260109-link_retain-v1-0-7e6782230f4b@oss.qualcomm.com>
On Fri, Jan 09, 2026 at 12:51:05PM +0530, Krishna Chaitanya Chundru wrote:
> This patch series introduces support for retaining the PCIe link across
> bootloader and kernel handoff on Qualcomm platforms, specifically
> X1E80100. The goal is to reduce boot time and avoid unnecessary link
> reinitialization when the link is already up.
>
> We are not enabling link retantion support for all the targets, as there
> is no guarantee that the bootloader on all targets has initialized the
> PCIe link in max supported speed. So we are enabling for hamoa & glymur
> target only for now based on the config flag.
>
> If the link is up and has link_retain is set to true in the
> ithe driver config data then enable retain logic in the controller.
>
> In phy as we already have skip init logic, the phy patch uses same
> assumption that if there is phy no csr and bootloader has done the init
> then driver can skip resetting the phy when phy status indicates it is
> up.
>
> Problem:-
> 1) As part of late init calls of clock & GENPD(for power domains) the
> framework is disabling all the unvoted resources by that time and also
> there is no sync state to keep them enabled till the probe is completed.
> Due to dependencies with regulators and phy, qcom pcie probe is happening
> after late init which is causing the resources(clocks & power domains) to
> be off which causes the link to go down. To avoid this we need to use these
> two kernel command line arguments (clk_ignore_unused & pd_ignore_unused)
> to skip disabling clocks and gendp power domains as part of late init
> for initial version. Once it is resolved we can avoid those kernel command
> line arguments.
>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Tested on Hamoa QCP and Glymur CRD, so
Tested-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> ---
> Krishna Chaitanya Chundru (5):
> phy: qcom: qmp-pcie: Skip PHY reset if already up
> PCI: dwc: Add support for retaining link during host init
> PCI: qcom: Keep PERST# GPIO state as-is during probe
> PCI: qcom: Add link retention support
> PCI: qcom: enable Link retain logic for Hamoa
>
> drivers/pci/controller/dwc/pcie-designware-host.c | 11 ++--
> drivers/pci/controller/dwc/pcie-designware.h | 1 +
> drivers/pci/controller/dwc/pcie-qcom.c | 62 ++++++++++++++++++++---
> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 28 ++++++----
> 4 files changed, 83 insertions(+), 19 deletions(-)
> ---
> base-commit: fc065cadc7ed048bedbb23cb6b7c4475198f431c
> change-id: 20251001-link_retain-f181307947e4
>
> Best regards,
> --
> Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
>
>
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^ permalink raw reply
* RE: [PATCH] phy: freescale: imx8qm-hsio: fix NULL pointer dereference
From: Hongxing Zhu @ 2026-01-15 1:52 UTC (permalink / raw)
To: Thomas Richard, Vinod Koul, Neil Armstrong, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, Frank Li
Cc: Thomas Petazzoni, linux-phy@lists.infradead.org,
imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
In-Reply-To: <20260114-phy-fsl-imx8qm-hsio-fix-null-pointer-dereference-v1-1-730e941be464@bootlin.com>
> -----Original Message-----
> From: Thomas Richard <thomas.richard@bootlin.com>
> Sent: 2026年1月15日 0:50
> To: Vinod Koul <vkoul@kernel.org>; Neil Armstrong
> <neil.armstrong@linaro.org>; Shawn Guo <shawnguo@kernel.org>; Sascha
> Hauer <s.hauer@pengutronix.de>; Pengutronix Kernel Team
> <kernel@pengutronix.de>; Fabio Estevam <festevam@gmail.com>; Frank Li
> <frank.li@nxp.com>; Hongxing Zhu <hongxing.zhu@nxp.com>
> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>;
> linux-phy@lists.infradead.org; imx@lists.linux.dev;
> linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; Thomas
> Richard <thomas.richard@bootlin.com>
> Subject: [PATCH] phy: freescale: imx8qm-hsio: fix NULL pointer dereference
>
> [You don't often get email from thomas.richard@bootlin.com. Learn why this is
> important at https://aka.ms/LearnAboutSenderIdentification ]
>
> During the probe the refclk_pad pointer is set to NULL if the
> 'fsl,refclk-pad-mode' property is not defined in the devicetree node. But in
> imx_hsio_configure_clk_pad() this pointer is unconditionally used which could
> result in a NULL pointer dereference. So check the pointer before to use it.
>
> Fixes: 82c56b6dd24f ("phy: freescale: imx8qm-hsio: Add i.MX8QM HSIO PHY
> driver support")
> Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
Thanks for your patch.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Best Regards
Richard Zhu
> ---
> drivers/phy/freescale/phy-fsl-imx8qm-hsio.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
> b/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
> index 977d21d753a5..279b8ac7822d 100644
> --- a/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
> +++ b/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
> @@ -251,7 +251,7 @@ static void imx_hsio_configure_clk_pad(struct phy
> *phy)
> struct imx_hsio_lane *lane = phy_get_drvdata(phy);
> struct imx_hsio_priv *priv = lane->priv;
>
> - if (strncmp(priv->refclk_pad, "output", 6) == 0) {
> + if (priv->refclk_pad && strncmp(priv->refclk_pad, "output", 6)
> + == 0) {
> pll = true;
> regmap_update_bits(priv->misc, HSIO_CTRL0,
> HSIO_IOB_A_0_TXOE |
> HSIO_IOB_A_0_M1M0_MASK,
>
> ---
> base-commit: c537e12daeecaecdcd322c56a5f70659d2de7bde
> change-id:
> 20260114-phy-fsl-imx8qm-hsio-fix-null-pointer-dereference-67b110635f77
>
> Best regards,
> --
> Thomas Richard <thomas.richard@bootlin.com>
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^ permalink raw reply
* Re: [PATCH 0/5] Add calibration for Synopsys PCIe PHY and Controller
From: Shawn Lin @ 2026-01-15 0:41 UTC (permalink / raw)
To: Niklas Cassel
Cc: shawn.lin, Manivannan Sadhasivam, Bjorn Helgaas, Vinod Koul,
linux-pci, linux-rockchip, linux-phy, Heiko Stuebner,
Neil Armstrong, Sebastian Reichel
In-Reply-To: <aWe5s5mqFt26lRGL@ryzen>
在 2026/01/14 星期三 23:43, Niklas Cassel 写道:
> On Wed, Dec 24, 2025 at 03:10:05PM +0800, Shawn Lin wrote:
>>
>> Currently, when pcie-dw-rockchip uses the Synopsys PHY, it relies on
>> the phy_init() callback of the phy-rockchip-snps-pcie3 driver to
>> perform calibration. This is incorrect because the controller is
>> still held in reset at that time, preventing the PHY from accurately
>> reflecting the actual PLL lock and calibration status.
>
> Hello Shawn,
>
> I can see that you move the calibration code from .phy_init() to
> .phy_calibrate().
>
> And I understandthat the controller is still held in reset.
>
> I understand that the the PHY calibration is supposed to be done
> when the controller is not held in reset, and that alone is
> enough to warrant a fix.
Sure.
>
> The Synopsys Gen3 PHY is used in e.g. Rock5b, and link training
> currently works fine with this PHY, so what is the actual
It just happended to work as in most cases, the calibration finished
very quickly after controller is not held in reset.
> implications of performing the PHY calibration when the controller
> is held in reset?
>
> Will it somehow it improve signal integrity?
>
Performing the PHY calibration when the controller is held
in reset is the wrong way. If the refclk or PHY power supply isn't
ready, the bogus calibration still passes, then the system will get
stuck when accessing DBI. So performing the PHY calibration must be done
after controller quit the reset state.
>
> Kind regards,
> Niklas
>
>>
>> To fix this, this series:
>> 1. Calls phy_calibrate() in the pcie-dw-rockchip driver (if supported)
>> after the controller is out of reset, ensuring the PHY can
>> properly synchronize with the controller state.
>> 2. Adds the necessary calibration support in the Synopsys PHY driver
>> to implement this callback.
>
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^ permalink raw reply
* Re: [PATCH 3/5] phy: rockchip-snps-pcie3: Increase sram init timeout
From: Shawn Lin @ 2026-01-15 0:30 UTC (permalink / raw)
To: Vinod Koul
Cc: shawn.lin, Manivannan Sadhasivam, Bjorn Helgaas, linux-pci,
linux-rockchip, linux-phy, Heiko Stuebner, Neil Armstrong,
Sebastian Reichel
In-Reply-To: <aWeaUG45FWtdgscG@vaman>
在 2026/01/14 星期三 21:29, Vinod Koul 写道:
> On 24-12-25, 15:10, Shawn Lin wrote:
>> Per massive test, 500us is not enough for all chips, increase it
>> to 20000us for worse case recommended.
>>
>> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
>> ---
>>
>> drivers/phy/rockchip/phy-rockchip-snps-pcie3.c | 10 +++++++---
>> 1 file changed, 7 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
>> index 9933cda..f5a5d0af 100644
>> --- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
>> +++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
>> @@ -19,6 +19,9 @@
>> #include <linux/regmap.h>
>> #include <linux/reset.h>
>>
>> +/* Common definition */
>> +#define RK_SRAM_INIT_TIMEOUT_US 20000
>> +
>> /* Register for RK3568 */
>> #define GRF_PCIE30PHY_CON1 0x4
>> #define GRF_PCIE30PHY_CON6 0x18
>> @@ -28,6 +31,7 @@
>> #define GRF_PCIE30PHY_WR_EN (0xf << 16)
>> #define SRAM_INIT_DONE(reg) (reg & BIT(14))
>>
>> +
>
> why this empty line here?
>
Oops, will fix it.
>> #define RK3568_BIFURCATION_LANE_0_1 BIT(0)
>>
>> /* Register for RK3588 */
>> @@ -134,7 +138,7 @@ static int rockchip_p3phy_rk3568_calibrate(struct rockchip_p3phy_priv *priv)
>> ret = regmap_read_poll_timeout(priv->phy_grf,
>> GRF_PCIE30PHY_STATUS0,
>> reg, SRAM_INIT_DONE(reg),
>> - 0, 500);
>> + 0, RK_SRAM_INIT_TIMEOUT_US);
>> if (ret)
>> dev_err(&priv->phy->dev, "lock failed 0x%x, check input refclk and power supply\n",
>> reg);
>> @@ -203,11 +207,11 @@ static int rockchip_p3phy_rk3588_calibrate(struct rockchip_p3phy_priv *priv)
>> ret = regmap_read_poll_timeout(priv->phy_grf,
>> RK3588_PCIE3PHY_GRF_PHY0_STATUS1,
>> reg, RK3588_SRAM_INIT_DONE(reg),
>> - 0, 500);
>> + 0, RK_SRAM_INIT_TIMEOUT_US);
>> ret |= regmap_read_poll_timeout(priv->phy_grf,
>> RK3588_PCIE3PHY_GRF_PHY1_STATUS1,
>> reg, RK3588_SRAM_INIT_DONE(reg),
>> - 0, 500);
>> + 0, RK_SRAM_INIT_TIMEOUT_US);
>> if (ret)
>> dev_err(&priv->phy->dev, "lock failed 0x%x, check input refclk and power supply\n",
>> reg);
>> --
>> 2.7.4
>
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^ permalink raw reply
* Re: [PATCH net-next 01/14] net: stmmac: qcom-ethqos: remove mac_base
From: Vladimir Oltean @ 2026-01-14 20:48 UTC (permalink / raw)
To: Russell King (Oracle)
Cc: Andrew Lunn, Heiner Kallweit, Alexandre Torgue, Andrew Lunn,
David S. Miller, Eric Dumazet, Jakub Kicinski, Konrad Dybcio,
linux-arm-kernel, linux-arm-msm, linux-phy, linux-stm32,
Maxime Coquelin, Mohd Ayaan Anwar, Neil Armstrong, netdev,
Paolo Abeni, Vinod Koul
In-Reply-To: <E1vg4vi-00000003SFh-0Abn@rmk-PC.armlinux.org.uk>
On Wed, Jan 14, 2026 at 05:45:14PM +0000, Russell King (Oracle) wrote:
> Since the blamed commit, ethqos->mac_base is only written, never
> read. Let's remove it.
>
> Fixes: 9b443e58a896 ("net: stmmac: qcom-ethqos: remove MAC_CTRL_REG modification")
> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
> ---
I think we reserve the use of Fixes: tags for user-visible issues, not
cleanup of dangling variables. You can move the sha1sum and its commit
title in the main commit message body and delete that tag.
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^ permalink raw reply
* Re: [PATCH net-next 03/14] phy: qcom-sgmii-eth: add .set_mode() and .validate() methods
From: Vladimir Oltean @ 2026-01-14 19:02 UTC (permalink / raw)
To: Russell King (Oracle)
Cc: Andrew Lunn, Heiner Kallweit, Alexandre Torgue, Andrew Lunn,
David S. Miller, Eric Dumazet, Jakub Kicinski, Konrad Dybcio,
linux-arm-kernel, linux-arm-msm, linux-phy, linux-stm32,
Maxime Coquelin, Mohd Ayaan Anwar, Neil Armstrong, netdev,
Paolo Abeni, Vinod Koul
In-Reply-To: <aWfmpq-dJ-mUCvz1@shell.armlinux.org.uk>
On Wed, Jan 14, 2026 at 06:55:34PM +0000, Russell King (Oracle) wrote:
> On Wed, Jan 14, 2026 at 08:47:05PM +0200, Vladimir Oltean wrote:
> > On Wed, Jan 14, 2026 at 05:45:24PM +0000, Russell King (Oracle) wrote:
> > > qcom-sgmii-eth is an Ethernet SerDes supporting only Ethernet mode
> > > using SGMII, 1000BASE-X and 2500BASE-X.
> > >
> > > Add an implementation of the .set_mode() method, which can be used
> > > instead of or as well as the .set_speed() method. The Ethernet
> > > interface modes mentioned above all have a fixed data rate, so
> > > setting the mode is sufficient to fully specify the operating
> > > parameters.
> > >
> > > Add an implementation of the .validate() method, which will be
> > > necessary to allow discovery of the SerDes capabilities for platform
> > > independent SerDes support in the stmmac netowrk driver.
> >
> > s/netowrk/network/
> >
> > >
> > > Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
> > > ---
> >
> > Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
>
> According to patchwork (I forgot the RFC tag on the patches) it needs
> linux/phy.h included. Plesae let me know if you'd like me to retain
> your r-b. Thanks.
Ah, ok, I thought that the SPEED_* macros are also phylib-specific like
PHY_INTERFACE_MODE_*, and hence, the phylib header would already be included,
but it seems the SPEED_* macros are provided by include/uapi/linux/ethtool.h.
Go figure...
Please keep the review tag.
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^ permalink raw reply
* Re: [PATCH net-next 03/14] phy: qcom-sgmii-eth: add .set_mode() and .validate() methods
From: Russell King (Oracle) @ 2026-01-14 18:55 UTC (permalink / raw)
To: Vladimir Oltean
Cc: Andrew Lunn, Heiner Kallweit, Alexandre Torgue, Andrew Lunn,
David S. Miller, Eric Dumazet, Jakub Kicinski, Konrad Dybcio,
linux-arm-kernel, linux-arm-msm, linux-phy, linux-stm32,
Maxime Coquelin, Mohd Ayaan Anwar, Neil Armstrong, netdev,
Paolo Abeni, Vinod Koul
In-Reply-To: <20260114184705.djvad5phrnfen6wx@skbuf>
On Wed, Jan 14, 2026 at 08:47:05PM +0200, Vladimir Oltean wrote:
> On Wed, Jan 14, 2026 at 05:45:24PM +0000, Russell King (Oracle) wrote:
> > qcom-sgmii-eth is an Ethernet SerDes supporting only Ethernet mode
> > using SGMII, 1000BASE-X and 2500BASE-X.
> >
> > Add an implementation of the .set_mode() method, which can be used
> > instead of or as well as the .set_speed() method. The Ethernet
> > interface modes mentioned above all have a fixed data rate, so
> > setting the mode is sufficient to fully specify the operating
> > parameters.
> >
> > Add an implementation of the .validate() method, which will be
> > necessary to allow discovery of the SerDes capabilities for platform
> > independent SerDes support in the stmmac netowrk driver.
>
> s/netowrk/network/
>
> >
> > Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
> > ---
>
> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
According to patchwork (I forgot the RFC tag on the patches) it needs
linux/phy.h included. Plesae let me know if you'd like me to retain
your r-b. Thanks.
--
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FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
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^ permalink raw reply
* Re: [PATCH net-next 03/14] phy: qcom-sgmii-eth: add .set_mode() and .validate() methods
From: Vladimir Oltean @ 2026-01-14 18:47 UTC (permalink / raw)
To: Russell King (Oracle)
Cc: Andrew Lunn, Heiner Kallweit, Alexandre Torgue, Andrew Lunn,
David S. Miller, Eric Dumazet, Jakub Kicinski, Konrad Dybcio,
linux-arm-kernel, linux-arm-msm, linux-phy, linux-stm32,
Maxime Coquelin, Mohd Ayaan Anwar, Neil Armstrong, netdev,
Paolo Abeni, Vinod Koul
In-Reply-To: <E1vg4vs-00000003SFt-1Fje@rmk-PC.armlinux.org.uk>
On Wed, Jan 14, 2026 at 05:45:24PM +0000, Russell King (Oracle) wrote:
> qcom-sgmii-eth is an Ethernet SerDes supporting only Ethernet mode
> using SGMII, 1000BASE-X and 2500BASE-X.
>
> Add an implementation of the .set_mode() method, which can be used
> instead of or as well as the .set_speed() method. The Ethernet
> interface modes mentioned above all have a fixed data rate, so
> setting the mode is sufficient to fully specify the operating
> parameters.
>
> Add an implementation of the .validate() method, which will be
> necessary to allow discovery of the SerDes capabilities for platform
> independent SerDes support in the stmmac netowrk driver.
s/netowrk/network/
>
> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
> ---
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
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* [PATCH net-next 14/14] net: stmmac: report PCS configuration changes
From: Russell King (Oracle) @ 2026-01-14 17:46 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Konrad Dybcio, linux-arm-kernel, linux-arm-msm,
linux-phy, linux-stm32, Maxime Coquelin, Mohd Ayaan Anwar,
Neil Armstrong, netdev, Paolo Abeni, Vinod Koul
In-Reply-To: <aWfWDsCoBc3YRKKo@shell.armlinux.org.uk>
Report if/when qcom-ethqos changes the PCS configuration. With phylink
now setting the PCS configuration, there should be no need for drivers
to change this.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
index f9e7a7ed840b..6a1e30b10740 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
@@ -71,6 +71,7 @@ static inline void dwmac_ctrl_ane(void __iomem *ioaddr, u32 reg, bool ane,
bool srgmi_ral)
{
u32 value = readl(ioaddr + GMAC_AN_CTRL(reg));
+ u32 old = value, diff;
/* Enable and restart the Auto-Negotiation */
if (ane)
@@ -84,6 +85,20 @@ static inline void dwmac_ctrl_ane(void __iomem *ioaddr, u32 reg, bool ane,
if (srgmi_ral)
value |= GMAC_AN_CTRL_SGMRAL;
+ diff = old ^ value;
+ if (diff & ~GMAC_AN_CTRL_RAN) {
+ pr_warn("dwmac: PCS configuration changed from phylink by glue, please report: 0x%08x -> 0x%08x\n",
+ old & ~GMAC_AN_CTRL_RAN, value & ~GMAC_AN_CTRL_RAN);
+#define REPORT_BIT(x) \
+ if (diff & GMAC_AN_CTRL_##x) \
+ pr_warn("dwmac: %8s %u -> %u\n", #x, \
+ !!(old & GMAC_AN_CTRL_##x), \
+ !!(value & GMAC_AN_CTRL_##x))
+ REPORT_BIT(ANE);
+ REPORT_BIT(SGMRAL);
+#undef REPORT_BIT
+ }
+
writel(value, ioaddr + GMAC_AN_CTRL(reg));
}
#endif /* __STMMAC_PCS_H__ */
--
2.47.3
--
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^ permalink raw reply related
* [PATCH net-next 12/14] net: stmmac: add support for reading inband SGMII status
From: Russell King (Oracle) @ 2026-01-14 17:46 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Konrad Dybcio, linux-arm-kernel, linux-arm-msm,
linux-phy, linux-stm32, Maxime Coquelin, Mohd Ayaan Anwar,
Neil Armstrong, netdev, Paolo Abeni, Vinod Koul
In-Reply-To: <aWfWDsCoBc3YRKKo@shell.armlinux.org.uk>
Report the link, speed and duplex for SGMII links, read from the
SGMII, RGMII and SMII status and control register.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
.../net/ethernet/stmicro/stmmac/stmmac_pcs.c | 44 ++++++++++++++++++-
.../net/ethernet/stmicro/stmmac/stmmac_pcs.h | 4 ++
2 files changed, 46 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
index 73fc56ce5e55..12fc5038d913 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
@@ -17,6 +17,16 @@
#define GMAC_ANE_LPA 0x0c /* ANE link partener ability */
#define GMAC_TBI 0x14 /* TBI extend status */
+/*
+ * RGSMII status bitfield definitions.
+ */
+#define GMAC_RGSMIII_LNKMOD BIT(0)
+#define GMAC_RGSMIII_SPEED_MASK GENMASK(2, 1)
+#define GMAC_RGSMIII_SPEED_125 2
+#define GMAC_RGSMIII_SPEED_25 1
+#define GMAC_RGSMIII_SPEED_2_5 0
+#define GMAC_RGSMIII_LNKSTS BIT(3)
+
static enum ethtool_link_mode_bit_indices dwmac_hd_mode_bits[] = {
ETHTOOL_LINK_MODE_10baseT_Half_BIT,
ETHTOOL_LINK_MODE_100baseT_Half_BIT,
@@ -97,7 +107,7 @@ static void dwmac_integrated_pcs_get_state(struct phylink_pcs *pcs,
struct phylink_link_state *state)
{
struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs);
- u32 status, lpa;
+ u32 status, lpa, rgsmii;
status = readl(spcs->base + GMAC_AN_STATUS);
@@ -111,7 +121,35 @@ static void dwmac_integrated_pcs_get_state(struct phylink_pcs *pcs,
phylink_mii_c22_pcs_decode_state(state, neg_mode, status, lpa);
} else {
- state->link = false;
+ rgsmii = field_get(spcs->rgsmii_status_mask,
+ readl(spcs->rgsmii));
+ state->link = !!(status & GMAC_RGSMIII_LNKSTS);
+
+ if (state->link && neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ /* FIXME: fill in speed and duplex. This requires the
+ * contents of the dwmac1000 GMAC_RGSMIIIS or dwmac4
+ * GMAC_PHYIF_CONTROL_STATUS register.
+ */
+ state->duplex = rgsmii & GMAC_RGSMIII_LNKMOD ?
+ DUPLEX_FULL : DUPLEX_HALF;
+ switch (FIELD_GET(GMAC_RGSMIII_SPEED_MASK, rgsmii)) {
+ case GMAC_RGSMIII_SPEED_2_5:
+ state->speed = SPEED_10;
+ break;
+
+ case GMAC_RGSMIII_SPEED_25:
+ state->speed = SPEED_100;
+ break;
+
+ case GMAC_RGSMIII_SPEED_125:
+ state->speed = SPEED_1000;
+ break;
+
+ default:
+ state->link = false;
+ break;
+ }
+ }
}
}
@@ -205,6 +243,8 @@ int stmmac_integrated_pcs_init(struct stmmac_priv *priv,
spcs->priv = priv;
spcs->base = priv->ioaddr + pcs_info->pcs_offset;
+ spcs->rgsmii = priv->ioaddr + pcs_info->rgsmii_offset;
+ spcs->rgsmii_status_mask = pcs_info->rgsmii_status_mask;
spcs->int_mask = pcs_info->int_mask;
spcs->pcs.ops = &dwmac_integrated_pcs_ops;
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
index a7c71f40f952..f9e7a7ed840b 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
@@ -29,12 +29,16 @@ struct stmmac_priv;
struct stmmac_pcs_info {
unsigned int pcs_offset;
+ unsigned int rgsmii_offset;
+ u32 rgsmii_status_mask;
u32 int_mask;
};
struct stmmac_pcs {
struct stmmac_priv *priv;
void __iomem *base;
+ void __iomem *rgsmii;
+ u32 rgsmii_status_mask;
u32 int_mask;
phy_interface_t interface;
struct phylink_pcs pcs;
--
2.47.3
--
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^ permalink raw reply related
* [PATCH net-next 13/14] net: stmmac: configure SGMII AN control according to phylink
From: Russell King (Oracle) @ 2026-01-14 17:46 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Konrad Dybcio, linux-arm-kernel, linux-arm-msm,
linux-phy, linux-stm32, Maxime Coquelin, Mohd Ayaan Anwar,
Neil Armstrong, netdev, Paolo Abeni, Vinod Koul
In-Reply-To: <aWfWDsCoBc3YRKKo@shell.armlinux.org.uk>
Provide phylink with the integrated PCS autonegotiation capabilities,
and configure the PCS's AN settings according to phylink's requested
requirements.
This may cause regressions.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
.../net/ethernet/stmicro/stmmac/stmmac_pcs.c | 20 ++++++++++++-------
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
index 12fc5038d913..44f82e6c1edb 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
@@ -65,7 +65,8 @@ static int dwmac_integrated_pcs_validate(struct phylink_pcs *pcs,
static unsigned int dwmac_integrated_pcs_inband_caps(struct phylink_pcs *pcs,
phy_interface_t interface)
{
- if (phy_interface_mode_is_8023z(interface))
+ if (phy_interface_mode_is_8023z(interface) ||
+ interface == PHY_INTERFACE_MODE_SGMII)
return LINK_INBAND_ENABLE | LINK_INBAND_DISABLE;
return 0;
@@ -160,8 +161,9 @@ static int dwmac_integrated_pcs_config(struct phylink_pcs *pcs,
bool permit_pause_to_mac)
{
struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs);
- bool changed = false, ane = true;
- u32 adv;
+ void __iomem *an_control = spcs->base + GMAC_AN_CTRL(0);
+ bool changed = false;
+ u32 adv, ctrl;
int ret;
if (spcs->interface != interface) {
@@ -178,12 +180,16 @@ static int dwmac_integrated_pcs_config(struct phylink_pcs *pcs,
if (readl(spcs->base + GMAC_ANE_ADV) != adv)
changed = true;
writel(adv, spcs->base + GMAC_ANE_ADV);
-
- ane = neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED;
}
- dwmac_ctrl_ane(spcs->base, 0, ane,
- spcs->priv->hw->reverse_sgmii_enable);
+ ctrl = readl(an_control) & ~(GMAC_AN_CTRL_ANE | GMAC_AN_CTRL_SGMRAL);
+ if (spcs->priv->hw->reverse_sgmii_enable)
+ ctrl |= GMAC_AN_CTRL_SGMRAL | GMAC_AN_CTRL_ANE;
+ else if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
+ ctrl |= GMAC_AN_CTRL_ANE;
+ else
+ ctrl |= GMAC_AN_CTRL_SGMRAL;
+ writel(ctrl, an_control);
return changed;
}
--
2.47.3
--
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^ permalink raw reply related
* [PATCH net-next 11/14] net: stmmac: add struct stmmac_pcs_info
From: Russell King (Oracle) @ 2026-01-14 17:46 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Konrad Dybcio, linux-arm-kernel, linux-arm-msm,
linux-phy, linux-stm32, Maxime Coquelin, Mohd Ayaan Anwar,
Neil Armstrong, netdev, Paolo Abeni, Vinod Koul
In-Reply-To: <aWfWDsCoBc3YRKKo@shell.armlinux.org.uk>
We need to describe one more register (offset and field bitmask) to
the PCS code. Move the existing PCS offset and interrupt enable bits
to a new struct and pass that in to stmmac_integrated_pcs_init().
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c | 9 ++++++---
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c | 8 ++++++--
drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c | 8 ++++----
drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h | 9 +++++++--
4 files changed, 23 insertions(+), 11 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
index af566636fad9..a3ef237de1b8 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
@@ -22,14 +22,17 @@
#include "stmmac_ptp.h"
#include "dwmac1000.h"
+static const struct stmmac_pcs_info dwmac1000_pcs_info = {
+ .pcs_offset = GMAC_PCS_BASE,
+ .int_mask = GMAC_INT_DISABLE_PCSLINK | GMAC_INT_DISABLE_PCSAN,
+};
+
static int dwmac1000_pcs_init(struct stmmac_priv *priv)
{
if (!priv->dma_cap.pcs)
return 0;
- return stmmac_integrated_pcs_init(priv, GMAC_PCS_BASE,
- GMAC_INT_DISABLE_PCSLINK |
- GMAC_INT_DISABLE_PCSAN);
+ return stmmac_integrated_pcs_init(priv, &dwmac1000_pcs_info);
}
static void dwmac1000_core_init(struct mac_device_info *hw,
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
index 623868afe93d..7f4949229288 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
@@ -22,13 +22,17 @@
#include "dwmac4.h"
#include "dwmac5.h"
+static const struct stmmac_pcs_info dwmac4_pcs_info = {
+ .pcs_offset = GMAC_PCS_BASE,
+ .int_mask = GMAC_INT_PCS_LINK | GMAC_INT_PCS_ANE,
+};
+
static int dwmac4_pcs_init(struct stmmac_priv *priv)
{
if (!priv->dma_cap.pcs)
return 0;
- return stmmac_integrated_pcs_init(priv, GMAC_PCS_BASE,
- GMAC_INT_PCS_LINK | GMAC_INT_PCS_ANE);
+ return stmmac_integrated_pcs_init(priv, &dwmac4_pcs_info);
}
static void dwmac4_core_init(struct mac_device_info *hw,
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
index edcf36083806..73fc56ce5e55 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
@@ -193,8 +193,8 @@ int stmmac_integrated_pcs_get_phy_intf_sel(struct stmmac_priv *priv,
return -EINVAL;
}
-int stmmac_integrated_pcs_init(struct stmmac_priv *priv, unsigned int offset,
- u32 int_mask)
+int stmmac_integrated_pcs_init(struct stmmac_priv *priv,
+ const struct stmmac_pcs_info *pcs_info)
{
struct stmmac_pcs *spcs;
int ret;
@@ -204,8 +204,8 @@ int stmmac_integrated_pcs_init(struct stmmac_priv *priv, unsigned int offset,
return -ENOMEM;
spcs->priv = priv;
- spcs->base = priv->ioaddr + offset;
- spcs->int_mask = int_mask;
+ spcs->base = priv->ioaddr + pcs_info->pcs_offset;
+ spcs->int_mask = pcs_info->int_mask;
spcs->pcs.ops = &dwmac_integrated_pcs_ops;
if (priv->plat->serdes) {
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
index 845bcad9d0f7..a7c71f40f952 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
@@ -27,6 +27,11 @@
struct stmmac_priv;
+struct stmmac_pcs_info {
+ unsigned int pcs_offset;
+ u32 int_mask;
+};
+
struct stmmac_pcs {
struct stmmac_priv *priv;
void __iomem *base;
@@ -45,8 +50,8 @@ void stmmac_integrated_pcs_irq(struct stmmac_priv *priv, u32 status,
struct stmmac_extra_stats *x);
int stmmac_integrated_pcs_get_phy_intf_sel(struct stmmac_priv *priv,
phy_interface_t interface);
-int stmmac_integrated_pcs_init(struct stmmac_priv *priv, unsigned int offset,
- u32 int_mask);
+int stmmac_integrated_pcs_init(struct stmmac_priv *priv,
+ const struct stmmac_pcs_info *pcs_info);
/**
* dwmac_ctrl_ane - To program the AN Control Register.
--
2.47.3
--
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^ permalink raw reply related
* [PATCH net-next 10/14] net: stmmac: use integrated PCS for BASE-X modes
From: Russell King (Oracle) @ 2026-01-14 17:46 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Konrad Dybcio, linux-arm-kernel, linux-arm-msm,
linux-phy, linux-stm32, Maxime Coquelin, Mohd Ayaan Anwar,
Neil Armstrong, netdev, Paolo Abeni, Vinod Koul
In-Reply-To: <aWfWDsCoBc3YRKKo@shell.armlinux.org.uk>
dwmac-qcom-ethqos supports SGMII and 2500BASE-X using the integrated
PCS, so we need to expand the PCS support to include support for
BASE-X modes.
Add support to the prereset configuration to detect 2500BASE-X, and
arrange for stmmac_mac_select_pcs() to return the integrated PCS if
its supported_interfaces bitmap reports support for the interface mode.
This results in priv->hw->pcs now being write-only, so remove it.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
drivers/net/ethernet/stmicro/stmmac/common.h | 1 -
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 8 ++------
2 files changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h
index 49df46be3669..8ef54f6e78f6 100644
--- a/drivers/net/ethernet/stmicro/stmmac/common.h
+++ b/drivers/net/ethernet/stmicro/stmmac/common.h
@@ -629,7 +629,6 @@ struct mac_device_info {
unsigned int unicast_filter_entries;
unsigned int mcast_bits_log2;
unsigned int rx_csum;
- unsigned int pcs;
unsigned int xlgmac;
unsigned int num_vlan;
u32 vlan_filter[32];
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 5254d9d19ffe..a63ae6c4bc8a 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -911,11 +911,8 @@ static struct phylink_pcs *stmmac_mac_select_pcs(struct phylink_config *config,
return pcs;
}
- /* The PCS control register is only relevant for SGMII, TBI and RTBI
- * modes. We no longer support TBI or RTBI, so only configure this
- * register when operating in SGMII mode with the integrated PCS.
- */
- if (priv->hw->pcs & STMMAC_PCS_SGMII && priv->integrated_pcs)
+ if (priv->integrated_pcs &&
+ test_bit(interface, priv->integrated_pcs->pcs.supported_interfaces))
return &priv->integrated_pcs->pcs;
return NULL;
@@ -1173,7 +1170,6 @@ static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
if (priv->dma_cap.pcs && interface == PHY_INTERFACE_MODE_SGMII) {
netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
- priv->hw->pcs = STMMAC_PCS_SGMII;
switch (speed) {
case SPEED_10:
--
2.47.3
--
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^ permalink raw reply related
* [PATCH net-next 09/14] net: stmmac: add BASE-X support to integrated PCS
From: Russell King (Oracle) @ 2026-01-14 17:45 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Konrad Dybcio, linux-arm-kernel, linux-arm-msm,
linux-phy, linux-stm32, Maxime Coquelin, Mohd Ayaan Anwar,
Neil Armstrong, netdev, Paolo Abeni, Vinod Koul
In-Reply-To: <aWfWDsCoBc3YRKKo@shell.armlinux.org.uk>
The integrated PCS supports 802.3z (BASE-X) modes when the Synopsys
IP is coupled with an appropriate SerDes to provide the electrical
interface. The PCS presents a TBI interface to the SerDes for this.
Thus, the BASE-X related registers are only present when TBI mode is
supported.
dwmac-qcom-ethqos added support for using 2.5G with the integrated PCS
by calling dwmac_ctrl_ane() directly.
Add support for 1000BASE-X mode to the integrated PCS support if the
PCS supports TBI, and 2500BASE-X if we have a SerDes that supports
this mode.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
.../net/ethernet/stmicro/stmmac/stmmac_pcs.c | 95 ++++++++++++++++++-
1 file changed, 92 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
index cf7337e9ed3e..edcf36083806 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
@@ -17,6 +17,50 @@
#define GMAC_ANE_LPA 0x0c /* ANE link partener ability */
#define GMAC_TBI 0x14 /* TBI extend status */
+static enum ethtool_link_mode_bit_indices dwmac_hd_mode_bits[] = {
+ ETHTOOL_LINK_MODE_10baseT_Half_BIT,
+ ETHTOOL_LINK_MODE_100baseT_Half_BIT,
+ ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
+ ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
+ ETHTOOL_LINK_MODE_10baseT1S_Half_BIT,
+ ETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT,
+};
+
+static int dwmac_integrated_pcs_validate(struct phylink_pcs *pcs,
+ unsigned long *supported,
+ const struct phylink_link_state *state)
+{
+ struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs);
+ size_t i;
+ u32 val;
+
+ if (phy_interface_mode_is_8023z(state->interface)) {
+ /* ESTATUS_1000_XFULL is always set, so full duplex is
+ * supported. ESTATUS_1000_XHALF depends on core configuration.
+ */
+ val = readl(spcs->base + GMAC_TBI);
+ if (~val & ESTATUS_1000_XHALF)
+ for (i = 0; i < ARRAY_SIZE(dwmac_hd_mode_bits); i++)
+ linkmode_clear_bit(dwmac_hd_mode_bits[i],
+ supported);
+
+ return 0;
+ } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static unsigned int dwmac_integrated_pcs_inband_caps(struct phylink_pcs *pcs,
+ phy_interface_t interface)
+{
+ if (phy_interface_mode_is_8023z(interface))
+ return LINK_INBAND_ENABLE | LINK_INBAND_DISABLE;
+
+ return 0;
+}
+
static int dwmac_integrated_pcs_enable(struct phylink_pcs *pcs)
{
struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs);
@@ -52,7 +96,23 @@ static void dwmac_integrated_pcs_get_state(struct phylink_pcs *pcs,
unsigned int neg_mode,
struct phylink_link_state *state)
{
- state->link = false;
+ struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs);
+ u32 status, lpa;
+
+ status = readl(spcs->base + GMAC_AN_STATUS);
+
+ if (phy_interface_mode_is_8023z(state->interface)) {
+ /* For 802.3z modes, the PCS block supports the advertisement
+ * and link partner advertisement registers using standard
+ * 802.3 format. The status register also has the link status
+ * and AN complete bits in the same bit location.
+ */
+ lpa = readl(spcs->base + GMAC_ANE_LPA);
+
+ phylink_mii_c22_pcs_decode_state(state, neg_mode, status, lpa);
+ } else {
+ state->link = false;
+ }
}
static int dwmac_integrated_pcs_config(struct phylink_pcs *pcs,
@@ -62,6 +122,8 @@ static int dwmac_integrated_pcs_config(struct phylink_pcs *pcs,
bool permit_pause_to_mac)
{
struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs);
+ bool changed = false, ane = true;
+ u32 adv;
int ret;
if (spcs->interface != interface) {
@@ -72,12 +134,25 @@ static int dwmac_integrated_pcs_config(struct phylink_pcs *pcs,
spcs->interface = interface;
}
- dwmac_ctrl_ane(spcs->base, 0, 1, spcs->priv->hw->reverse_sgmii_enable);
+ if (phy_interface_mode_is_8023z(interface)) {
+ adv = phylink_mii_c22_pcs_encode_advertisement(interface,
+ advertising);
+ if (readl(spcs->base + GMAC_ANE_ADV) != adv)
+ changed = true;
+ writel(adv, spcs->base + GMAC_ANE_ADV);
- return 0;
+ ane = neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED;
+ }
+
+ dwmac_ctrl_ane(spcs->base, 0, ane,
+ spcs->priv->hw->reverse_sgmii_enable);
+
+ return changed;
}
static const struct phylink_pcs_ops dwmac_integrated_pcs_ops = {
+ .pcs_validate = dwmac_integrated_pcs_validate,
+ .pcs_inband_caps = dwmac_integrated_pcs_inband_caps,
.pcs_enable = dwmac_integrated_pcs_enable,
.pcs_disable = dwmac_integrated_pcs_disable,
.pcs_get_state = dwmac_integrated_pcs_get_state,
@@ -112,6 +187,9 @@ int stmmac_integrated_pcs_get_phy_intf_sel(struct stmmac_priv *priv,
if (interface == PHY_INTERFACE_MODE_SGMII)
return PHY_INTF_SEL_SGMII;
+ if (phy_interface_mode_is_8023z(interface))
+ return PHY_INTF_SEL_TBI;
+
return -EINVAL;
}
@@ -140,6 +218,17 @@ int stmmac_integrated_pcs_init(struct stmmac_priv *priv, unsigned int offset,
__set_bit(PHY_INTERFACE_MODE_SGMII, spcs->pcs.supported_interfaces);
+ if (readl(spcs->base + GMAC_AN_STATUS) & BMSR_ESTATEN) {
+ __set_bit(PHY_INTERFACE_MODE_1000BASEX,
+ spcs->pcs.supported_interfaces);
+
+ /* Only allow 2500Base-X if the SerDes has support. */
+ ret = dwmac_serdes_validate(priv, PHY_INTERFACE_MODE_2500BASEX);
+ if (ret == 0)
+ __set_bit(PHY_INTERFACE_MODE_2500BASEX,
+ spcs->pcs.supported_interfaces);
+ }
+
priv->integrated_pcs = spcs;
return 0;
--
2.47.3
--
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