* Re: [PATCH] phy: Sort the subsystem Makefile
From: Vinod Koul @ 2026-02-27 15:29 UTC (permalink / raw)
To: linux-phy, Vinod Koul; +Cc: Neil Armstrong, Vladimir Oltean
In-Reply-To: <20260223065743.395539-1-vkoul@kernel.org>
On Mon, 23 Feb 2026 12:27:43 +0530, Vinod Koul wrote:
> Makefile is supposed to be sorted alphabetically, sadly it has bitrotted
> so fix that
>
>
Applied, thanks!
[1/1] phy: Sort the subsystem Makefile
commit: d8f0ef2aebaa90c0155e266c1fdd6fa2aef44bb1
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* Re: [PATCH] phy: move spacemit pcie driver to its subfolder
From: Vinod Koul @ 2026-02-27 15:29 UTC (permalink / raw)
To: linux-phy, Vinod Koul
Cc: Neil Armstrong, Vladimir Oltean, Alex Elder, Ze Huang, spacemit
In-Reply-To: <20260223064240.386617-1-vkoul@kernel.org>
On Mon, 23 Feb 2026 12:12:39 +0530, Vinod Koul wrote:
> Commit fe4bc1a08638 ("phy: spacemit: support K1 USB2.0 PHY controller")
> created spacemit subfolder with usb driver while commit 57e920b92724
> ("phy: spacemit: Introduce PCIe/combo PHY") added pcie driver in phy
> folder. Move latter into spacemit subfolder and rename file to
> phy-k1-pcie.c
>
>
> [...]
Applied, thanks!
[1/1] phy: move spacemit pcie driver to its subfolder
commit: 75fb1a33f9ac4c9730e61bb19aaaab02023a99b2
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* Re: [PATCH net-next 0/9] net: stmmac: qcom-ethqos: further serdes reorganisation
From: Vladimir Oltean @ 2026-02-27 15:27 UTC (permalink / raw)
To: Vinod Koul
Cc: Russell King (Oracle), Andrew Lunn, Alexandre Torgue, Andrew Lunn,
David S. Miller, Eric Dumazet, Jakub Kicinski, linux-arm-kernel,
linux-arm-msm, linux-phy, linux-stm32, Mohd Ayaan Anwar,
Neil Armstrong, netdev, Paolo Abeni
In-Reply-To: <aaGgWUpM2A5y11Wh@vaman>
Hi Vinod,
On Fri, Feb 27, 2026 at 07:17:05PM +0530, Vinod Koul wrote:
> On 25-02-26, 09:02, Russell King (Oracle) wrote:
> > Note: only 8 patches in this series, not 9 as the subject line says,
> > as the set_clk_tx_rate() patch became part of the first series.
> >
> > On Wed, Feb 25, 2026 at 09:00:41AM +0000, Russell King (Oracle) wrote:
> > > This is part 2 of the qcom-ethqos series, part 1 has now been merged.
> > >
> > > This part of the series focuses on the generic PHY driver, but these
> > > changes have dependencies on the ethernet driver, hence why
> > > it will need to go via net-next. Furthermore, subsequent changes
> > > depend on these patches.
>
> This lgtm, can we get signed tag so that we can pull this into phy tree
> as well
I think this series is obsolete. It has been superseded in the netdev
patchwork by:
[PATCH RESEND2 net-next 0/8] net: stmmac: qcom-ethqos: further serdes reorganisation
├─>[PATCH RESEND2 net-next 1/8] net: stmmac: qcom-ethqos: move ethqos_set_serdes_speed()
├─>[PATCH RESEND2 net-next 2/8] phy: qcom-sgmii-eth: add .set_mode() and .validate() methods
├─>[PATCH RESEND2 net-next 3/8] net: stmmac: qcom-ethqos: convert to use phy_set_mode_ext()
├─>[PATCH RESEND2 net-next 4/8] phy: qcom-sgmii-eth: remove .set_speed() implementation
├─>[PATCH RESEND2 net-next 5/8] phy: qcom-sgmii-eth: use PHY interface mode for SerDes settings
├─>[PATCH RESEND2 net-next 6/8] phy: qcom-sgmii-eth: remove qcom_dwmac_sgmii_phy_interface()
├─>[PATCH RESEND2 net-next 7/8] phy: qcom-sgmii-eth: relax order of .power_on() vs .set_mode*()
└─>[PATCH RESEND2 net-next 8/8] net: stmmac: qcom-ethqos: remove phy_set_mode_ext() after phy_power_on()
(with which it is only partially overlapping)
I guess you should give your Acks there as well.
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* Re: [PATCH] phy: qcom: qmp-ufs: Fix SM8650 PCS table for Gear 4
From: Vinod Koul @ 2026-02-27 15:25 UTC (permalink / raw)
To: Neil Armstrong, Konrad Dybcio, Abel Vesa
Cc: Manivannan Sadhasivam, linux-arm-msm, linux-phy, linux-kernel,
stable, Nitin Rawat
In-Reply-To: <20260219-phy-qcom-qmp-ufs-fix-sm8650-pcs-g4-table-v1-1-f136505b57f6@oss.qualcomm.com>
On Thu, 19 Feb 2026 13:11:48 +0200, Abel Vesa wrote:
> According to internal documentation, on SM8650, when the PHY is configured
> in Gear 4, the QPHY_V6_PCS_UFS_PLL_CNTL register needs to have the same
> value as for Gear 5.
>
> At the moment, there is no board that comes with a UFS 3.x device, so
> this issue doesn't show up, but with the new Eliza SoC, which uses the
> same init sequence as SM8650, on the MTP board, the link startup fails
> with the current Gear 4 PCS table.
>
> [...]
Applied, thanks!
[1/1] phy: qcom: qmp-ufs: Fix SM8650 PCS table for Gear 4
commit: 81af9e40e2e4e1aa95f09fb34811760be6742c58
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* Re: [PATCH v2] phy: ti: j721e-wiz: Fix device node reference leak in wiz_get_lane_phy_types()
From: Vinod Koul @ 2026-02-27 15:25 UTC (permalink / raw)
To: Neil Armstrong, Kishon Vijay Abraham I, Jyri Sarha,
Vladimir Oltean, Felix Gu
Cc: linux-phy, linux-kernel
In-Reply-To: <20260212-wiz-v2-1-6e8bd4cc7a4a@gmail.com>
On Thu, 12 Feb 2026 18:39:19 +0800, Felix Gu wrote:
> The serdes device_node is obtained using of_get_child_by_name(),
> which increments the reference count. However, it is never put,
> leading to a reference leak.
>
> Add the missing of_node_put() calls to ensure the reference count is
> properly balanced.
>
> [...]
Applied, thanks!
[1/1] phy: ti: j721e-wiz: Fix device node reference leak in wiz_get_lane_phy_types()
commit: 584b457f4166293bdfa50f930228e9fb91a38392
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* Re: [PATCH v3] phy: k1-usb: add disconnect function support
From: Vinod Koul @ 2026-02-27 15:25 UTC (permalink / raw)
To: Neil Armstrong, Ze Huang, Yixun Lan
Cc: Vladimir Oltean, Junzhong Pan, spacemit, linux-phy, linux-riscv,
linux-kernel
In-Reply-To: <20260216152653.25244-1-dlan@kernel.org>
On Mon, 16 Feb 2026 23:26:53 +0800, Yixun Lan wrote:
> A disconnect status BIT of USB2 PHY need to be cleared, otherwise
> it will fail to work properly during next connection when devices
> connect to roothub directly.
>
>
Applied, thanks!
[1/1] phy: k1-usb: add disconnect function support
commit: f0cf0a882a02dcf28547f32264f6fd37e9a7b147
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* Re: [PATCH phy-fixes] phy: lynx-28g: skip CDR lock workaround for lanes disabled in the device tree
From: Vinod Koul @ 2026-02-27 15:25 UTC (permalink / raw)
To: linux-phy, Vladimir Oltean; +Cc: Neil Armstrong, Ioana Ciornei, linux-kernel
In-Reply-To: <20260226182853.1103616-1-vladimir.oltean@nxp.com>
On Thu, 26 Feb 2026 20:28:53 +0200, Vladimir Oltean wrote:
> The blamed commit introduced support for specifying individual lanes as
> OF nodes in the device, and these can have status = "disabled".
>
> When that happens, for_each_available_child_of_node() skips them and
> lynx_28g_probe_lane() -> devm_phy_create() is not called, so lane->phy
> will be NULL. Yet it will be dereferenced in lynx_28g_cdr_lock_check(),
> resulting in a crash.
>
> [...]
Applied, thanks!
[1/1] phy: lynx-28g: skip CDR lock workaround for lanes disabled in the device tree
commit: a258d843a3e4cb687da19437f8f81fee55ad7d35
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* Re: [PATCH phy-fixes] phy: make PHY_COMMON_PROPS Kconfig symbol conditionally user-selectable
From: Vinod Koul @ 2026-02-27 15:25 UTC (permalink / raw)
To: linux-phy, Vladimir Oltean
Cc: Neil Armstrong, Bjørn Mork, linux-kernel, Geert Uytterhoeven
In-Reply-To: <20260226153315.3530378-1-vladimir.oltean@nxp.com>
On Thu, 26 Feb 2026 17:33:15 +0200, Vladimir Oltean wrote:
> Geert reports that enabling CONFIG_KUNIT_ALL_TESTS shouldn't enable
> features that aren't enabled without it. That isn't what "*all* tests"
> means, but as the prompt puts it, "All KUnit tests with satisfied
> dependencies".
>
> The impact is that enabling CONFIG_KUNIT_ALL_TESTS brings features which
> cannot be disabled as built-in into the kernel.
>
> [...]
Applied, thanks!
[1/1] phy: make PHY_COMMON_PROPS Kconfig symbol conditionally user-selectable
commit: 48fafffcf29bb968c9dee6bf507c1e57d0ccb6b5
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* Re: [PATCH v2 3/3] phy: k1-usb: k3: add USB2 PHY support
From: Vinod Koul @ 2026-02-27 14:59 UTC (permalink / raw)
To: Yixun Lan
Cc: Neil Armstrong, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Ze Huang, Junzhong Pan, linux-phy, devicetree, linux-riscv,
spacemit, linux-kernel
In-Reply-To: <20260214-11-k3-usb2-phy-v2-3-6ed31e031ab4@kernel.org>
On 14-02-26, 20:29, Yixun Lan wrote:
> Add USB2 PHY support for SpacemiT K3 SoC.
>
> Register layout of handling USB disconnect operation has been changed,
> So introducing a platform data to distinguish the different SoCs.
>
> Signed-off-by: Yixun Lan <dlan@kernel.org>
> ---
> drivers/phy/spacemit/phy-k1-usb2.c | 34 +++++++++++++++++++++++++++++-----
> 1 file changed, 29 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/phy/spacemit/phy-k1-usb2.c b/drivers/phy/spacemit/phy-k1-usb2.c
> index 959bf79c7a72..b4ba97481ddd 100644
> --- a/drivers/phy/spacemit/phy-k1-usb2.c
> +++ b/drivers/phy/spacemit/phy-k1-usb2.c
> @@ -51,6 +51,9 @@
> #define PHY_K1_HS_HOST_DISC 0x40
> #define PHY_K1_HS_HOST_DISC_CLR BIT(0)
>
> +#define PHY_K3_HS_HOST_DISC 0x20
> +#define PHY_K3_HS_HOST_DISC_CLR BIT(8)
> +
> #define PHY_PLL_DIV_CFG 0x98
> #define PHY_FDIV_FRACT_8_15 GENMASK(7, 0)
> #define PHY_FDIV_FRACT_16_19 GENMASK(11, 8)
> @@ -145,7 +148,7 @@ static int spacemit_usb2phy_exit(struct phy *phy)
> return 0;
> }
>
> -static int spacemit_usb2phy_disconnect(struct phy *phy, int port)
> +static int spacemit_k1_usb2phy_disconnect(struct phy *phy, int port)
> {
> struct spacemit_usb2phy *sphy = phy_get_drvdata(phy);
>
> @@ -155,10 +158,27 @@ static int spacemit_usb2phy_disconnect(struct phy *phy, int port)
> return 0;
> }
>
> -static const struct phy_ops spacemit_usb2phy_ops = {
> +static int spacemit_k3_usb2phy_disconnect(struct phy *phy, int port)
> +{
> + struct spacemit_usb2phy *sphy = phy_get_drvdata(phy);
> +
> + regmap_update_bits(sphy->regmap_base, PHY_K3_HS_HOST_DISC,
> + PHY_K3_HS_HOST_DISC_CLR, PHY_K3_HS_HOST_DISC_CLR);
Please match this with preceding open parenthesis
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* Re: [PATCH v2 2/4] phy: axiado: add Axiado eMMC PHY driver
From: Vinod Koul @ 2026-02-27 14:53 UTC (permalink / raw)
To: Tzu-Hao Wei
Cc: SriNavmani A, Prasad Bolisetty, Neil Armstrong, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-phy, devicetree,
linux-arm-kernel, linux-kernel, openbmc
In-Reply-To: <20260206-axiado-ax3000-add-emmc-phy-driver-support-v2-2-a2f59e97a92d@axiado.com>
On 06-02-26, 16:22, Tzu-Hao Wei wrote:
> From: SriNavmani A <srinavmani@axiado.com>
>
> It provides the required configurations for Axiado eMMC PHY driver for
> HS200 mode.
>
> Signed-off-by: SriNavmani A <srinavmani@axiado.com>
> Co-developed-by: Prasad Bolisetty <pbolisetty@axiado.com>
> Signed-off-by: Prasad Bolisetty <pbolisetty@axiado.com>
> Signed-off-by: Tzu-Hao Wei <twei@axiado.com>
> ---
> drivers/phy/Kconfig | 1 +
> drivers/phy/Makefile | 1 +
> drivers/phy/axiado/Kconfig | 11 ++
> drivers/phy/axiado/Makefile | 1 +
> drivers/phy/axiado/phy-axiado-emmc.c | 221 +++++++++++++++++++++++++++++++++++
> 5 files changed, 235 insertions(+)
>
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 678dd0452f0aa0597773433f04d2a9ba77474d2a..b802274ea45a84bd36d7c0b7fb90e368a5c018b4 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -103,6 +103,7 @@ config PHY_NXP_PTN3222
>
> source "drivers/phy/allwinner/Kconfig"
> source "drivers/phy/amlogic/Kconfig"
> +source "drivers/phy/axiado/Kconfig"
> source "drivers/phy/broadcom/Kconfig"
> source "drivers/phy/cadence/Kconfig"
> source "drivers/phy/freescale/Kconfig"
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index bfb27fb5a494283d7fd05dd670ebd1b12df8b1a1..f1b9e4a8673bcde3fdc0fdc06a3deddb5785ced1 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -15,6 +15,7 @@ obj-$(CONFIG_PHY_AIROHA_PCIE) += phy-airoha-pcie.o
> obj-$(CONFIG_PHY_NXP_PTN3222) += phy-nxp-ptn3222.o
> obj-y += allwinner/ \
> amlogic/ \
> + axiado/ \
> broadcom/ \
> cadence/ \
> freescale/ \
> diff --git a/drivers/phy/axiado/Kconfig b/drivers/phy/axiado/Kconfig
> new file mode 100644
> index 0000000000000000000000000000000000000000..d159e0345345987c7f48dcd12d3237997735d2b5
> --- /dev/null
> +++ b/drivers/phy/axiado/Kconfig
> @@ -0,0 +1,11 @@
> +#
> +# PHY drivers for Axiado platforms
> +#
> +
> +config PHY_AX3000_EMMC
> + tristate "Axiado eMMC PHY driver"
> + depends on OF && (ARCH_AXIADO || COMPILE_TEST)
> + select GENERIC_PHY
> + help
> + Enables this to support for the AX3000 EMMC PHY driver.
> + If unsure, say N.
> diff --git a/drivers/phy/axiado/Makefile b/drivers/phy/axiado/Makefile
> new file mode 100644
> index 0000000000000000000000000000000000000000..1e2b1ba016092eaffdbd7acbd9cdc8577d79b35c
> --- /dev/null
> +++ b/drivers/phy/axiado/Makefile
> @@ -0,0 +1 @@
> +obj-$(CONFIG_PHY_AX3000_EMMC) += phy-axiado-emmc.o
> diff --git a/drivers/phy/axiado/phy-axiado-emmc.c b/drivers/phy/axiado/phy-axiado-emmc.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..28d2a30c3b35ee7dba917487959e226941e8ea4b
> --- /dev/null
> +++ b/drivers/phy/axiado/phy-axiado-emmc.c
> @@ -0,0 +1,221 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Axiado eMMC PHY driver
> + *
> + * Copyright (C) 2017 Arasan Chip Systems Inc.
> + * Copyright (C) 2022-2025 Axiado Corporation (or its affiliates).
2026
> + *
> + * Based on Arasan Driver (sdhci-pci-arasan.c)
> + * sdhci-pci-arasan.c - Driver for Arasan PCI Controller with integrated phy.
> + */
> +#include <linux/bitfield.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +
> +/* Arasan eMMC 5.1 - PHY configuration registers */
> +#define CAP_REG_IN_S1_LSB 0x00
> +#define CAP_REG_IN_S1_MSB 0x04
> +#define PHY_CTRL_1 0x38
> +#define PHY_CTRL_2 0x3C
smaller hex case please, here and other places
> +#define PHY_CTRL_3 0x40
> +#define STATUS 0x50
> +
> +#define DLL_ENBL BIT(26)
> +#define RTRIM_EN BIT(21)
> +#define PDB_ENBL BIT(23)
> +#define RETB_ENBL BIT(1)
> +
> +#define REN_STRB BIT(27)
> +#define REN_CMD BIT(12)
> +#define REN_DAT0 BIT(13)
> +#define REN_DAT1 BIT(14)
> +#define REN_DAT2 BIT(15)
> +#define REN_DAT3 BIT(16)
> +#define REN_DAT4 BIT(17)
> +#define REN_DAT5 BIT(18)
> +#define REN_DAT6 BIT(19)
> +#define REN_DAT7 BIT(20)
> +#define REN_CMD_EN (REN_CMD | REN_DAT0 | REN_DAT1 | REN_DAT2 | \
> + REN_DAT3 | REN_DAT4 | REN_DAT5 | REN_DAT6 | REN_DAT7)
> +
> +/* Pull-UP Enable on CMD Line */
> +#define PU_CMD BIT(3)
> +#define PU_DAT0 BIT(4)
> +#define PU_DAT1 BIT(5)
> +#define PU_DAT2 BIT(6)
> +#define PU_DAT3 BIT(7)
> +#define PU_DAT4 BIT(8)
> +#define PU_DAT5 BIT(9)
> +#define PU_DAT6 BIT(10)
> +#define PU_DAT7 BIT(11)
> +#define PU_CMD_EN (PU_CMD | PU_DAT0 | PU_DAT1 | PU_DAT2 | PU_DAT3 | \
> + PU_DAT4 | PU_DAT5 | PU_DAT6 | PU_DAT7)
The bit define are used only once, why not define the cmd with
respective bits here
> +
> +/* Selection value for the optimum delay from 1-32 output tap lines */
> +#define OTAP_DLY 0x02
> +/* DLL charge pump current trim default [1000] */
> +#define DLL_TRM_ICP 0x08
> +/* Select the frequency range of DLL Operation */
> +#define FRQ_SEL 0x01
> +
> +#define OTAP_SEL_MASK GENMASK(10, 7)
> +#define DLL_TRM_MASK GENMASK(25, 22)
> +#define DLL_FRQSEL_MASK GENMASK(27, 25)
> +
> +#define OTAP_SEL(x) (FIELD_PREP(OTAP_SEL_MASK, x) | OTAPDLY_EN)
> +#define DLL_TRM(x) (FIELD_PREP(DLL_TRM_MASK, x) | DLL_ENBL)
> +#define DLL_FRQSEL(x) FIELD_PREP(DLL_FRQSEL_MASK, x)
> +
> +#define OTAPDLY_EN BIT(11)
> +
> +#define SEL_DLY_RXCLK BIT(18)
> +#define SEL_DLY_TXCLK BIT(19)
> +
> +#define CALDONE_MASK 0x40
> +#define DLL_RDY_MASK 0x1
> +#define MAX_CLK_BUF0 BIT(20)
> +#define MAX_CLK_BUF1 BIT(21)
> +#define MAX_CLK_BUF2 BIT(22)
> +
> +#define CLK_MULTIPLIER 0xC008E
> +#define POLL_TIMEOUT_MS 3000
> +#define POLL_DELAY_US 100
> +
> +struct axiado_emmc_phy {
> + void __iomem *reg_base;
> + struct device *dev;
> +};
> +
> +static int axiado_emmc_phy_init(struct phy *phy)
> +{
> + struct axiado_emmc_phy *ax_phy = phy_get_drvdata(phy);
> + struct device *dev = ax_phy->dev;
> + u32 val;
> + int ret;
> +
> + val = readl(ax_phy->reg_base + PHY_CTRL_1);
> + writel(val | RETB_ENBL | RTRIM_EN, ax_phy->reg_base + PHY_CTRL_1);
> +
> + val = readl(ax_phy->reg_base + PHY_CTRL_3);
> + writel(val | PDB_ENBL, ax_phy->reg_base + PHY_CTRL_3);
> +
> + ret = readl_poll_timeout(ax_phy->reg_base + STATUS, val,
> + val & CALDONE_MASK, POLL_DELAY_US,
> + POLL_TIMEOUT_MS * 1000);
> + if (ret) {
> + dev_err(dev, "PHY calibration timeout\n");
> + return ret;
> + }
> +
> + val = readl(ax_phy->reg_base + PHY_CTRL_1);
> + writel(val | REN_CMD_EN | PU_CMD_EN, ax_phy->reg_base + PHY_CTRL_1);
> +
> + val = readl(ax_phy->reg_base + PHY_CTRL_2);
> + writel(val | REN_STRB, ax_phy->reg_base + PHY_CTRL_2);
> +
> + val = readl(ax_phy->reg_base + PHY_CTRL_3);
> + writel(val | MAX_CLK_BUF0 | MAX_CLK_BUF1 | MAX_CLK_BUF2,
> + ax_phy->reg_base + PHY_CTRL_3);
> +
> + writel(CLK_MULTIPLIER, ax_phy->reg_base + CAP_REG_IN_S1_MSB);
> +
> + val = readl(ax_phy->reg_base + PHY_CTRL_3);
> + writel(val | SEL_DLY_RXCLK | SEL_DLY_TXCLK,
> + ax_phy->reg_base + PHY_CTRL_3);
> +
> + return 0;
> +}
> +
> +static int axiado_emmc_phy_power_on(struct phy *phy)
> +{
> + struct axiado_emmc_phy *ax_phy = phy_get_drvdata(phy);
> + struct device *dev = ax_phy->dev;
> + u32 val;
> + int ret;
> +
> + val = readl(ax_phy->reg_base + PHY_CTRL_1);
> + writel(val | RETB_ENBL, ax_phy->reg_base + PHY_CTRL_1);
> +
> + val = readl(ax_phy->reg_base + PHY_CTRL_3);
> + writel(val | PDB_ENBL, ax_phy->reg_base + PHY_CTRL_3);
> +
> + val = readl(ax_phy->reg_base + PHY_CTRL_2);
> + writel(val | OTAP_SEL(OTAP_DLY), ax_phy->reg_base + PHY_CTRL_2);
> +
> + val = readl(ax_phy->reg_base + PHY_CTRL_1);
> + writel(val | DLL_TRM(DLL_TRM_ICP), ax_phy->reg_base + PHY_CTRL_1);
> +
> + val = readl(ax_phy->reg_base + PHY_CTRL_3);
> + writel(val | DLL_FRQSEL(FRQ_SEL), ax_phy->reg_base + PHY_CTRL_3);
> +
> + ret = read_poll_timeout(readl, val, val & DLL_RDY_MASK, POLL_DELAY_US,
> + POLL_TIMEOUT_MS * 1000, false,
> + ax_phy->reg_base + STATUS);
> + if (ret) {
> + dev_err(dev, "DLL ready timeout\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static const struct phy_ops axiado_emmc_phy_ops = {
> + .init = axiado_emmc_phy_init,
> + .power_on = axiado_emmc_phy_power_on,
no power_off?
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* Re: [PATCH v6 3/8] phy: Add driver for EyeQ5 Ethernet PHY wrapper
From: Vinod Koul @ 2026-02-27 14:08 UTC (permalink / raw)
To: Théo Lebrun
Cc: Vladimir Kondratiev, Grégory Clement, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kishon Vijay Abraham I,
Michael Turquette, Stephen Boyd, Philipp Zabel,
Thomas Bogendoerfer, Neil Armstrong, linux-mips, devicetree,
linux-kernel, linux-phy, linux-clk, Benoît Monin,
Tawfik Bayouk, Thomas Petazzoni, Luca Ceresoli
In-Reply-To: <DGO5XYKELMA3.14FPOZ2FCD8NN@bootlin.com>
On 25-02-26, 16:54, Théo Lebrun wrote:
> On Wed Feb 25, 2026 at 4:00 PM CET, Vinod Koul wrote:
> > On 27-01-26, 18:09, Théo Lebrun wrote:
> >> EyeQ5 embeds a system-controller called OLB. It features many unrelated
> >> registers, and some of those are registers used to configure the
> >> integration of the RGMII/SGMII Cadence PHY used by MACB/GEM instances.
> >>
> >> Wrap in a neat generic PHY provider, exposing two PHYs with standard
> >> phy_init() / phy_set_mode() / phy_power_on() operations.
> >
> > Is there a dependency of this patch with rest of the series. If not
> > please post different series for subsystems.
>
> ACK. It felt sensible to keep patches close together to understand their
> reasoning.
> - clk patches are there because they imply we get a dev->of_node.
> Without them we don't and therefore the driver is useless.
> - DTS/MIPS patches are there because they exploit this new driver.
> They show the first users of this driver.
You can add that in cover letter for people interested to read. It is
easy for me to pick a series rather than find which patches to review
and apply
>
> Will split for next revision.
Thanks
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* Re: [PATCH v7 1/2] phy: sort Kconfig and Makefile
From: Vinod Koul @ 2026-02-27 13:55 UTC (permalink / raw)
To: Théo Lebrun
Cc: Neil Armstrong, linux-phy, linux-kernel, linux-mips,
Vladimir Kondratiev, Gregory CLEMENT, Benoît Monin,
Tawfik Bayouk, Thomas Petazzoni, Luca Ceresoli
In-Reply-To: <20260225-macb-phy-v7-1-e5211a61db56@bootlin.com>
On 25-02-26, 17:54, Théo Lebrun wrote:
> Neither Kconfig nor Makefile are sorted; reorder them.
>
> $ diff -U100 <(grep ^config drivers/phy/Kconfig) \
> <(grep ^config drivers/phy/Kconfig | sort)
>
> $ diff -U100 <(grep ^obj-\\$ drivers/phy/Makefile) \
> <(grep ^obj-\\$ drivers/phy/Makefile | sort)
>
> PHY_COMMON_PROPS{,_TEST} are kept at the top which does not respect
> sorting order.
>
> Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
> ---
> drivers/phy/Kconfig | 86 ++++++++++++++++++++++++++--------------------------
> drivers/phy/Makefile | 8 ++---
> 2 files changed, 47 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 02467dfd4fb0..c86e90027443 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -47,6 +47,26 @@ config GENERIC_PHY_MIPI_DPHY
> Provides a number of helpers a core functions for MIPI D-PHY
> drivers to us.
>
> +config PHY_AIROHA_PCIE
> + tristate "Airoha PCIe-PHY Driver"
> + depends on ARCH_AIROHA || COMPILE_TEST
> + depends on OF
> + select GENERIC_PHY
> + help
> + Say Y here to add support for Airoha PCIe PHY driver.
> + This driver create the basic PHY instance and provides initialize
> + callback for PCIe GEN3 port.
> +
> +config PHY_CAN_TRANSCEIVER
> + tristate "CAN transceiver PHY"
> + select GENERIC_PHY
> + select MULTIPLEXER
> + help
> + This option enables support for CAN transceivers as a PHY. This
> + driver provides function for putting the transceivers in various
> + functional modes using gpios and sets the attribute max link
> + rate, for CAN drivers.
> +
> config PHY_GOOGLE_USB
> tristate "Google Tensor SoC USB PHY driver"
> select GENERIC_PHY
> @@ -69,6 +89,17 @@ config PHY_LPC18XX_USB_OTG
> This driver is need for USB0 support on LPC18xx/43xx and takes
> care of enabling and clock setup.
>
> +config PHY_NXP_PTN3222
> + tristate "NXP PTN3222 1-port eUSB2 to USB2 redriver"
> + depends on I2C
> + depends on OF
> + select GENERIC_PHY
> + help
> + Enable this to support NXP PTN3222 1-port eUSB2 to USB2 Redriver.
> + This redriver performs translation between eUSB2 and USB2 signalling
> + schemes. It supports all three USB 2.0 data rates: Low Speed, Full
> + Speed and High Speed.
> +
> config PHY_PISTACHIO_USB
> tristate "IMG Pistachio USB2.0 PHY driver"
> depends on MIPS || COMPILE_TEST
> @@ -84,6 +115,18 @@ config PHY_SNPS_EUSB2
> Enable support for the USB high-speed SNPS eUSB2 phy on select
> SoCs. The PHY is usually paired with a Synopsys DWC3 USB controller.
>
> +config PHY_SPACEMIT_K1_PCIE
> + tristate "PCIe and combo PHY driver for the SpacemiT K1 SoC"
> + depends on ARCH_SPACEMIT || COMPILE_TEST
> + depends on COMMON_CLK
> + depends on HAS_IOMEM
> + depends on OF
> + select GENERIC_PHY
> + default ARCH_SPACEMIT
> + help
> + Enable support for the PCIe and USB 3 combo PHY and two
> + PCIe-only PHYs used in the SpacemiT K1 SoC.
I moved this into spacemit directory and while at it notice the file is
not sorted and patched that up.20260223065743.395539-1-vkoul@kernel.org
Sorry I missed this and earlier one
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* Re: [PATCH v11 5/9] phy: renesas: rcar-gen3-usb2: drop helper getting optional mux-state
From: Vinod Koul @ 2026-02-27 13:53 UTC (permalink / raw)
To: Josua Mayer
Cc: Marc Kleine-Budde, Vincent Mailhol, Neil Armstrong, Peter Rosin,
Aaro Koskinen, Andreas Kemnade, Kevin Hilman, Roger Quadros,
Tony Lindgren, Janusz Krzysztofik, Vignesh R, Andi Shyti,
Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm, Wolfram Sang, Yoshihiro Shimoda,
Yazan Shhady, Jon Nettleton, Vladimir Oltean, Mikhail Anikin,
linux-can, linux-phy, linux-kernel, linux-omap, linux-i2c,
linux-mmc, devicetree, linux-renesas-soc
In-Reply-To: <20260226-rz-sdio-mux-v11-5-c2a350f9bbd3@solid-run.com>
On 26-02-26, 15:21, Josua Mayer wrote:
> Multiplexer subsystem has now added helpers for getting managed optional
> mux-state.
>
> Switch to the new devm_mux_state_get_optional_selected helper.
Acked-by: Vinod Koul <vkoul@kernel.org>
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* Re: [PATCH v11 2/9] phy: renesas: rcar-gen3-usb2: rename local mux helper to avoid conflict
From: Vinod Koul @ 2026-02-27 13:52 UTC (permalink / raw)
To: Josua Mayer
Cc: Marc Kleine-Budde, Vincent Mailhol, Neil Armstrong, Peter Rosin,
Aaro Koskinen, Andreas Kemnade, Kevin Hilman, Roger Quadros,
Tony Lindgren, Janusz Krzysztofik, Vignesh R, Andi Shyti,
Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm, Wolfram Sang, Yoshihiro Shimoda,
Yazan Shhady, Jon Nettleton, Vladimir Oltean, Mikhail Anikin,
linux-can, linux-phy, linux-kernel, linux-omap, linux-i2c,
linux-mmc, devicetree, linux-renesas-soc
In-Reply-To: <20260226-rz-sdio-mux-v11-2-c2a350f9bbd3@solid-run.com>
On 26-02-26, 15:21, Josua Mayer wrote:
> Rename the temporary devm_mux_state_get_optional function to avoid
> conflict with upcoming implementation in multiplexer subsystem.
Acked-by: Vinod Koul <vkoul@kernel.org>
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* Re: [PATCH v11 1/9] phy: can-transceiver: rename temporary helper function to avoid conflict
From: Vinod Koul @ 2026-02-27 13:52 UTC (permalink / raw)
To: Josua Mayer
Cc: Marc Kleine-Budde, Vincent Mailhol, Neil Armstrong, Peter Rosin,
Aaro Koskinen, Andreas Kemnade, Kevin Hilman, Roger Quadros,
Tony Lindgren, Janusz Krzysztofik, Vignesh R, Andi Shyti,
Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm, Wolfram Sang, Yoshihiro Shimoda,
Yazan Shhady, Jon Nettleton, Vladimir Oltean, Mikhail Anikin,
linux-can, linux-phy, linux-kernel, linux-omap, linux-i2c,
linux-mmc, devicetree, linux-renesas-soc
In-Reply-To: <20260226-rz-sdio-mux-v11-1-c2a350f9bbd3@solid-run.com>
On 26-02-26, 15:21, Josua Mayer wrote:
> Rename the temporary devm_mux_state_get_optional function to avoid
> conflict with upcoming implementation in multiplexer subsystem.
Acked-by: Vinod Koul <vkoul@kernel.org>
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* Re: [PATCH net-next 0/9] net: stmmac: qcom-ethqos: further serdes reorganisation
From: Vinod Koul @ 2026-02-27 13:47 UTC (permalink / raw)
To: Russell King (Oracle)
Cc: Andrew Lunn, Alexandre Torgue, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, linux-arm-kernel, linux-arm-msm,
linux-phy, linux-stm32, Mohd Ayaan Anwar, Neil Armstrong, netdev,
Paolo Abeni
In-Reply-To: <aZ66uXCwGgH7B_A-@shell.armlinux.org.uk>
On 25-02-26, 09:02, Russell King (Oracle) wrote:
> Note: only 8 patches in this series, not 9 as the subject line says,
> as the set_clk_tx_rate() patch became part of the first series.
>
> On Wed, Feb 25, 2026 at 09:00:41AM +0000, Russell King (Oracle) wrote:
> > This is part 2 of the qcom-ethqos series, part 1 has now been merged.
> >
> > This part of the series focuses on the generic PHY driver, but these
> > changes have dependencies on the ethernet driver, hence why
> > it will need to go via net-next. Furthermore, subsequent changes
> > depend on these patches.
This lgtm, can we get signed tag so that we can pull this into phy tree
as well
Thanks
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* Re: [PATCH net-next 7/8] phy: qcom-sgmii-eth: relax order of .power_on() vs .set_mode*()
From: Vinod Koul @ 2026-02-27 13:45 UTC (permalink / raw)
To: Russell King (Oracle)
Cc: Andrew Lunn, Alexandre Torgue, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, linux-arm-kernel, linux-arm-msm,
linux-phy, linux-stm32, Mohd Ayaan Anwar, Neil Armstrong, netdev,
Paolo Abeni
In-Reply-To: <E1vvCcE-0000000ArLT-1COQ@rmk-PC.armlinux.org.uk>
On 25-02-26, 10:59, Russell King (Oracle) wrote:
> Allow any order of the .power_on() and .set_mode*() methods as per the
> recent discussion. This means phy_power_on() with this SerDes will now
> restore the previous setup without requiring a subsequent
> phy_set_mode*() call.
>
> Tested-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Acked-by: Vinod Koul <vkoul@kernel.org>
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* Re: [PATCH net-next 6/8] phy: qcom-sgmii-eth: remove qcom_dwmac_sgmii_phy_interface()
From: Vinod Koul @ 2026-02-27 13:45 UTC (permalink / raw)
To: Russell King (Oracle)
Cc: Andrew Lunn, Alexandre Torgue, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, linux-arm-kernel, linux-arm-msm,
linux-phy, linux-stm32, Mohd Ayaan Anwar, Neil Armstrong, netdev,
Paolo Abeni
In-Reply-To: <E1vvCc9-0000000ArLG-0if1@rmk-PC.armlinux.org.uk>
On 25-02-26, 10:59, Russell King (Oracle) wrote:
> Now that qcom_dwmac_sgmii_phy_interface() only serves to validate the
> passed interface mode, combine it with qcom_dwmac_sgmii_phy_validate(),
> and use qcom_dwmac_sgmii_phy_validate() to validate the mode in
> qcom_dwmac_sgmii_phy_set_mode().
>
> Tested-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Acked-by: Vinod Koul <vkoul@kernel.org>
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* Re: [PATCH net-next 5/8] phy: qcom-sgmii-eth: use PHY interface mode for SerDes settings
From: Vinod Koul @ 2026-02-27 13:43 UTC (permalink / raw)
To: Russell King (Oracle)
Cc: Andrew Lunn, Alexandre Torgue, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, linux-arm-kernel, linux-arm-msm,
linux-phy, linux-stm32, Mohd Ayaan Anwar, Neil Armstrong, netdev,
Paolo Abeni
In-Reply-To: <E1vvCc4-0000000ArLA-0Eix@rmk-PC.armlinux.org.uk>
On 25-02-26, 10:59, Russell King (Oracle) wrote:
> As established in the previous commit, using SPEED_1000 and SPEED_2500
> does not make sense for a SerDes due to the PCS encoding that is used
> over the SerDes link, which inflates the data rate at the SerDes. Thus,
> the use of these constants in a SerDes driver is incorrect.
>
> Since qcom-sgmii-eth no longer implements phy_set_speed(), but instead
> uses the PHY interface mode passed via the .set_mode() method, convert
> the driver to use the PHY interface mode internally to decide whether
> to configure the SerDes for 1.25Gbps or 3.125Gbps mode.
Acked-by: Vinod Koul <vkoul@kernel.org>
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* Re: [PATCH net-next 4/8] phy: qcom-sgmii-eth: remove .set_speed() implementation
From: Vinod Koul @ 2026-02-27 13:42 UTC (permalink / raw)
To: Russell King (Oracle)
Cc: Andrew Lunn, Alexandre Torgue, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, linux-arm-kernel, linux-arm-msm,
linux-phy, linux-stm32, Mohd Ayaan Anwar, Neil Armstrong, netdev,
Paolo Abeni
In-Reply-To: <E1vvCby-0000000ArL4-3x4U@rmk-PC.armlinux.org.uk>
On 25-02-26, 10:59, Russell King (Oracle) wrote:
> Now that the qcom-ethqos driver has migrated to use phy_set_mode_ext()
> rather than phy_set_speed() to configure the SerDes, the support for
> phy_set_speed() is now obsolete. Remove support for this method.
>
> Using the MAC speed for the SerDes is never correct due to the PCS
> encoding. For SGMII and 2500BASE-X, the PCS uses 8B10B encoding, and
> so:
>
> MAC rate * PCS output bits / PCS input bits = SerDes rate
> 1000M * 10 / 8 = 1250M
> 2500M * 10 / 8 = 3125M
>
> Tested-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Acked-by: Vinod Koul <vkoul@kernel.org>
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* [PATCH] phy: qcom: qmp-usbc: Fix out-of-bounds array access in dp swing config
From: Xiangxu Yin via B4 Relay @ 2026-02-27 12:15 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Dmitry Baryshkov
Cc: linux-arm-msm, linux-phy, linux-kernel, fange.zhang, yongxing.mou,
li.liu, tingwei.zhang, Konrad Dybcio, Dan Carpenter, Xiangxu Yin
From: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com>
swing_tbl and pre_emphasis_tbl are 4x4 arrays (valid indices 0-3), but
the boundary check uses "> 4" instead of ">= 4", allowing index 4 to
cause an out-of-bounds access.
Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
Fixes: 81791c45c8e0 ("phy: qcom: qmp-usbc: Add QCS615 USB/DP PHY config and DP mode support")
Signed-off-by: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com>
---
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
index 14feb77789b3..0dd7000614f4 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
@@ -794,7 +794,7 @@ static int qmp_v2_configure_dp_swing(struct qmp_usbc *qmp)
p_level = max(p_level, dp_opts->pre[i]);
}
- if (v_level > 4 || p_level > 4) {
+ if (v_level >= 4 || p_level >= 4) {
dev_err(qmp->dev, "Invalid v(%d) | p(%d) level)\n",
v_level, p_level);
return -EINVAL;
---
base-commit: 7d6661873f6b54c75195780a40d66bad3d482d8f
change-id: 20260227-master-8b948c5633ea
Best regards,
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* Re: [PATCH v3 1/2] dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schema
From: Bryan O'Donoghue @ 2026-02-27 9:47 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Neil Armstrong,
Bryan O'Donoghue, Vladimir Zapolskiy, linux-arm-msm,
linux-phy, linux-media, devicetree, linux-kernel
In-Reply-To: <20260227-overjoyed-spiritual-saluki-7561c2@quoll>
On 27/02/2026 09:41, Krzysztof Kozlowski wrote:
> On Thu, Feb 26, 2026 at 12:34:25PM +0000, Bryan O'Donoghue wrote:
>> Add a base schema initially compatible with x1e80100 to describe MIPI CSI2
>> PHY devices.
>>
>> The hardware can support both C-PHY and D-PHY modes. The CSIPHY devices
>> have their own pinouts on the SoC as well as their own individual voltage
>> rails.
>>
>> The need to model voltage rails on a per-PHY basis leads us to define
>> CSIPHY devices as individual nodes.
>>
>> Two nice outcomes in terms of schema and DT arise from this change.
>>
>> 1. The ability to define on a per-PHY basis voltage rails.
>> 2. The ability to require those voltage.
>>
>> We have had a complete bodge upstream for this where a single set of
>> voltage rail for all CSIPHYs has been buried inside of CAMSS.
>>
>> Much like the I2C bus which is dedicated to Camera sensors - the CCI bus in
>> CAMSS parlance, the CSIPHY devices should be individually modelled.
>>
>> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
>> ---
>> .../bindings/phy/qcom,x1e80100-csi2-phy.yaml | 114 +++++++++++++++++++++
>> 1 file changed, 114 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
>> new file mode 100644
>> index 0000000000000..c937d26ccbda9
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
>> @@ -0,0 +1,114 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/phy/qcom,x1e80100-csi2-phy.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm CSI2 PHY
>
> Qualcomm SoC CSI2 PHY
>
>
>> +
>> +maintainers:
>> + - Bryan O'Donoghue <bod@kernel.org>
>> +
>> +description:
>> + Qualcomm MIPI CSI2 C-PHY/D-PHY combination PHY. Connects MIPI CSI2 sensors
>> + to Qualcomm's Camera CSI Decoder. The PHY supports both C-PHY and D-PHY
>> + modes.
>
> So just to be clear: this is not MIPI CSI, but only the CSI PHY? There
> are no ports here, which seems fine for the phy and will be in the MIPI
> CSI block?
CAMSS ports map to the CSID - CSI Decoder yes.
>
>> +
>> +properties:
>> + compatible:
>> + const: qcom,x1e80100-csi2-phy
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + "#phy-cells":
>> + const: 1
>> +
>> + clocks:
>> + maxItems: 4
>> +
>> + clock-names:
>> + items:
>> + - const: csiphy
>
> probably: core or iface
>
>> + - const: csiphy_timer
>
> timer
>
>> + - const: camnoc_axi
>
> axi or noc
>
>> + - const: cpas_ahb
>
> bus, ahb or cpas, depending whether this is only one ahb or this is bus of
> some cpas subblock
>
> See also: https://lore.kernel.org/all/20260115-sm6150_evk-v3-2-81526dd15543@oss.qualcomm.com/
>
>
>> +
>> + interrupts:
>> + maxItems: 1
>> +
>> + operating-points-v2:
>
> Just true. It is not an array.
LOL I asked a chatbot to review my submission and it told me to change
this from true to a list.
€90 subscription well spent...
Thanks for review.
---
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* Re: [PATCH v3 1/2] dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schema
From: Krzysztof Kozlowski @ 2026-02-27 9:41 UTC (permalink / raw)
To: Bryan O'Donoghue
Cc: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Neil Armstrong,
Bryan O'Donoghue, Vladimir Zapolskiy, linux-arm-msm,
linux-phy, linux-media, devicetree, linux-kernel
In-Reply-To: <20260226-x1e-csi2-phy-v3-1-11e608759410@linaro.org>
On Thu, Feb 26, 2026 at 12:34:25PM +0000, Bryan O'Donoghue wrote:
> Add a base schema initially compatible with x1e80100 to describe MIPI CSI2
> PHY devices.
>
> The hardware can support both C-PHY and D-PHY modes. The CSIPHY devices
> have their own pinouts on the SoC as well as their own individual voltage
> rails.
>
> The need to model voltage rails on a per-PHY basis leads us to define
> CSIPHY devices as individual nodes.
>
> Two nice outcomes in terms of schema and DT arise from this change.
>
> 1. The ability to define on a per-PHY basis voltage rails.
> 2. The ability to require those voltage.
>
> We have had a complete bodge upstream for this where a single set of
> voltage rail for all CSIPHYs has been buried inside of CAMSS.
>
> Much like the I2C bus which is dedicated to Camera sensors - the CCI bus in
> CAMSS parlance, the CSIPHY devices should be individually modelled.
>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> ---
> .../bindings/phy/qcom,x1e80100-csi2-phy.yaml | 114 +++++++++++++++++++++
> 1 file changed, 114 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
> new file mode 100644
> index 0000000000000..c937d26ccbda9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
> @@ -0,0 +1,114 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/qcom,x1e80100-csi2-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm CSI2 PHY
Qualcomm SoC CSI2 PHY
> +
> +maintainers:
> + - Bryan O'Donoghue <bod@kernel.org>
> +
> +description:
> + Qualcomm MIPI CSI2 C-PHY/D-PHY combination PHY. Connects MIPI CSI2 sensors
> + to Qualcomm's Camera CSI Decoder. The PHY supports both C-PHY and D-PHY
> + modes.
So just to be clear: this is not MIPI CSI, but only the CSI PHY? There
are no ports here, which seems fine for the phy and will be in the MIPI
CSI block?
> +
> +properties:
> + compatible:
> + const: qcom,x1e80100-csi2-phy
> +
> + reg:
> + maxItems: 1
> +
> + "#phy-cells":
> + const: 1
> +
> + clocks:
> + maxItems: 4
> +
> + clock-names:
> + items:
> + - const: csiphy
probably: core or iface
> + - const: csiphy_timer
timer
> + - const: camnoc_axi
axi or noc
> + - const: cpas_ahb
bus, ahb or cpas, depending whether this is only one ahb or this is bus of
some cpas subblock
See also: https://lore.kernel.org/all/20260115-sm6150_evk-v3-2-81526dd15543@oss.qualcomm.com/
> +
> + interrupts:
> + maxItems: 1
> +
> + operating-points-v2:
Just true. It is not an array.
> + maxItems: 1
Also opp-table like in other schemas.
> +
> + power-domains:
> + maxItems: 1
> +
> + vdda-0p8-supply:
> + description: Phandle to a 0.8V regulator supply to a PHY.
> +
> + vdda-1p2-supply:
> + description: Phandle to 1.2V regulator supply to a PHY.
> +
> +required:
> + - compatible
> + - reg
> + - "#phy-cells"
> + - clocks
> + - clock-names
> + - interrupts
> + - operating-points-v2
> + - power-domains
> + - vdda-0p8-supply
> + - vdda-1p2-supply
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/clock/qcom,x1e80100-camcc.h>
> + #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
> + #include <dt-bindings/phy/phy.h>
> +
> + csiphy@ace4000 {
phy@ or csi-phy@
> + compatible = "qcom,x1e80100-csi2-phy";
> + reg = <0x0ace4000 0x2000>;
> + #phy-cells = <1>;
> +
> + clocks = <&camcc CAM_CC_CSIPHY0_CLK>,
> + <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
> + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>,
> + <&camcc CAM_CC_CPAS_AHB_CLK>;
> + clock-names = "csiphy",
> + "csiphy_timer",
> + "camnoc_axi",
> + "cpas_ahb";
> +
> + operating-points-v2 = <&csiphy_opp_table>;
> +
> + interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>;
> +
> + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> +
> + vdda-0p8-supply = <&vreg_l2c_0p8>;
> + vdda-1p2-supply = <&vreg_l1c_1p2>;
> + };
> +
> + csiphy_opp_table: opp-table-csiphy {
Drop entire node, not relevant here.
Best regards,
Krzysztof
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* Re: [bug report] phy: qcom: qmp-usbc: Add QCS615 USB/DP PHY config and DP mode support
From: Xiangxu Yin @ 2026-02-27 5:11 UTC (permalink / raw)
To: Konrad Dybcio, Dan Carpenter
Cc: Neil Armstrong, linux-arm-msm, linux-phy, linux-kernel,
Dmitry Baryshkov, li.liu
In-Reply-To: <e110546e-dd18-4ebe-9281-adfbdde98d7a@oss.qualcomm.com>
On 2/17/2026 11:27 PM, Konrad Dybcio wrote:
> On 2/6/26 2:39 PM, Dan Carpenter wrote:
>> [ Smatch checking is paused while we raise funding. #SadFace
>> https://lore.kernel.org/all/aTaiGSbWZ9DJaGo7@stanley.mountain/ -dan ]
>>
>> Hello Xiangxu Yin,
>>
>> Commit 81791c45c8e0 ("phy: qcom: qmp-usbc: Add QCS615 USB/DP PHY
>> config and DP mode support") from Dec 15, 2025 (linux-next), leads to
>> the following Smatch static checker warning:
>>
>> drivers/phy/qualcomm/phy-qcom-qmp-usbc.c:803 qmp_v2_configure_dp_swing()
>> index hardmax out of bounds '(*cfg->swing_tbl)[v_level]' size=4 max='4' rl='0-4'
>>
>> drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
>> 777 static int qmp_v2_configure_dp_swing(struct qmp_usbc *qmp)
>> 778 {
>> 779 const struct qmp_phy_cfg *cfg = qmp->cfg;
>> 780 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
>> 781 void __iomem *tx = qmp->dp_tx;
>> 782 void __iomem *tx2 = qmp->dp_tx2;
>> 783 unsigned int v_level = 0, p_level = 0;
>> 784 u8 voltage_swing_cfg, pre_emphasis_cfg;
>> 785 int i;
>> 786
>> 787 if (dp_opts->lanes > 4) {
>> 788 dev_err(qmp->dev, "Invalid lane_num(%d)\n", dp_opts->lanes);
>> 789 return -EINVAL;
>> 790 }
>> 791
>> 792 for (i = 0; i < dp_opts->lanes; i++) {
>> 793 v_level = max(v_level, dp_opts->voltage[i]);
>> 794 p_level = max(p_level, dp_opts->pre[i]);
>> 795 }
>> 796
>> 797 if (v_level > 4 || p_level > 4) {
>>
>> These should be >= 4 instead of >.
>>
>> 798 dev_err(qmp->dev, "Invalid v(%d) | p(%d) level)\n",
>> 799 v_level, p_level);
>> 800 return -EINVAL;
>> 801 }
>> 802
>> --> 803 voltage_swing_cfg = (*cfg->swing_tbl)[v_level][p_level];
>> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>> This is a 4x4 array.
> Thanks Dan for the report
>
> Xiangxu, are you planning to send a patch to address that?
>
> Konrad
Thanks for the notice, Dan & Konrad.
I just got back from a long leave and will submit the relevant patches as soon as possible.
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* Re: [PATCH v3 2/2] phy: qcom-mipi-csi2: Add a CSI2 MIPI DPHY driver
From: Dmitry Baryshkov @ 2026-02-27 1:40 UTC (permalink / raw)
To: Bryan O'Donoghue
Cc: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Neil Armstrong,
Bryan O'Donoghue, Vladimir Zapolskiy, linux-arm-msm,
linux-phy, linux-media, devicetree, linux-kernel
In-Reply-To: <20260226-x1e-csi2-phy-v3-2-11e608759410@linaro.org>
On Thu, Feb 26, 2026 at 12:34:26PM +0000, Bryan O'Donoghue wrote:
> Add a new MIPI CSI2 driver in DPHY mode initially. The entire set of
> existing CAMSS CSI PHY init sequences are imported in order to save time
> and effort in later patches.
>
> The following devices are supported in this drop:
> "qcom,x1e80100-csi2-phy"
>
> In-line with other PHY drivers the process node is included in the name. At
> the moment we follow the assignment of lane positions - the bitmap of
> physical input lanes to logical lane numbers as a linear list per the
> existing DPHY @lanes data-member.
>
> This is fine for us in upstream at the moment since we also map the lanes
> contiguously but, our hardware can support different lane mappings so we
> should in the future extend out the DPHY structure to capture the mapping.
>
> The Qualcomm 3PH class of PHYs can do both DPHY and CPHY mode. For now only
> DPHY is supported.
>
> In porting some of the logic over from camss-csiphy*.c to here its also
> possible to rationalise some of the code.
>
> In particular use of regulator_bulk and clk_bulk as well as dropping the
> seemingly useless and unused interrupt handler.
>
> The PHY sequences and a lot of the logic that goes with them are well
> proven in CAMSS and mature so the main thing to watch out for here is how
> to get the right sequencing of regulators, clocks and register-writes.
>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> ---
> MAINTAINERS | 11 +
> drivers/phy/qualcomm/Kconfig | 13 +
> drivers/phy/qualcomm/Makefile | 5 +
> drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 384 +++++++++++++++++++++
> drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c | 307 ++++++++++++++++
> drivers/phy/qualcomm/phy-qcom-mipi-csi2.h | 102 ++++++
> 6 files changed, 822 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 62ccdc72384d4..fe19722355d94 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -21542,6 +21542,17 @@ S: Maintained
> F: Documentation/devicetree/bindings/media/qcom,*-iris.yaml
> F: drivers/media/platform/qcom/iris/
>
> +QUALCOMM MIPI CSI2 PHY DRIVER
> +M: Bryan O'Donoghue <bod@kernel.org>
> +L: linux-phy@lists.infradead.org
> +L: linux-media@vger.kernel.org
> +L: linux-arm-msm@vger.kernel.org
> +S: Supported
> +F: Documentation/devicetree/bindings/phy/qcom,*-csi2-phy.yaml
> +F: drivers/phy/qualcomm/phy-qcom-mipi-csi2*.c
> +F: drivers/phy/qualcomm/phy-qcom-mipi-csi2*.h
> +F: include/dt-bindings/phy/phy-qcom-mipi-csi2*
> +
> QUALCOMM NAND CONTROLLER DRIVER
> M: Manivannan Sadhasivam <mani@kernel.org>
> L: linux-mtd@lists.infradead.org
> diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig
> index 60a0ead127fa9..ea33025a40fd0 100644
> --- a/drivers/phy/qualcomm/Kconfig
> +++ b/drivers/phy/qualcomm/Kconfig
> @@ -28,6 +28,19 @@ config PHY_QCOM_EDP
> Enable this driver to support the Qualcomm eDP PHY found in various
> Qualcomm chipsets.
>
> +config PHY_QCOM_MIPI_CSI2
> + tristate "Qualcomm MIPI CSI2 PHY driver"
> + depends on ARCH_QCOM || COMPILE_TEST
> + depends on OF
> + depends on COMMON_CLK
> + select GENERIC_PHY
> + select GENERIC_PHY_MIPI_DPHY
> + help
> + Enable this to support the MIPI CSI2 PHY driver found in various
> + Qualcomm chipsets. This PHY is used to connect MIPI CSI2
> + camera sensors to the CSI Decoder in the Qualcomm Camera Subsystem
> + CAMSS.
> +
> config PHY_QCOM_IPQ4019_USB
> tristate "Qualcomm IPQ4019 USB PHY driver"
> depends on OF && (ARCH_QCOM || COMPILE_TEST)
> diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile
> index b71a6a0bed3f1..382cb594b06b6 100644
> --- a/drivers/phy/qualcomm/Makefile
> +++ b/drivers/phy/qualcomm/Makefile
> @@ -6,6 +6,11 @@ obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
> obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
> obj-$(CONFIG_PHY_QCOM_M31_USB) += phy-qcom-m31.o
> obj-$(CONFIG_PHY_QCOM_M31_EUSB) += phy-qcom-m31-eusb2.o
> +
> +phy-qcom-mipi-csi2-objs += phy-qcom-mipi-csi2-core.o \
> + phy-qcom-mipi-csi2-3ph-dphy.o
> +obj-$(CONFIG_PHY_QCOM_MIPI_CSI2) += phy-qcom-mipi-csi2.o
> +
> obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o
>
> obj-$(CONFIG_PHY_QCOM_QMP_COMBO) += phy-qcom-qmp-combo.o phy-qcom-qmp-usbc.o
> diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c
> new file mode 100644
> index 0000000000000..f9f3451e9a5e1
> --- /dev/null
> +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c
> @@ -0,0 +1,384 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * camss-phy_qcom_mipi_csi2-3ph-1-0.c
And it doesn't match the driver anymore. Please drop it.
> + *
> + * Qualcomm MSM Camera Subsystem - CSIPHY Module 3phase v1.0
> + *
> + * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
> + * Copyright (C) 2016-2025 Linaro Ltd.
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/time64.h>
> +
> +#include "phy-qcom-mipi-csi2.h"
> +
> +#define CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(offset, n) ((offset) + 0x4 * (n))
> +#define CSIPHY_3PH_CMN_CSI_COMMON_CTRL0_PHY_SW_RESET BIT(0)
> +#define CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE BIT(7)
> +#define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B BIT(0)
> +#define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID BIT(1)
> +#define CSIPHY_3PH_CMN_CSI_COMMON_CTRL10_IRQ_CLEAR_CMD BIT(0)
> +#define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(offset, n) ((offset) + 0xb0 + 0x4 * (n))
> +
> +/*
> + * 3 phase CSI has 19 common status regs with only 0-10 being used
> + * and 11-18 being reserved.
> + */
> +#define CSI_COMMON_STATUS_NUM 11
> +/*
> + * There are a number of common control registers
> + * The offset to clear the CSIPHY IRQ status starts @ 22
> + * So to clear CSI_COMMON_STATUS0 this is CSI_COMMON_CONTROL22, STATUS1 is
> + * CONTROL23 and so on
> + */
> +#define CSI_CTRL_STATUS_INDEX 22
> +
> +/*
> + * There are 43 COMMON_CTRL registers with regs after # 33 being reserved
> + */
> +#define CSI_CTRL_MAX 33
> +
> +#define CSIPHY_DEFAULT_PARAMS 0
> +#define CSIPHY_LANE_ENABLE 1
Unused
> +#define CSIPHY_SETTLE_CNT_LOWER_BYTE 2
> +#define CSIPHY_SETTLE_CNT_HIGHER_BYTE 3
Unused
> +#define CSIPHY_DNP_PARAMS 4
> +#define CSIPHY_2PH_REGS 5
> +#define CSIPHY_3PH_REGS 6
Both are unused
> +#define CSIPHY_SKEW_CAL 7
> +
> +/* 4nm 2PH v 2.1.2 2p5Gbps 4 lane DPHY mode */
> +static const struct
> +mipi_csi2phy_lane_regs lane_regs_x1e80100[] = {
> + /* Power up lanes 2ph mode */
> + {.reg_addr = 0x1014, .reg_data = 0xD5, .param_type = CSIPHY_DEFAULT_PARAMS},
As you are moving the driver, it might also make sense to split / rework
the huge table with the code sequence. The code is easier to adapt.
As you can see in the tables, there are repetitive code patterns, which
correspond to the lane programming. Once that is extracted, it would be
much, much easier to manipulate the data.
It's fine if you are just moving the data with the intention of
improving it later, but then please state so in the commit message.
Also, please use low-case hex, I think it was a recommended practice
nowadays.
> + {.reg_addr = 0x101C, .reg_data = 0x7A, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x1018, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS},
> +
> + {.reg_addr = 0x0094, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x00A0, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0090, .reg_data = 0x0f, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0098, .reg_data = 0x08, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0094, .reg_data = 0x07, .delay_us = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0030, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0000, .reg_data = 0x8E, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0038, .reg_data = 0xFE, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x002C, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0034, .reg_data = 0x0F, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x001C, .reg_data = 0x0A, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0014, .reg_data = 0x60, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x003C, .reg_data = 0xB8, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0004, .reg_data = 0x0C, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0020, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0008, .reg_data = 0x10, .param_type = CSIPHY_SETTLE_CNT_LOWER_BYTE},
> + {.reg_addr = 0x0010, .reg_data = 0x52, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0094, .reg_data = 0xD7, .param_type = CSIPHY_SKEW_CAL},
> + {.reg_addr = 0x005C, .reg_data = 0x00, .param_type = CSIPHY_SKEW_CAL},
> + {.reg_addr = 0x0060, .reg_data = 0xBD, .param_type = CSIPHY_SKEW_CAL},
> + {.reg_addr = 0x0064, .reg_data = 0x7F, .param_type = CSIPHY_SKEW_CAL},
> +
> + {.reg_addr = 0x0E94, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0EA0, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0E90, .reg_data = 0x0f, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0E98, .reg_data = 0x08, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0E94, .reg_data = 0x07, .delay_us = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0E30, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0E28, .reg_data = 0x04, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0E00, .reg_data = 0x80, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0E0C, .reg_data = 0xFF, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0E38, .reg_data = 0x1F, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0E2C, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0E34, .reg_data = 0x0F, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0E1C, .reg_data = 0x0A, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0E14, .reg_data = 0x60, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0E3C, .reg_data = 0xB8, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0E04, .reg_data = 0x0C, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0E20, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0E08, .reg_data = 0x10, .param_type = CSIPHY_SETTLE_CNT_LOWER_BYTE},
> + {.reg_addr = 0x0E10, .reg_data = 0x52, .param_type = CSIPHY_DEFAULT_PARAMS},
> +
> + {.reg_addr = 0x0494, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x04A0, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0490, .reg_data = 0x0f, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0498, .reg_data = 0x08, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0494, .reg_data = 0x07, .delay_us = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0430, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0400, .reg_data = 0x8E, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0438, .reg_data = 0xFE, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x042C, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0434, .reg_data = 0x0F, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x041C, .reg_data = 0x0A, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0414, .reg_data = 0x60, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x043C, .reg_data = 0xB8, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0404, .reg_data = 0x0C, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0420, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0408, .reg_data = 0x10, .param_type = CSIPHY_SETTLE_CNT_LOWER_BYTE},
> + {.reg_addr = 0x0410, .reg_data = 0x52, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0494, .reg_data = 0xD7, .param_type = CSIPHY_SKEW_CAL},
> + {.reg_addr = 0x045C, .reg_data = 0x00, .param_type = CSIPHY_SKEW_CAL},
> + {.reg_addr = 0x0460, .reg_data = 0xBD, .param_type = CSIPHY_SKEW_CAL},
> + {.reg_addr = 0x0464, .reg_data = 0x7F, .param_type = CSIPHY_SKEW_CAL},
> +
> + {.reg_addr = 0x0894, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x08A0, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0890, .reg_data = 0x0f, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0898, .reg_data = 0x08, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0894, .reg_data = 0x07, .delay_us = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0830, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0800, .reg_data = 0x8E, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0838, .reg_data = 0xFE, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x082C, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0834, .reg_data = 0x0F, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x081C, .reg_data = 0x0A, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0814, .reg_data = 0x60, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x083C, .reg_data = 0xB8, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0804, .reg_data = 0x0C, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0820, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0808, .reg_data = 0x10, .param_type = CSIPHY_SETTLE_CNT_LOWER_BYTE},
> + {.reg_addr = 0x0810, .reg_data = 0x52, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0894, .reg_data = 0xD7, .param_type = CSIPHY_SKEW_CAL},
> + {.reg_addr = 0x085C, .reg_data = 0x00, .param_type = CSIPHY_SKEW_CAL},
> + {.reg_addr = 0x0860, .reg_data = 0xBD, .param_type = CSIPHY_SKEW_CAL},
> + {.reg_addr = 0x0864, .reg_data = 0x7F, .param_type = CSIPHY_SKEW_CAL},
> +
> + {.reg_addr = 0x0C94, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0CA0, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0C90, .reg_data = 0x0f, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0C98, .reg_data = 0x08, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0C94, .reg_data = 0x07, .delay_us = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0C30, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0C00, .reg_data = 0x8E, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0C38, .reg_data = 0xFE, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0C2C, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0C34, .reg_data = 0x0F, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0C1C, .reg_data = 0x0A, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0C14, .reg_data = 0x60, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0C3C, .reg_data = 0xB8, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0C04, .reg_data = 0x0C, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0C20, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0C08, .reg_data = 0x10, .param_type = CSIPHY_SETTLE_CNT_LOWER_BYTE},
> + {.reg_addr = 0x0C10, .reg_data = 0x52, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0C94, .reg_data = 0xD7, .param_type = CSIPHY_SKEW_CAL},
> + {.reg_addr = 0x0C5C, .reg_data = 0x00, .param_type = CSIPHY_SKEW_CAL},
> + {.reg_addr = 0x0C60, .reg_data = 0xBD, .param_type = CSIPHY_SKEW_CAL},
> + {.reg_addr = 0x0C64, .reg_data = 0x7F, .param_type = CSIPHY_SKEW_CAL},
> +};
> +
> +static inline const struct mipi_csi2phy_device_regs *
> +csi2phy_dev_to_regs(struct mipi_csi2phy_device *csi2phy)
> +{
> + return &csi2phy->soc_cfg->reg_info;
> +}
> +
> +static void phy_qcom_mipi_csi2_hw_version_read(struct mipi_csi2phy_device *csi2phy)
> +{
> + const struct mipi_csi2phy_device_regs *regs = csi2phy_dev_to_regs(csi2phy);
> + u32 tmp;
> +
> + writel(CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID, csi2phy->base +
> + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->common_regs_offset, 6));
> +
> + tmp = readl_relaxed(csi2phy->base +
> + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, 12));
> + csi2phy->hw_version = tmp;
> +
> + tmp = readl_relaxed(csi2phy->base +
> + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, 13));
> + csi2phy->hw_version |= (tmp << 8) & 0xFF00;
> +
> + tmp = readl_relaxed(csi2phy->base +
> + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, 14));
> + csi2phy->hw_version |= (tmp << 16) & 0xFF0000;
> +
> + tmp = readl_relaxed(csi2phy->base +
> + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, 15));
> + csi2phy->hw_version |= (tmp << 24) & 0xFF000000;
> +
> + dev_dbg_once(csi2phy->dev, "CSIPHY 3PH HW Version = 0x%08x\n", csi2phy->hw_version);
> +}
> +
> +/*
> + * phy_qcom_mipi_csi2_reset - Perform software reset on CSIPHY module
> + * @phy_qcom_mipi_csi2: CSIPHY device
> + */
> +static void phy_qcom_mipi_csi2_reset(struct mipi_csi2phy_device *csi2phy)
> +{
> + const struct mipi_csi2phy_device_regs *regs = csi2phy_dev_to_regs(csi2phy);
> +
> + writel(CSIPHY_3PH_CMN_CSI_COMMON_CTRL0_PHY_SW_RESET,
> + csi2phy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->common_regs_offset, 0));
> + usleep_range(5000, 8000);
> + writel(0x0, csi2phy->base +
> + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->common_regs_offset, 0));
> +}
> +
> +/*
> + * phy_qcom_mipi_csi2_settle_cnt_calc - Calculate settle count value
> + *
> + * Helper function to calculate settle count value. This is
> + * based on the CSI2 T_hs_settle parameter which in turn
> + * is calculated based on the CSI2 transmitter link frequency.
> + *
> + * Return settle count value or 0 if the CSI2 link frequency
> + * is not available
> + */
> +static u8 phy_qcom_mipi_csi2_settle_cnt_calc(s64 link_freq, u32 timer_clk_rate)
> +{
> + u32 t_hs_prepare_max_ps;
> + u32 timer_period_ps;
> + u32 t_hs_settle_ps;
> + u8 settle_cnt;
> + u32 ui_ps;
> +
> + if (link_freq <= 0)
> + return 0;
> +
> + ui_ps = div_u64(PSEC_PER_SEC, link_freq);
> + ui_ps /= 2;
> + t_hs_prepare_max_ps = 85000 + 6 * ui_ps;
> + t_hs_settle_ps = t_hs_prepare_max_ps;
> +
> + timer_period_ps = div_u64(PSEC_PER_SEC, timer_clk_rate);
> + settle_cnt = t_hs_settle_ps / timer_period_ps - 6;
> +
> + return settle_cnt;
> +}
> +
> +static void
> +phy_qcom_mipi_csi2_gen2_config_lanes(struct mipi_csi2phy_device *csi2phy,
> + u8 settle_cnt)
> +{
> + const struct mipi_csi2phy_device_regs *regs = csi2phy_dev_to_regs(csi2phy);
> + const struct mipi_csi2phy_lane_regs *r = regs->init_seq;
> + int i, array_size = regs->lane_array_size;
> + u32 val;
> +
> + for (i = 0; i < array_size; i++, r++) {
> + switch (r->param_type) {
> + case CSIPHY_SETTLE_CNT_LOWER_BYTE:
> + val = settle_cnt & 0xff;
> + break;
> + case CSIPHY_SKEW_CAL:
> + /* TODO: support application of skew from dt flag */
> + continue;
> + default:
> + val = r->reg_data;
> + break;
> + }
> + writel(val, csi2phy->base + r->reg_addr);
> + if (r->delay_us)
> + udelay(r->delay_us);
> + }
> +}
> +
> +static int phy_qcom_mipi_csi2_lanes_enable(struct mipi_csi2phy_device *csi2phy,
> + struct mipi_csi2phy_stream_cfg *cfg)
> +{
> + const struct mipi_csi2phy_device_regs *regs = csi2phy_dev_to_regs(csi2phy);
> + struct mipi_csi2phy_lanes_cfg *lane_cfg = &cfg->lane_cfg;
> + u8 settle_cnt;
> + u8 val;
> + int i;
> +
> + settle_cnt = phy_qcom_mipi_csi2_settle_cnt_calc(cfg->link_freq, csi2phy->timer_clk_rate);
> +
> + val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
> + for (i = 0; i < cfg->num_data_lanes; i++)
> + val |= BIT(lane_cfg->data[i].pos * 2);
> +
> + writel(val, csi2phy->base +
> + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->common_regs_offset, 5));
> +
> + val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B;
> + writel(val, csi2phy->base +
> + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->common_regs_offset, 6));
> +
> + val = 0x02;
> + writel(val, csi2phy->base +
> + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->common_regs_offset, 7));
> +
> + val = 0x00;
> + writel(val, csi2phy->base +
> + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->common_regs_offset, 0));
> +
> + phy_qcom_mipi_csi2_gen2_config_lanes(csi2phy, settle_cnt);
> +
> + /* IRQ_MASK registers - disable all interrupts */
> + for (i = CSI_COMMON_STATUS_NUM; i < CSI_CTRL_STATUS_INDEX; i++) {
> + writel(0, csi2phy->base +
> + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->common_regs_offset, i));
> + }
> +
> + return 0;
> +}
> +
> +static void
> +phy_qcom_mipi_csi2_lanes_disable(struct mipi_csi2phy_device *csi2phy,
> + struct mipi_csi2phy_stream_cfg *cfg)
> +{
> + const struct mipi_csi2phy_device_regs *regs = csi2phy_dev_to_regs(csi2phy);
> +
> + writel(0, csi2phy->base +
> + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->common_regs_offset, 5));
> +
> + writel(0, csi2phy->base +
> + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->common_regs_offset, 6));
> +}
> +
> +static const struct mipi_csi2phy_hw_ops phy_qcom_mipi_csi2_ops_3ph_1_0 = {
> + .hw_version_read = phy_qcom_mipi_csi2_hw_version_read,
> + .reset = phy_qcom_mipi_csi2_reset,
> + .lanes_enable = phy_qcom_mipi_csi2_lanes_enable,
> + .lanes_disable = phy_qcom_mipi_csi2_lanes_disable,
> +};
> +
> +static const struct mipi_csi2phy_clk_freq zero = { 0 };
> +
> +static const struct mipi_csi2phy_clk_freq dphy_4nm_x1e_csiphy = {
> + .freq = {
> + 300000000, 400000000, 480000000
> + },
> + .num_freq = 3,
> +};
> +
> +static const struct mipi_csi2phy_clk_freq dphy_4nm_x1e_csiphy_timer = {
> + .freq = {
> + 266666667, 400000000
> + },
> + .num_freq = 2,
As you are migrating to a modern codebase, these values should be set
via the OPP tables instead.
> +};
> +
> +static const char * const x1e_clks[] = {
> + "camnoc_axi",
> + "cpas_ahb",
> + "csiphy",
> + "csiphy_timer"
> +};
> +
> +const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_4nm_x1e = {
> + .ops = &phy_qcom_mipi_csi2_ops_3ph_1_0,
> + .reg_info = {
> + .init_seq = lane_regs_x1e80100,
> + .lane_array_size = ARRAY_SIZE(lane_regs_x1e80100),
> + .common_regs_offset = 0x1000,
> + .generation = GEN2,
Does this generation match anything in the actual hardware?
> + },
> + .supply_names = (const char *[]){
> + "vdda-0p8",
> + "vdda-1p2"
> + },
> + .num_supplies = 2,
> + .clk_names = (const char **)x1e_clks,
> + .num_clk = ARRAY_SIZE(x1e_clks),
> + .opp_clk = x1e_clks[2],
> + .timer_clk = x1e_clks[3],
> + .clk_freq = {
> + zero,
> + zero,
> + dphy_4nm_x1e_csiphy,
> + dphy_4nm_x1e_csiphy_timer,
> + },
> +};
> diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c
> new file mode 100644
> index 0000000000000..454144f81b719
> --- /dev/null
> +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c
> @@ -0,0 +1,307 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2025, Linaro Ltd.
> + */
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/pm_opp.h>
> +#include <linux/phy/phy.h>
> +#include <linux/phy/phy-mipi-dphy.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/regmap.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/reset.h>
> +#include <linux/slab.h>
> +
> +#include "phy-qcom-mipi-csi2.h"
> +
> +#define CAMSS_CLOCK_MARGIN_NUMERATOR 105
> +#define CAMSS_CLOCK_MARGIN_DENOMINATOR 100
> +
> +static inline void phy_qcom_mipi_csi2_add_clock_margin(u64 *rate)
> +{
> + *rate *= CAMSS_CLOCK_MARGIN_NUMERATOR;
> + *rate = div_u64(*rate, CAMSS_CLOCK_MARGIN_DENOMINATOR);
> +}
> +
> +static int
> +phy_qcom_mipi_csi2_set_clock_rates(struct mipi_csi2phy_device *csi2phy,
> + s64 link_freq)
> +{
> + const struct mipi_csi2phy_soc_cfg *soc_cfg = csi2phy->soc_cfg;
> + unsigned long rates[MAX_CSI2PHY_CLKS] = {0};
> + struct device *dev = csi2phy->dev;
> + unsigned long vote_freq = 0;
> + int i, j;
> + int ret;
> +
> + for (i = 0; i < soc_cfg->num_clk; i++) {
> + const struct mipi_csi2phy_clk_freq *clk_freq = &soc_cfg->clk_freq[i];
> + const char *clk_name = soc_cfg->clk_names[i];
> + struct clk *clk = csi2phy->clks[i].clk;
> + u64 min_rate = link_freq / 4;
> + long round_rate;
> +
> + phy_qcom_mipi_csi2_add_clock_margin(&min_rate);
> +
> + /* This clock should be enabled only not set */
> + if (!clk_freq->num_freq)
> + continue;
> +
> + for (j = 0; j < clk_freq->num_freq; j++)
> + if (min_rate < clk_freq->freq[j])
> + break;
> +
> + if (j == clk_freq->num_freq) {
> + dev_err(dev,
> + "Pixel clock %llu is too high for %s\n",
> + min_rate, clk_name);
> + return -EINVAL;
> + }
> +
> + /* if sensor pixel clock is not available
> + * set highest possible CSIPHY clock rate
> + */
> + if (min_rate == 0)
> + j = clk_freq->num_freq - 1;
> +
> + round_rate = clk_round_rate(clk, clk_freq->freq[j]);
> + if (round_rate < 0) {
> + dev_err(dev, "clk round rate failed: %ld\n",
> + round_rate);
> + return -EINVAL;
> + }
All of this code looks like a poor man's implementation of the OPP
handling, finding the highest possible clock rate, etc.
> +
> + rates[i] = round_rate;
> +
> + if (!strcmp(clk_name, soc_cfg->timer_clk))
> + csi2phy->timer_clk_rate = round_rate;
> +
> + if (!strcmp(clk_name, soc_cfg->opp_clk))
> + vote_freq = round_rate;
> + }
> +
> + if (!vote_freq) {
> + dev_err(dev, "Unable to find operating point frequency\n");
> + return -ENODEV;
> + };
> +
> + dev_dbg(dev, "OPP freq: %lu Hz\n", vote_freq);
> +
> + ret = dev_pm_opp_set_rate(dev, vote_freq);
> + if (ret < 0) {
> + dev_err(dev, "Failed to set OPP rate: %d\n", ret);
> + return ret;
> + }
> +
> + for (i = 0; i < soc_cfg->num_clk; i++) {
> + if (rates[i] == 0)
> + continue;
> +
> + dev_dbg(dev, "Setting clk %s to %lu Hz\n",
> + soc_cfg->clk_names[i], rates[i]);
> +
> + ret = clk_set_rate(csi2phy->clks[i].clk, rates[i]);
> + if (ret < 0) {
> + dev_err(dev, "clk_set_rate failed for %s: %d\n",
> + soc_cfg->clk_names[i], ret);
> + return ret;
> + }
> + }
> +
> + return 0;
> +}
> +
--
With best wishes
Dmitry
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