* Re: [PATCH v2 1/4] phy: phy-can-transceiver: Convert to use device property API
From: Josua Mayer @ 2026-04-27 11:26 UTC (permalink / raw)
To: Andy Shevchenko, linux-can@vger.kernel.org,
linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org
Cc: Marc Kleine-Budde, Vincent Mailhol, Vinod Koul, Neil Armstrong,
Ulf Hansson
In-Reply-To: <20260317203001.2108568-2-andriy.shevchenko@linux.intel.com>
Hi Andy,
Am 17.03.26 um 21:27 schrieb Andy Shevchenko:
> It seems the driver is half-moved to use device property APIs.
> Finish that by converting everything to use that.
As per v7.1-rc1 it seems you really just drop the last of_* function call,
while you're no adding any new device property call.
>
> While at it, drop unneeded argument to devm_phy_create() which
> extracts device node from the given device by default.
This was counter-intuitive to me at first,
but I confirmed it by reading in phy-core.c.
>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> ---
> drivers/phy/phy-can-transceiver.c | 8 +++-----
> 1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/phy/phy-can-transceiver.c b/drivers/phy/phy-can-transceiver.c
> index 2b52e47f247a..80eece74f77d 100644
> --- a/drivers/phy/phy-can-transceiver.c
> +++ b/drivers/phy/phy-can-transceiver.c
> @@ -5,9 +5,9 @@
> * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com
> *
> */
> -#include <linux/of.h>
> #include <linux/phy/phy.h>
> #include <linux/platform_device.h>
> +#include <linux/property.h>
> #include <linux/module.h>
> #include <linux/gpio.h>
> #include <linux/gpio/consumer.h>
> @@ -152,7 +152,6 @@ static int can_transceiver_phy_probe(struct platform_device *pdev)
> struct can_transceiver_phy *can_transceiver_phy;
> struct can_transceiver_priv *priv;
> const struct can_transceiver_data *drvdata;
> - const struct of_device_id *match;
> struct phy *phy;
> struct gpio_desc *silent_gpio;
> struct gpio_desc *standby_gpio;
> @@ -161,8 +160,7 @@ static int can_transceiver_phy_probe(struct platform_device *pdev)
> u32 max_bitrate = 0;
> int err, i, num_ch = 1;
>
> - match = of_match_node(can_transceiver_phy_ids, pdev->dev.of_node);
> - drvdata = match->data;
> + drvdata = device_get_match_data(dev);
> if (drvdata->flags & CAN_TRANSCEIVER_DUAL_CH)
> num_ch = 2;
>
> @@ -187,7 +185,7 @@ static int can_transceiver_phy_probe(struct platform_device *pdev)
> can_transceiver_phy = &priv->can_transceiver_phy[i];
> can_transceiver_phy->priv = priv;
>
> - phy = devm_phy_create(dev, dev->of_node, &can_transceiver_phy_ops);
> + phy = devm_phy_create(dev, NULL, &can_transceiver_phy_ops);
> if (IS_ERR(phy)) {
> dev_err(dev, "failed to create can transceiver phy\n");
> return PTR_ERR(phy);
Commit message seems sub-optimal, but code change looks good.
Reviewed-by: Josua Mayer <josua@solid-run.com>
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* Re: [PATCH v2 0/4] phy: phy-can-transceiver: Ad-hoc cleanups and refactoring
From: Josua Mayer @ 2026-04-27 11:09 UTC (permalink / raw)
To: Andy Shevchenko, linux-can@vger.kernel.org,
linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org
Cc: Marc Kleine-Budde, Vincent Mailhol, Vinod Koul, Neil Armstrong,
Ulf Hansson
In-Reply-To: <ad6KwGIhpJn_2eVz@ashevche-desk.local>
Hi Andy,
Am 14.04.26 um 20:43 schrieb Andy Shevchenko:
> On Tue, Mar 17, 2026 at 09:27:26PM +0100, Andy Shevchenko wrote:
>> The driver does two things that need to be addressed:
>> - includes subject to remove gpio.h
>> - checks for error code from device property APIs when it can be done in
>> a robust way
>>
>> This series addresses the above and adds a couple of additional refactoring.
> Any comments on this? Doesn't look like it being applied so far...
For unknown reason your patch-set did not arrive in my inbox.
Perhaps it went missing for others, too?
sincerely
Josua Mayer
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* Re: [PATCH v2 4/4] phy: phy-can-transceiver: Drop unused include
From: Josua Mayer @ 2026-04-27 11:05 UTC (permalink / raw)
To: Andy Shevchenko, linux-can@vger.kernel.org,
linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org
Cc: Marc Kleine-Budde, Vincent Mailhol, Vinod Koul, Neil Armstrong,
Ulf Hansson
In-Reply-To: <20260317203001.2108568-5-andriy.shevchenko@linux.intel.com>
Am 17.03.26 um 21:27 schrieb Andy Shevchenko:
> This file does not use the symbols from the legacy
> <linux/gpio.h> header, so let's drop it.
>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> ---
> drivers/phy/phy-can-transceiver.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/phy/phy-can-transceiver.c b/drivers/phy/phy-can-transceiver.c
> index 21b0406d1a09..8e250039c183 100644
> --- a/drivers/phy/phy-can-transceiver.c
> +++ b/drivers/phy/phy-can-transceiver.c
> @@ -5,12 +5,11 @@
> * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com
> *
> */
> +#include <linux/gpio/consumer.h>
> #include <linux/phy/phy.h>
> #include <linux/platform_device.h>
> #include <linux/property.h>
> #include <linux/module.h>
> -#include <linux/gpio.h>
> -#include <linux/gpio/consumer.h>
> #include <linux/mux/consumer.h>
>
> struct can_transceiver_data {
Reviewed-by: Josua Mayer <josua@solid-run.com>
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* Re: [PATCH 4/4] phy: qualcomm: qmp-combo: Add support for Hawi SoC
From: Konrad Dybcio @ 2026-04-27 10:59 UTC (permalink / raw)
To: Ronak Raheja, vkoul, krzk+dt, conor+dt, robh, neil.armstrong,
gregkh
Cc: dmitry.baryshkov, abel.vesa, wesley.cheng, linux-arm-msm,
linux-phy, devicetree, linux-usb, linux-kernel
In-Reply-To: <20260425070002.348733-5-ronak.raheja@oss.qualcomm.com>
On 4/25/26 9:00 AM, Ronak Raheja wrote:
> Add support for the USB3-DP combo PHY found on Hawi platform.
>
> The QMP PHY for Hawi uses QSERDES V10 register layouts. Add the required
> PHY sequences from the hardware programming guide and new V10 register
> header files. Also add a new v10 offset structure to incorporate the new
> COM AON register module.
>
> Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
> ---
[...]
> + QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
> +
> + QMP_PHY_INIT_CFG(QSERDES_V10_RX_SIGDET_ENABLES, 0x0c),
nit: stray \n above
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
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* [PATCH v5 5/5] phy: qcom: edp: Add PHY-specific LDO config for eDP low vdiff
From: Yongxing Mou @ 2026-04-27 6:35 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Stephen Boyd, Bjorn Andersson
Cc: linux-arm-msm, linux-phy, linux-kernel, Yongxing Mou, stable,
Dmitry Baryshkov, Konrad Dybcio
In-Reply-To: <20260427-edp_phy-v5-0-3bb876824475@oss.qualcomm.com>
For eDP low vdiff, the LDO setting depends on the PHY version rather
than being a simple 0x0 or 0x1 value. Introduce a PHY callback to program
the correct LDO setting according to the HPG.
Since SC7280/SC8180X uses different LDO settings from SA8775P/SC8280XP,
introduce qcom_edp_phy_ops_v3 to keep the LDO setting correct.
Cc: stable@vger.kernel.org
Fixes: f199223cb490 ("phy: qcom: Introduce new eDP PHY driver")
Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Tested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> # SC8280XP X13s
---
drivers/phy/qualcomm/phy-qcom-edp.c | 88 ++++++++++++++++++++++++++++++++-----
1 file changed, 77 insertions(+), 11 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c
index 3a848f18a8d6..a3c893f72908 100644
--- a/drivers/phy/qualcomm/phy-qcom-edp.c
+++ b/drivers/phy/qualcomm/phy-qcom-edp.c
@@ -81,6 +81,7 @@ struct phy_ver_ops {
int (*com_clk_fwd_cfg)(const struct qcom_edp *edp);
int (*com_configure_pll)(const struct qcom_edp *edp);
int (*com_configure_ssc)(const struct qcom_edp *edp);
+ int (*com_ldo_config)(const struct qcom_edp *edp);
};
struct qcom_edp_phy_cfg {
@@ -352,7 +353,7 @@ static int qcom_edp_set_voltages(struct qcom_edp *edp, const struct phy_configur
const struct qcom_edp_swing_pre_emph_cfg *cfg;
unsigned int v_level = 0;
unsigned int p_level = 0;
- u8 ldo_config;
+ int ret;
u8 swing;
u8 emph;
int i;
@@ -378,13 +379,13 @@ static int qcom_edp_set_voltages(struct qcom_edp *edp, const struct phy_configur
if (swing == 0xff || emph == 0xff)
return -EINVAL;
- ldo_config = edp->is_edp ? 0x0 : 0x1;
+ ret = edp->cfg->ver_ops->com_ldo_config(edp);
+ if (ret)
+ return ret;
- writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG);
writel(swing, edp->tx0 + TXn_TX_DRV_LVL);
writel(emph, edp->tx0 + TXn_TX_EMP_POST1_LVL);
- writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG);
writel(swing, edp->tx1 + TXn_TX_DRV_LVL);
writel(emph, edp->tx1 + TXn_TX_EMP_POST1_LVL);
@@ -608,6 +609,52 @@ static int qcom_edp_com_configure_pll_v4(const struct qcom_edp *edp)
return 0;
}
+static int qcom_edp_ldo_config_v3(const struct qcom_edp *edp)
+{
+ const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts;
+ u32 ldo_config;
+
+ if (!edp->is_edp)
+ ldo_config = 0x0;
+ else if (dp_opts->link_rate <= 2700)
+ ldo_config = 0x81;
+ else
+ ldo_config = 0x41;
+
+ writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG);
+ writel(dp_opts->lanes > 2 ? ldo_config : 0x00, edp->tx1 + TXn_LDO_CONFIG);
+
+ return 0;
+}
+
+static int qcom_edp_ldo_config_v4(const struct qcom_edp *edp)
+{
+ const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts;
+ u32 ldo_config;
+
+ if (!edp->is_edp)
+ ldo_config = 0x0;
+ else if (dp_opts->link_rate <= 2700)
+ ldo_config = 0xc1;
+ else
+ ldo_config = 0x81;
+
+ writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG);
+ writel(dp_opts->lanes > 2 ? ldo_config : 0x00, edp->tx1 + TXn_LDO_CONFIG);
+
+ return 0;
+}
+
+static const struct phy_ver_ops qcom_edp_phy_ops_v3 = {
+ .com_power_on = qcom_edp_phy_power_on_v4,
+ .com_resetsm_cntrl = qcom_edp_phy_com_resetsm_cntrl_v4,
+ .com_bias_en_clkbuflr = qcom_edp_com_bias_en_clkbuflr_v4,
+ .com_clk_fwd_cfg = qcom_edp_com_clk_fwd_cfg_v4,
+ .com_configure_pll = qcom_edp_com_configure_pll_v4,
+ .com_configure_ssc = qcom_edp_com_configure_ssc_v4,
+ .com_ldo_config = qcom_edp_ldo_config_v3,
+};
+
static const struct phy_ver_ops qcom_edp_phy_ops_v4 = {
.com_power_on = qcom_edp_phy_power_on_v4,
.com_resetsm_cntrl = qcom_edp_phy_com_resetsm_cntrl_v4,
@@ -615,6 +662,7 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v4 = {
.com_clk_fwd_cfg = qcom_edp_com_clk_fwd_cfg_v4,
.com_configure_pll = qcom_edp_com_configure_pll_v4,
.com_configure_ssc = qcom_edp_com_configure_ssc_v4,
+ .com_ldo_config = qcom_edp_ldo_config_v4,
};
static const struct qcom_edp_phy_cfg sa8775p_dp_phy_cfg = {
@@ -631,7 +679,7 @@ static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg = {
.vco_div_cfg = edp_phy_vco_div_cfg_v4,
.dp_swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg,
.edp_swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg_v3,
- .ver_ops = &qcom_edp_phy_ops_v4,
+ .ver_ops = &qcom_edp_phy_ops_v3,
};
static const struct qcom_edp_phy_cfg sc8180x_dp_phy_cfg = {
@@ -639,7 +687,7 @@ static const struct qcom_edp_phy_cfg sc8180x_dp_phy_cfg = {
.vco_div_cfg = edp_phy_vco_div_cfg_v4,
.dp_swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg_v2,
.edp_swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg_v2,
- .ver_ops = &qcom_edp_phy_ops_v4,
+ .ver_ops = &qcom_edp_phy_ops_v3,
};
static const struct qcom_edp_phy_cfg sc8280xp_dp_phy_cfg = {
@@ -824,6 +872,24 @@ static int qcom_edp_com_configure_pll_v6(const struct qcom_edp *edp)
return 0;
}
+static int qcom_edp_ldo_config_v6(const struct qcom_edp *edp)
+{
+ const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts;
+ u32 ldo_config;
+
+ if (!edp->is_edp)
+ ldo_config = 0x0;
+ else if (dp_opts->link_rate <= 2700)
+ ldo_config = 0x51;
+ else
+ ldo_config = 0x91;
+
+ writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG);
+ writel(dp_opts->lanes > 2 ? ldo_config : 0x00, edp->tx1 + TXn_LDO_CONFIG);
+
+ return 0;
+}
+
static const struct phy_ver_ops qcom_edp_phy_ops_v6 = {
.com_power_on = qcom_edp_phy_power_on_v6,
.com_resetsm_cntrl = qcom_edp_phy_com_resetsm_cntrl_v6,
@@ -831,6 +897,7 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v6 = {
.com_clk_fwd_cfg = qcom_edp_com_clk_fwd_cfg_v4,
.com_configure_pll = qcom_edp_com_configure_pll_v6,
.com_configure_ssc = qcom_edp_com_configure_ssc_v6,
+ .com_ldo_config = qcom_edp_ldo_config_v6,
};
static struct qcom_edp_phy_cfg x1e80100_phy_cfg = {
@@ -1011,6 +1078,7 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v8 = {
.com_clk_fwd_cfg = qcom_edp_com_clk_fwd_cfg_v8,
.com_configure_pll = qcom_edp_com_configure_pll_v8,
.com_configure_ssc = qcom_edp_com_configure_ssc_v8,
+ .com_ldo_config = qcom_edp_ldo_config_v6,
};
static struct qcom_edp_phy_cfg glymur_phy_cfg = {
@@ -1026,7 +1094,6 @@ static int qcom_edp_phy_power_on(struct phy *phy)
const struct qcom_edp *edp = phy_get_drvdata(phy);
u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
unsigned long pixel_freq;
- u8 ldo_config = 0x0;
int ret;
u32 val;
u8 cfg1;
@@ -1035,11 +1102,10 @@ static int qcom_edp_phy_power_on(struct phy *phy)
if (ret)
return ret;
- if (edp->cfg->edp_swing_pre_emph_cfg && !edp->is_edp)
- ldo_config = 0x1;
+ ret = edp->cfg->ver_ops->com_ldo_config(edp);
+ if (ret)
+ return ret;
- writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG);
- writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG);
writel(0x00, edp->tx0 + TXn_LANE_MODE_1);
writel(0x00, edp->tx1 + TXn_LANE_MODE_1);
--
2.43.0
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* [PATCH v5 4/5] phy: qcom: edp: Fix AUX_CFG8 programming for DP mode
From: Yongxing Mou @ 2026-04-27 6:35 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Stephen Boyd, Bjorn Andersson
Cc: linux-arm-msm, linux-phy, linux-kernel, Yongxing Mou, stable,
Konrad Dybcio, Dmitry Baryshkov
In-Reply-To: <20260427-edp_phy-v5-0-3bb876824475@oss.qualcomm.com>
AUX_CFG8 depends on whether the PHY is operating in eDP or DP mode, not
the selected swing/pre-emphasis table. All supported platforms already
have the proper tables, so remove the unnecessary check.
Cc: stable@vger.kernel.org
Fixes: 6078b8ce070c ("phy: qcom: edp: Add set_mode op for configuring eDP/DP submode")
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
---
drivers/phy/qualcomm/phy-qcom-edp.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c
index 3e613b374032..3a848f18a8d6 100644
--- a/drivers/phy/qualcomm/phy-qcom-edp.c
+++ b/drivers/phy/qualcomm/phy-qcom-edp.c
@@ -325,12 +325,7 @@ static int qcom_edp_phy_init(struct phy *phy)
DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
edp->edp + DP_PHY_PD_CTL);
- /*
- * TODO: Re-work the conditions around setting the cfg8 value
- * when more information becomes available about why this is
- * even needed.
- */
- if (edp->cfg->dp_swing_pre_emph_cfg && !edp->is_edp)
+ if (!edp->is_edp)
aux_cfg[8] = 0xb7;
writel(0xfc, edp->edp + DP_PHY_MODE);
--
2.43.0
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* [PATCH v5 3/5] phy: qcom: edp: Add SC7280/SC8180X swing/pre-emphasis tables
From: Yongxing Mou @ 2026-04-27 6:35 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Stephen Boyd, Bjorn Andersson
Cc: linux-arm-msm, linux-phy, linux-kernel, Yongxing Mou
In-Reply-To: <20260427-edp_phy-v5-0-3bb876824475@oss.qualcomm.com>
SC7280 and SC8180X previously shared the same cfg because they did not use
swing/pre-emphasis tables. Add the corresponding tables for these
platforms. Since they have different PHY sub-versions, their eDP/DP mode
tables also differ, so move SC8180X to its own cfg instead of reusing the
SC7280 one.
Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
---
drivers/phy/qualcomm/phy-qcom-edp.c | 84 +++++++++++++++++++++++++++++++++++--
1 file changed, 80 insertions(+), 4 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c
index 3266026cfe37..3e613b374032 100644
--- a/drivers/phy/qualcomm/phy-qcom-edp.c
+++ b/drivers/phy/qualcomm/phy-qcom-edp.c
@@ -165,6 +165,33 @@ static const struct qcom_edp_swing_pre_emph_cfg dp_phy_swing_pre_emph_cfg_v8 = {
.pre_emphasis_hbr3_hbr2 = &dp_pre_emp_hbr2_hbr3,
};
+static const u8 dp_swing_hbr2_hbr3_v2[4][4] = {
+ { 0x27, 0x2f, 0x36, 0xff },
+ { 0x31, 0x3e, 0x3f, 0xff },
+ { 0x3a, 0x3f, 0xff, 0xff },
+ { 0xff, 0xff, 0xff, 0xff }
+};
+
+static const u8 dp_pre_emp_hbr2_hbr3_v2[4][4] = {
+ { 0x20, 0x2e, 0x35, 0xff },
+ { 0x20, 0x2e, 0x35, 0xff },
+ { 0x20, 0x2e, 0xff, 0xff },
+ { 0xff, 0xff, 0xff, 0xff }
+};
+
+static const struct qcom_edp_swing_pre_emph_cfg dp_phy_swing_pre_emph_cfg_v2 = {
+ /*
+ * NOTE: The HPG does not specify a separate swing_hbr_rbr table.
+ * Reuse the HBR2/HBR3 table for now.
+ *
+ * TODO: Update this once the HPG explicitly defines RBR/HBR swing values.
+ */
+ .swing_hbr_rbr = &dp_swing_hbr2_hbr3_v2,
+ .swing_hbr3_hbr2 = &dp_swing_hbr2_hbr3_v2,
+ .pre_emphasis_hbr_rbr = &dp_pre_emp_hbr2_hbr3_v2,
+ .pre_emphasis_hbr3_hbr2 = &dp_pre_emp_hbr2_hbr3_v2,
+};
+
static const u8 edp_swing_hbr_rbr[4][4] = {
{ 0x07, 0x0f, 0x16, 0x1f },
{ 0x0d, 0x16, 0x1e, 0xff },
@@ -208,6 +235,48 @@ static const u8 edp_phy_vco_div_cfg_v4[4] = {
0x01, 0x01, 0x02, 0x00,
};
+static const u8 edp_pre_emp_hbr_rbr_v2[4][4] = {
+ { 0x05, 0x12, 0x17, 0x1d },
+ { 0x05, 0x11, 0x18, 0xff },
+ { 0x06, 0x11, 0xff, 0xff },
+ { 0x00, 0xff, 0xff, 0xff }
+};
+
+static const u8 edp_pre_emp_hbr2_hbr3_v2[4][4] = {
+ { 0x0c, 0x15, 0x19, 0x1e },
+ { 0x08, 0x15, 0x19, 0xff },
+ { 0x0e, 0x14, 0xff, 0xff },
+ { 0x0d, 0xff, 0xff, 0xff }
+};
+
+static const struct qcom_edp_swing_pre_emph_cfg edp_phy_swing_pre_emph_cfg_v2 = {
+ .swing_hbr_rbr = &edp_swing_hbr_rbr,
+ .swing_hbr3_hbr2 = &edp_swing_hbr2_hbr3,
+ .pre_emphasis_hbr_rbr = &edp_pre_emp_hbr_rbr_v2,
+ .pre_emphasis_hbr3_hbr2 = &edp_pre_emp_hbr2_hbr3_v2,
+};
+
+static const u8 edp_swing_hbr2_hbr3_v3[4][4] = {
+ { 0x06, 0x11, 0x16, 0x1b },
+ { 0x0b, 0x19, 0x1f, 0xff },
+ { 0x18, 0x1f, 0xff, 0xff },
+ { 0x1f, 0xff, 0xff, 0xff }
+};
+
+static const u8 edp_pre_emp_hbr2_hbr3_v3[4][4] = {
+ { 0x0c, 0x15, 0x19, 0x1e },
+ { 0x09, 0x14, 0x19, 0xff },
+ { 0x0f, 0x14, 0xff, 0xff },
+ { 0x0d, 0xff, 0xff, 0xff }
+};
+
+static const struct qcom_edp_swing_pre_emph_cfg edp_phy_swing_pre_emph_cfg_v3 = {
+ .swing_hbr_rbr = &edp_swing_hbr_rbr,
+ .swing_hbr3_hbr2 = &edp_swing_hbr2_hbr3_v3,
+ .pre_emphasis_hbr_rbr = &edp_pre_emp_hbr_rbr,
+ .pre_emphasis_hbr3_hbr2 = &edp_pre_emp_hbr2_hbr3_v3,
+};
+
static const u8 edp_phy_aux_cfg_v5[DP_AUX_CFG_SIZE] = {
0x00, 0x13, 0xa4, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03, 0x02, 0x02, 0x00,
};
@@ -298,9 +367,6 @@ static int qcom_edp_set_voltages(struct qcom_edp *edp, const struct phy_configur
else
cfg = edp->cfg->dp_swing_pre_emph_cfg;
- if (!cfg)
- return 0;
-
for (i = 0; i < dp_opts->lanes; i++) {
v_level = max(v_level, dp_opts->voltage[i]);
p_level = max(p_level, dp_opts->pre[i]);
@@ -568,6 +634,16 @@ static const struct qcom_edp_phy_cfg sa8775p_dp_phy_cfg = {
static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg = {
.aux_cfg = edp_phy_aux_cfg_v4,
.vco_div_cfg = edp_phy_vco_div_cfg_v4,
+ .dp_swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg,
+ .edp_swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg_v3,
+ .ver_ops = &qcom_edp_phy_ops_v4,
+};
+
+static const struct qcom_edp_phy_cfg sc8180x_dp_phy_cfg = {
+ .aux_cfg = edp_phy_aux_cfg_v4,
+ .vco_div_cfg = edp_phy_vco_div_cfg_v4,
+ .dp_swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg_v2,
+ .edp_swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg_v2,
.ver_ops = &qcom_edp_phy_ops_v4,
};
@@ -1348,7 +1424,7 @@ static const struct of_device_id qcom_edp_phy_match_table[] = {
{ .compatible = "qcom,glymur-dp-phy", .data = &glymur_phy_cfg, },
{ .compatible = "qcom,sa8775p-edp-phy", .data = &sa8775p_dp_phy_cfg, },
{ .compatible = "qcom,sc7280-edp-phy", .data = &sc7280_dp_phy_cfg, },
- { .compatible = "qcom,sc8180x-edp-phy", .data = &sc7280_dp_phy_cfg, },
+ { .compatible = "qcom,sc8180x-edp-phy", .data = &sc8180x_dp_phy_cfg, },
{ .compatible = "qcom,sc8280xp-dp-phy", .data = &sc8280xp_dp_phy_cfg, },
{ .compatible = "qcom,sc8280xp-edp-phy", .data = &sc8280xp_edp_phy_cfg, },
{ .compatible = "qcom,x1e80100-dp-phy", .data = &x1e80100_phy_cfg, },
--
2.43.0
--
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^ permalink raw reply related
* [PATCH v5 2/5] phy: qcom: edp: Add eDP/DP mode switch support
From: Yongxing Mou @ 2026-04-27 6:35 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Stephen Boyd, Bjorn Andersson
Cc: linux-arm-msm, linux-phy, linux-kernel, Yongxing Mou, stable,
Konrad Dybcio
In-Reply-To: <20260427-edp_phy-v5-0-3bb876824475@oss.qualcomm.com>
The eDP PHY supports both eDP/DP modes, each requiring a different
swing/pre-emphasis table. However, the driver currently uses a fixed
static table for eDP programming rather than selecting the appropriate
table based on the current mode. Add separate tables for eDP and DP
modes, and select the appropriate table dynamically based on the
current mode.
Glymur's DP mode table differs from the other platforms, add a
dedicated table for it.
This also fixes the table mismatch for X1E80100 (eDP) and SA8775P (DP).
Cc: stable@vger.kernel.org
Fixes: 3f12bf16213c ("phy: qcom: edp: Add support for eDP PHY on SA8775P")
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
---
drivers/phy/qualcomm/phy-qcom-edp.c | 46 +++++++++++++++++++++++++++----------
1 file changed, 34 insertions(+), 12 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c
index 2af3fd63832f..3266026cfe37 100644
--- a/drivers/phy/qualcomm/phy-qcom-edp.c
+++ b/drivers/phy/qualcomm/phy-qcom-edp.c
@@ -87,7 +87,8 @@ struct qcom_edp_phy_cfg {
bool is_edp;
const u8 *aux_cfg;
const u8 *vco_div_cfg;
- const struct qcom_edp_swing_pre_emph_cfg *swing_pre_emph_cfg;
+ const struct qcom_edp_swing_pre_emph_cfg *dp_swing_pre_emph_cfg;
+ const struct qcom_edp_swing_pre_emph_cfg *edp_swing_pre_emph_cfg;
const struct phy_ver_ops *ver_ops;
};
@@ -150,6 +151,20 @@ static const struct qcom_edp_swing_pre_emph_cfg dp_phy_swing_pre_emph_cfg = {
.pre_emphasis_hbr3_hbr2 = &dp_pre_emp_hbr2_hbr3,
};
+static const u8 dp_pre_emp_hbr_rbr_v8[4][4] = {
+ { 0x00, 0x0e, 0x15, 0x1a },
+ { 0x00, 0x0e, 0x15, 0xff },
+ { 0x00, 0x0e, 0xff, 0xff },
+ { 0x00, 0xff, 0xff, 0xff }
+};
+
+static const struct qcom_edp_swing_pre_emph_cfg dp_phy_swing_pre_emph_cfg_v8 = {
+ .swing_hbr_rbr = &dp_swing_hbr_rbr,
+ .swing_hbr3_hbr2 = &dp_swing_hbr2_hbr3,
+ .pre_emphasis_hbr_rbr = &dp_pre_emp_hbr_rbr_v8,
+ .pre_emphasis_hbr3_hbr2 = &dp_pre_emp_hbr2_hbr3,
+};
+
static const u8 edp_swing_hbr_rbr[4][4] = {
{ 0x07, 0x0f, 0x16, 0x1f },
{ 0x0d, 0x16, 0x1e, 0xff },
@@ -246,7 +261,7 @@ static int qcom_edp_phy_init(struct phy *phy)
* when more information becomes available about why this is
* even needed.
*/
- if (edp->cfg->swing_pre_emph_cfg && !edp->is_edp)
+ if (edp->cfg->dp_swing_pre_emph_cfg && !edp->is_edp)
aux_cfg[8] = 0xb7;
writel(0xfc, edp->edp + DP_PHY_MODE);
@@ -270,7 +285,7 @@ static int qcom_edp_phy_init(struct phy *phy)
static int qcom_edp_set_voltages(struct qcom_edp *edp, const struct phy_configure_opts_dp *dp_opts)
{
- const struct qcom_edp_swing_pre_emph_cfg *cfg = edp->cfg->swing_pre_emph_cfg;
+ const struct qcom_edp_swing_pre_emph_cfg *cfg;
unsigned int v_level = 0;
unsigned int p_level = 0;
u8 ldo_config;
@@ -278,12 +293,14 @@ static int qcom_edp_set_voltages(struct qcom_edp *edp, const struct phy_configur
u8 emph;
int i;
+ if (edp->is_edp)
+ cfg = edp->cfg->edp_swing_pre_emph_cfg;
+ else
+ cfg = edp->cfg->dp_swing_pre_emph_cfg;
+
if (!cfg)
return 0;
- if (edp->is_edp)
- cfg = &edp_phy_swing_pre_emph_cfg;
-
for (i = 0; i < dp_opts->lanes; i++) {
v_level = max(v_level, dp_opts->voltage[i]);
p_level = max(p_level, dp_opts->pre[i]);
@@ -543,7 +560,8 @@ static const struct qcom_edp_phy_cfg sa8775p_dp_phy_cfg = {
.is_edp = false,
.aux_cfg = edp_phy_aux_cfg_v5,
.vco_div_cfg = edp_phy_vco_div_cfg_v4,
- .swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg,
+ .dp_swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg,
+ .edp_swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg,
.ver_ops = &qcom_edp_phy_ops_v4,
};
@@ -556,7 +574,8 @@ static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg = {
static const struct qcom_edp_phy_cfg sc8280xp_dp_phy_cfg = {
.aux_cfg = edp_phy_aux_cfg_v4,
.vco_div_cfg = edp_phy_vco_div_cfg_v4,
- .swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg,
+ .dp_swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg,
+ .edp_swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg,
.ver_ops = &qcom_edp_phy_ops_v4,
};
@@ -564,7 +583,8 @@ static const struct qcom_edp_phy_cfg sc8280xp_edp_phy_cfg = {
.is_edp = true,
.aux_cfg = edp_phy_aux_cfg_v4,
.vco_div_cfg = edp_phy_vco_div_cfg_v4,
- .swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg,
+ .dp_swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg,
+ .edp_swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg,
.ver_ops = &qcom_edp_phy_ops_v4,
};
@@ -745,7 +765,8 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v6 = {
static struct qcom_edp_phy_cfg x1e80100_phy_cfg = {
.aux_cfg = edp_phy_aux_cfg_v4,
.vco_div_cfg = edp_phy_vco_div_cfg_v4,
- .swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg,
+ .dp_swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg,
+ .edp_swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg,
.ver_ops = &qcom_edp_phy_ops_v6,
};
@@ -924,7 +945,8 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v8 = {
static struct qcom_edp_phy_cfg glymur_phy_cfg = {
.aux_cfg = edp_phy_aux_cfg_v8,
.vco_div_cfg = edp_phy_vco_div_cfg_v8,
- .swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg,
+ .dp_swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg_v8,
+ .edp_swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg,
.ver_ops = &qcom_edp_phy_ops_v8,
};
@@ -942,7 +964,7 @@ static int qcom_edp_phy_power_on(struct phy *phy)
if (ret)
return ret;
- if (edp->cfg->swing_pre_emph_cfg && !edp->is_edp)
+ if (edp->cfg->edp_swing_pre_emph_cfg && !edp->is_edp)
ldo_config = 0x1;
writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG);
--
2.43.0
--
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^ permalink raw reply related
* [PATCH v5 1/5] phy: qcom: edp: Unify generic DP/eDP swing and pre-emphasis tables
From: Yongxing Mou @ 2026-04-27 6:35 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Stephen Boyd, Bjorn Andersson
Cc: linux-arm-msm, linux-phy, linux-kernel, Yongxing Mou, stable,
Konrad Dybcio, Dmitry Baryshkov
In-Reply-To: <20260427-edp_phy-v5-0-3bb876824475@oss.qualcomm.com>
The current eDP and DP swing/pre-emphasis tables do not match the HPG
requirements for the supported platforms, correct the table accordingly.
The generic tables which can be shared as follows:
DP mode:
-sa8775p/sc7280/sc8280xp/x1e80100
-glymur
-sc8180x
eDP mode(low vdiff):
-glymur/sa8775p/sc8280xp/x1e80100
-sc7280
-sc8180x
The proper tables for SC8180X and SC7280 will be added in a later patch,
since they need separate table.
Cc: stable@vger.kernel.org
Fixes: f199223cb490 ("phy: qcom: Introduce new eDP PHY driver")
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
---
drivers/phy/qualcomm/phy-qcom-edp.c | 41 +++++++++----------------------------
1 file changed, 10 insertions(+), 31 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c
index 7372de05a0b8..2af3fd63832f 100644
--- a/drivers/phy/qualcomm/phy-qcom-edp.c
+++ b/drivers/phy/qualcomm/phy-qcom-edp.c
@@ -116,17 +116,17 @@ struct qcom_edp {
};
static const u8 dp_swing_hbr_rbr[4][4] = {
- { 0x08, 0x0f, 0x16, 0x1f },
+ { 0x07, 0x0f, 0x16, 0x1f },
{ 0x11, 0x1e, 0x1f, 0xff },
{ 0x16, 0x1f, 0xff, 0xff },
{ 0x1f, 0xff, 0xff, 0xff }
};
static const u8 dp_pre_emp_hbr_rbr[4][4] = {
- { 0x00, 0x0d, 0x14, 0x1a },
+ { 0x00, 0x0e, 0x15, 0x1a },
{ 0x00, 0x0e, 0x15, 0xff },
{ 0x00, 0x0e, 0xff, 0xff },
- { 0x03, 0xff, 0xff, 0xff }
+ { 0x04, 0xff, 0xff, 0xff }
};
static const u8 dp_swing_hbr2_hbr3[4][4] = {
@@ -158,7 +158,7 @@ static const u8 edp_swing_hbr_rbr[4][4] = {
};
static const u8 edp_pre_emp_hbr_rbr[4][4] = {
- { 0x05, 0x12, 0x17, 0x1d },
+ { 0x05, 0x11, 0x17, 0x1d },
{ 0x05, 0x11, 0x18, 0xff },
{ 0x06, 0x11, 0xff, 0xff },
{ 0x00, 0xff, 0xff, 0xff }
@@ -172,10 +172,10 @@ static const u8 edp_swing_hbr2_hbr3[4][4] = {
};
static const u8 edp_pre_emp_hbr2_hbr3[4][4] = {
- { 0x08, 0x11, 0x17, 0x1b },
- { 0x00, 0x0c, 0x13, 0xff },
- { 0x05, 0x10, 0xff, 0xff },
- { 0x00, 0xff, 0xff, 0xff }
+ { 0x0c, 0x15, 0x19, 0x1e },
+ { 0x0b, 0x15, 0x19, 0xff },
+ { 0x0e, 0x14, 0xff, 0xff },
+ { 0x0d, 0xff, 0xff, 0xff }
};
static const struct qcom_edp_swing_pre_emph_cfg edp_phy_swing_pre_emph_cfg = {
@@ -193,27 +193,6 @@ static const u8 edp_phy_vco_div_cfg_v4[4] = {
0x01, 0x01, 0x02, 0x00,
};
-static const u8 edp_pre_emp_hbr_rbr_v5[4][4] = {
- { 0x05, 0x11, 0x17, 0x1d },
- { 0x05, 0x11, 0x18, 0xff },
- { 0x06, 0x11, 0xff, 0xff },
- { 0x00, 0xff, 0xff, 0xff }
-};
-
-static const u8 edp_pre_emp_hbr2_hbr3_v5[4][4] = {
- { 0x0c, 0x15, 0x19, 0x1e },
- { 0x0b, 0x15, 0x19, 0xff },
- { 0x0e, 0x14, 0xff, 0xff },
- { 0x0d, 0xff, 0xff, 0xff }
-};
-
-static const struct qcom_edp_swing_pre_emph_cfg edp_phy_swing_pre_emph_cfg_v5 = {
- .swing_hbr_rbr = &edp_swing_hbr_rbr,
- .swing_hbr3_hbr2 = &edp_swing_hbr2_hbr3,
- .pre_emphasis_hbr_rbr = &edp_pre_emp_hbr_rbr_v5,
- .pre_emphasis_hbr3_hbr2 = &edp_pre_emp_hbr2_hbr3_v5,
-};
-
static const u8 edp_phy_aux_cfg_v5[DP_AUX_CFG_SIZE] = {
0x00, 0x13, 0xa4, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03, 0x02, 0x02, 0x00,
};
@@ -564,7 +543,7 @@ static const struct qcom_edp_phy_cfg sa8775p_dp_phy_cfg = {
.is_edp = false,
.aux_cfg = edp_phy_aux_cfg_v5,
.vco_div_cfg = edp_phy_vco_div_cfg_v4,
- .swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg_v5,
+ .swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg,
.ver_ops = &qcom_edp_phy_ops_v4,
};
@@ -945,7 +924,7 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v8 = {
static struct qcom_edp_phy_cfg glymur_phy_cfg = {
.aux_cfg = edp_phy_aux_cfg_v8,
.vco_div_cfg = edp_phy_vco_div_cfg_v8,
- .swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg_v5,
+ .swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg,
.ver_ops = &qcom_edp_phy_ops_v8,
};
--
2.43.0
--
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^ permalink raw reply related
* [PATCH v5 0/5] phy: qcom: edp: Add DP/eDP switch for phys
From: Yongxing Mou @ 2026-04-27 6:35 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Stephen Boyd, Bjorn Andersson
Cc: linux-arm-msm, linux-phy, linux-kernel, Yongxing Mou, stable,
Konrad Dybcio, Dmitry Baryshkov
Currently the PHY selects the DP/eDP configuration tables in a fixed way,
choosing the table when enable. This driver has known issues:
1. The selected table does not match the actual platform mode.
2. It cannot support both modes at the same time.
As discussed here[1], this series:
1. Cleans up duplicated and incorrect tables based on the HPG.
2. Fixes the LDO programming error in eDP mode.
3. Adds DP/eDP mode switching support.
Note: x1e80100/sa8775p/sc7280/SC8280XP have been tested, while
glymur/sc8180x have not been tested.
[1] https://lore.kernel.org/all/20260119-klm_dpphy-v2-1-52252190940b@oss.qualcomm.com/
Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
---
Changes in v5:
- Correct the incorrect swing/pre-emphasis table used on SC8180x.[Konard][Dmitry]
- Fix the commit message and add the missing Fixes tag.[Dmitry]
- Reuse the HBR3 table for the RBR case on SC8180x.[Konard]
- Link to v4: https://lore.kernel.org/r/20260422-edp_phy-v4-0-c38bef2d027b@oss.qualcomm.com
Changes in v4:
- Splite changes.[Dmitry]
- Add sc8180x tables in a single chagne.[Dmitry][Konrad]
- Link to v3: https://lore.kernel.org/r/20260302-edp_phy-v3-0-ca8888d793b0@oss.qualcomm.com
Changes in v3:
- Rebase to next-20260224.[Dmitry]
- Only enable TX1 LDO when lane counts > 2.[Konrad]
- Link to v2: https://lore.kernel.org/all/20260213-edp_phy-v2-0-43c40976435e@oss.qualcomm.com/
Changes in v2:
- Combine the third patch with the first one.[Dmitry]
- Fix code formatting issues.[Konrad][Dmitry]
- Update the commit message description.[Dmitry][Konrad]
- Fix kodiak swing/pre_emp table values.[Konrad]
---
Yongxing Mou (5):
phy: qcom: edp: Unify generic DP/eDP swing and pre-emphasis tables
phy: qcom: edp: Add eDP/DP mode switch support
phy: qcom: edp: Add SC7280/SC8180X swing/pre-emphasis tables
phy: qcom: edp: Fix AUX_CFG8 programming for DP mode
phy: qcom: edp: Add PHY-specific LDO config for eDP low vdiff
drivers/phy/qualcomm/phy-qcom-edp.c | 224 +++++++++++++++++++++++++++++-------
1 file changed, 181 insertions(+), 43 deletions(-)
---
base-commit: bee6ea30c48788e18348309f891ed8afbf7702ac
change-id: 20260205-edp_phy-1eca3ed074c0
Best regards,
--
Yongxing Mou <yongxing.mou@oss.qualcomm.com>
--
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^ permalink raw reply
* Re: [PATCH v4 3/5] phy: qcom: edp: Add SC7280/SC8180X swing/pre-emphasis tables
From: Yongxing Mou @ 2026-04-27 6:27 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Konrad Dybcio, Vinod Koul, Neil Armstrong, Stephen Boyd,
Bjorn Andersson, linux-arm-msm, linux-phy, linux-kernel
In-Reply-To: <ocydv6bbja7z46yjidtemwxtvwyxc4jpmnsc5uz7eorshgr36r@v4e7oo4sgeol>
On 4/23/2026 12:41 PM, Dmitry Baryshkov wrote:
> On Thu, Apr 23, 2026 at 11:28:44AM +0800, Yongxing Mou wrote:
>>
>>
>> On 4/22/2026 6:42 PM, Konrad Dybcio wrote:
>>> The swing and preem settings for HBR3 look OK
>>>
>>> For DP / low-Vdiff:
>>>
>>> .swing_hbr3_hbr2 OK
>>> .swing_hbr_rbr - I don't know. The docs are unclear whether the same
>>> settings should be used for RBR and HBR3, but maybe? There's a
>>> separate table for mini-DP but I doubt there's any poipu boards with
>>> such a connector (maybe some obscure ones)
>>>
>>> .pre_emphasis_hbr3_hbr2 OK
>>> .pre_emphasis_hbr_rbr same as above
>>>
>> Thanks for point this, so pre_emphasis_hbr_rbr same with
>> pre_emphasis_hbr3_hbr2? I also don't get it's RBR or HBR3 from phy HPG. But
>> now i think only eDP will be used in upstreamed poipu boards. i check the
>> dts and not find any poipu boards will use DP mode(or mini DP)..
>
> After checking the HPG, could you please actually talk to the colleagues
> who brough up the PHY on those platforms (with the downstreaam kernels)?
> They might know the details not captured in the HPG.
>
The driver actually existed in the very first upstream version, but it
didn’t use any tables back then.
On the downstream side, I couldn’t find any 7nm eDP PHY implementations
either.
I tried reaching out to a few teams, but this platform is quite old and
most people don’t really have context any more. My understanding is that
it was primarily a compute-oriented chip, but I’m not very familiar with
that code path myself. At this point, the only remaining option is to
try contacting the hardware team to see if they have any additional
insights.
Since this is unlikely to be resolved quickly, I’d like to proceed with
posting the next revision first. For SC8180X, it should only ever be
using eDP mode.
--
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^ permalink raw reply
* [PATCH v2] dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Document Nord QMP UFS PHY
From: Shawn Guo @ 2026-04-27 1:27 UTC (permalink / raw)
To: Vinod Koul
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio,
Dmitry Baryshkov, Bartosz Golaszewski, Deepti Jaggi, linux-phy,
devicetree, linux-arm-msm, linux-kernel, Shawn Guo
Document QMP UFS PHY on Qualcomm Nord SoC which is compatible with
'qcom,sm8650-qmp-ufs-phy'.
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
---
Changes in v2:
- Add Nord compatible to existing qcom,sm8650-qmp-ufs-phy item instead
of duplicating (Thanks Krzysztof!)
- Link to v1: https://lore.kernel.org/all/20260420074942.1250414-1-shengchao.guo@oss.qualcomm.com/
.../devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
index 9616c736b6d4..b2c5c9a375a3 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
@@ -31,6 +31,7 @@ properties:
- items:
- enum:
- qcom,eliza-qmp-ufs-phy
+ - qcom,nord-qmp-ufs-phy
- const: qcom,sm8650-qmp-ufs-phy
- items:
- enum:
--
2.43.0
--
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^ permalink raw reply related
* [PATCH v3] phy: rockchip: naneng-combphy: Consolidate SSC configuration
From: Shawn Lin @ 2026-04-27 0:57 UTC (permalink / raw)
To: Vinod Koul
Cc: linux-rockchip, linux-phy, Heiko Stuebner, Neil Armstrong,
Shawn Lin
The PCIe SSC configuration for the RK3588 and RK3576 SoCs required
additional tuning which is missing. When adding these same SSC
configurations for both of these two SoCs, as well as upcoming
platforms, it's obvious the SSC setup code was largely duplicated
across the platform-specific configuration functions. This becomes
harder to maintain as more platforms are added.
So extract the common SSC logic into a shared helper function,
rk_combphy_common_cfg_ssc(). This cleans up the per-platform drivers
and centralizes the standard configuration as possible.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
.../rockchip/phy-rockchip-naneng-combphy.c | 173 ++++++++----------
1 file changed, 73 insertions(+), 100 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index b60d6bf3f33c..2b0f152f5470 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -121,6 +121,7 @@
#define RK3568_PHYREG32_SSC_OFFSET_500PPM 1
#define RK3568_PHYREG33 0x80
+#define RK3568_PHYREG33_PLL_SSC_CTRL BIT(5)
#define RK3568_PHYREG33_PLL_KVCO_MASK GENMASK(4, 2)
#define RK3568_PHYREG33_PLL_KVCO_SHIFT 2
#define RK3568_PHYREG33_PLL_KVCO_VALUE 2
@@ -446,6 +447,74 @@ static int rockchip_combphy_probe(struct platform_device *pdev)
return PTR_ERR_OR_ZERO(phy_provider);
}
+static void rk_combphy_common_cfg_ssc(struct rockchip_combphy_priv *priv, unsigned long rate)
+{
+ struct device_node *np = priv->dev->of_node;
+ u32 val;
+
+ if (!priv->enable_ssc)
+ return;
+
+ /* Set SSC downward spread spectrum for PCIe and USB3 */
+ if (priv->type == PHY_TYPE_PCIE || priv->type == PHY_TYPE_USB3) {
+ val = FIELD_PREP(RK3568_PHYREG32_SSC_MASK, RK3568_PHYREG32_SSC_DOWNWARD);
+ rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
+ }
+
+ /* Set SSC downward spread spectrum +500ppm for SATA in 100MHz */
+ if (priv->type == PHY_TYPE_SATA && rate == REF_CLOCK_100MHz) {
+ val = FIELD_PREP(RK3568_PHYREG32_SSC_DIR_MASK,
+ RK3568_PHYREG32_SSC_DOWNWARD);
+ val |= FIELD_PREP(RK3568_PHYREG32_SSC_OFFSET_MASK,
+ RK3568_PHYREG32_SSC_OFFSET_500PPM);
+ rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val,
+ RK3568_PHYREG32);
+ }
+
+ /* Enable SSC */
+ val = readl(priv->mmio + RK3568_PHYREG8);
+ val |= RK3568_PHYREG8_SSC_EN;
+ writel(val, priv->mmio + RK3568_PHYREG8);
+
+ /* Some SoCs need tuning PCIe SSC instead of default configuration in 24MHz */
+ if (!of_device_is_compatible(np, "rockchip,rk3588-naneng-combphy") &&
+ !of_device_is_compatible(np, "rockchip,rk3576-naneng-combphy"))
+ return;
+
+ /* PLL control SSC module period should be set if need tuning */
+ val = readl(priv->mmio + RK3568_PHYREG33);
+ val |= RK3568_PHYREG33_PLL_SSC_CTRL;
+ writel(val, priv->mmio + RK3568_PHYREG33);
+
+ if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_24MHz) {
+ /* Set PLL loop divider */
+ writel(0x00, priv->mmio + RK3576_PHYREG17);
+ writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
+
+ /* Set up rx_pck invert and rx msb to disable */
+ writel(0x00, priv->mmio + RK3588_PHYREG27);
+
+ /*
+ * Set up SU adjust signal:
+ * su_trim[7:0], PLL KVCO adjust bits[2:0] to min
+ * su_trim[15:8], PLL LPF R1 adujst bits[9:7]=3'b101
+ * su_trim[23:16], CKRCV adjust
+ * su_trim[31:24], CKDRV adjust
+ */
+ writel(0x90, priv->mmio + RK3568_PHYREG11);
+ writel(0x02, priv->mmio + RK3568_PHYREG12);
+ writel(0x08, priv->mmio + RK3568_PHYREG13);
+ writel(0x57, priv->mmio + RK3568_PHYREG14);
+ writel(0x40, priv->mmio + RK3568_PHYREG15);
+
+ writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
+
+ val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
+ RK3576_PHYREG33_PLL_KVCO_VALUE);
+ writel(val, priv->mmio + RK3568_PHYREG33);
+ }
+}
+
static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
{
const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
@@ -600,21 +669,12 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
switch (priv->type) {
case PHY_TYPE_PCIE:
- /* Set SSC downward spread spectrum */
- val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT;
- rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
-
rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
break;
case PHY_TYPE_USB3:
- /* Set SSC downward spread spectrum */
- val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT;
- rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val,
- RK3568_PHYREG32);
-
/* Enable adaptive CTLE for USB3.0 Rx */
rockchip_combphy_updatel(priv, RK3568_PHYREG15_CTLE_EN,
RK3568_PHYREG15_CTLE_EN, RK3568_PHYREG15);
@@ -706,11 +766,7 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
}
}
- if (priv->enable_ssc) {
- val = readl(priv->mmio + RK3568_PHYREG8);
- val |= RK3568_PHYREG8_SSC_EN;
- writel(val, priv->mmio + RK3568_PHYREG8);
- }
+ rk_combphy_common_cfg_ssc(priv, rate);
return 0;
}
@@ -755,11 +811,6 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
switch (priv->type) {
case PHY_TYPE_PCIE:
- /* Set SSC downward spread spectrum. */
- val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT;
-
- rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
-
rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
@@ -767,10 +818,6 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
break;
case PHY_TYPE_USB3:
- /* Set SSC downward spread spectrum. */
- val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT,
- rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
-
/* Enable adaptive CTLE for USB3.0 Rx. */
val = readl(priv->mmio + RK3568_PHYREG15);
val |= RK3568_PHYREG15_CTLE_EN;
@@ -880,13 +927,6 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
- } else if (priv->type == PHY_TYPE_SATA) {
- /* downward spread spectrum +500ppm */
- val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT;
- val |= RK3568_PHYREG32_SSC_OFFSET_500PPM <<
- RK3568_PHYREG32_SSC_OFFSET_SHIFT;
- rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val,
- RK3568_PHYREG32);
}
break;
@@ -909,11 +949,7 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
}
}
- if (priv->enable_ssc) {
- val = readl(priv->mmio + RK3568_PHYREG8);
- val |= RK3568_PHYREG8_SSC_EN;
- writel(val, priv->mmio + RK3568_PHYREG8);
- }
+ rk_combphy_common_cfg_ssc(priv, rate);
return 0;
}
@@ -972,10 +1008,6 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
switch (priv->type) {
case PHY_TYPE_PCIE:
- /* Set SSC downward spread spectrum */
- val = FIELD_PREP(RK3568_PHYREG32_SSC_MASK, RK3568_PHYREG32_SSC_DOWNWARD);
- rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
-
rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
@@ -983,10 +1015,6 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
break;
case PHY_TYPE_USB3:
- /* Set SSC downward spread spectrum */
- val = FIELD_PREP(RK3568_PHYREG32_SSC_MASK, RK3568_PHYREG32_SSC_DOWNWARD);
- rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
-
/* Enable adaptive CTLE for USB3.0 Rx */
val = readl(priv->mmio + RK3568_PHYREG15);
val |= RK3568_PHYREG15_CTLE_EN;
@@ -1110,14 +1138,6 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
writel(0x88, priv->mmio + RK3568_PHYREG13);
writel(0x56, priv->mmio + RK3568_PHYREG14);
} else if (priv->type == PHY_TYPE_SATA) {
- /* downward spread spectrum +500ppm */
- val = FIELD_PREP(RK3568_PHYREG32_SSC_DIR_MASK,
- RK3568_PHYREG32_SSC_DOWNWARD);
- val |= FIELD_PREP(RK3568_PHYREG32_SSC_OFFSET_MASK,
- RK3568_PHYREG32_SSC_OFFSET_500PPM);
- rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val,
- RK3568_PHYREG32);
-
/* ssc ppm adjust to 3500ppm */
rockchip_combphy_updatel(priv, RK3576_PHYREG10_SSC_PCM_MASK,
RK3576_PHYREG10_SSC_PCM_3500PPM,
@@ -1156,39 +1176,7 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
}
}
- if (priv->enable_ssc) {
- val = readl(priv->mmio + RK3568_PHYREG8);
- val |= RK3568_PHYREG8_SSC_EN;
- writel(val, priv->mmio + RK3568_PHYREG8);
-
- if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_24MHz) {
- /* Set PLL loop divider */
- writel(0x00, priv->mmio + RK3576_PHYREG17);
- writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
-
- /* Set up rx_pck invert and rx msb to disable */
- writel(0x00, priv->mmio + RK3588_PHYREG27);
-
- /*
- * Set up SU adjust signal:
- * su_trim[7:0], PLL KVCO adjust bits[2:0] to min
- * su_trim[15:8], PLL LPF R1 adujst bits[9:7]=3'b101
- * su_trim[23:16], CKRCV adjust
- * su_trim[31:24], CKDRV adjust
- */
- writel(0x90, priv->mmio + RK3568_PHYREG11);
- writel(0x02, priv->mmio + RK3568_PHYREG12);
- writel(0x08, priv->mmio + RK3568_PHYREG13);
- writel(0x57, priv->mmio + RK3568_PHYREG14);
- writel(0x40, priv->mmio + RK3568_PHYREG15);
-
- writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
-
- val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
- RK3576_PHYREG33_PLL_KVCO_VALUE);
- writel(val, priv->mmio + RK3568_PHYREG33);
- }
- }
+ rk_combphy_common_cfg_ssc(priv, rate);
return 0;
}
@@ -1255,10 +1243,6 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
}
break;
case PHY_TYPE_USB3:
- /* Set SSC downward spread spectrum */
- val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT;
- rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
-
/* Enable adaptive CTLE for USB3.0 Rx. */
val = readl(priv->mmio + RK3568_PHYREG15);
val |= RK3568_PHYREG15_CTLE_EN;
@@ -1343,13 +1327,6 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
/* Set up su_trim: */
writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
- } else if (priv->type == PHY_TYPE_SATA) {
- /* downward spread spectrum +500ppm */
- val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT;
- val |= RK3568_PHYREG32_SSC_OFFSET_500PPM <<
- RK3568_PHYREG32_SSC_OFFSET_SHIFT;
- rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val,
- RK3568_PHYREG32);
}
break;
default:
@@ -1371,11 +1348,7 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
}
}
- if (priv->enable_ssc) {
- val = readl(priv->mmio + RK3568_PHYREG8);
- val |= RK3568_PHYREG8_SSC_EN;
- writel(val, priv->mmio + RK3568_PHYREG8);
- }
+ rk_combphy_common_cfg_ssc(priv, rate);
return 0;
}
--
2.43.0
--
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^ permalink raw reply related
* Re: [PATCH] phy: rockchip: naneng-combphy: Fix TX detect RX termination errata
From: Shawn Lin @ 2026-04-27 0:42 UTC (permalink / raw)
To: Vinod Koul, linux-phy
Cc: shawn.lin, linux-rockchip, Heiko Stuebner, Neil Armstrong,
linux-kernel
In-Reply-To: <1774423383-36599-1-git-send-email-shawn.lin@rock-chips.com>
Ping...
在 2026/03/25 星期三 15:23, Shawn Lin 写道:
> Some PHY revisions may fail to detect the peer RX's termination
> resistor (RTERM) under certain critical temperature conditions.
> This causes TX detection failures on PCIe links.
>
> Add a workaround to force the RTERM detection ready signal for
> affected PHY revisions. This ensures reliable TX-to-RX termination
> detection across all operating temperature ranges.
>
> The fix applies to RK3562, RK3568, RK3576 and RK3588 SoCs which share
> the same PHY IP with this hardware errata.
>
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> ---
>
> drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> index b60d6bf..76d4994 100644
> --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> @@ -106,6 +106,9 @@
> #define RK3568_PHYREG18 0x44
> #define RK3568_PHYREG18_PLL_LOOP 0x32
>
> +#define RK3568_PHYREG26 0x64
> +#define RK3568_PHYREG26_FORCE_RTERM_DET_RDY BIT(5)
> +
> #define RK3568_PHYREG30 0x74
> #define RK3568_PHYREG30_GATE_TX_PCK_SEL BIT(7)
> #define RK3568_PHYREG30_GATE_TX_PCK_DLY_PLL_OFF BIT(7)
> @@ -193,6 +196,7 @@ struct rockchip_combphy_cfg {
> unsigned int num_phys;
> unsigned int phy_ids[3];
> const struct rockchip_combphy_grfcfg *grfcfg;
> + bool force_rxterm_det_rdy;
> int (*combphy_cfg)(struct rockchip_combphy_priv *priv);
> };
>
> @@ -264,6 +268,17 @@ static int rockchip_combphy_init(struct phy *phy)
>
> switch (priv->type) {
> case PHY_TYPE_PCIE:
> + /*
> + * Hardware Errata: TX fails to detect peer RX termination.
> + * Some PHY revisions may fail to detect remote RX's RTERM
> + * (receiver termination resistor) under certain critical
> + * temperature conditions. Set force rterm detect ready to
> + * fix it.
> + */
> + if (priv->cfg->force_rxterm_det_rdy)
> + rockchip_combphy_updatel(priv, RK3568_PHYREG26_FORCE_RTERM_DET_RDY,
> + RK3568_PHYREG26_FORCE_RTERM_DET_RDY, RK3568_PHYREG26);
> + fallthrough;
> case PHY_TYPE_USB3:
> case PHY_TYPE_SATA:
> case PHY_TYPE_SGMII:
> @@ -745,6 +760,7 @@ static const struct rockchip_combphy_cfg rk3562_combphy_cfgs = {
> },
> .grfcfg = &rk3562_combphy_grfcfgs,
> .combphy_cfg = rk3562_combphy_cfg,
> + .force_rxterm_det_rdy = true,
> };
>
> static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
> @@ -962,6 +978,7 @@ static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
> },
> .grfcfg = &rk3568_combphy_grfcfgs,
> .combphy_cfg = rk3568_combphy_cfg,
> + .force_rxterm_det_rdy = true,
> };
>
> static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
> @@ -1231,6 +1248,7 @@ static const struct rockchip_combphy_cfg rk3576_combphy_cfgs = {
> },
> .grfcfg = &rk3576_combphy_grfcfgs,
> .combphy_cfg = rk3576_combphy_cfg,
> + .force_rxterm_det_rdy = true,
> };
>
> static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
> @@ -1418,6 +1436,7 @@ static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = {
> },
> .grfcfg = &rk3588_combphy_grfcfgs,
> .combphy_cfg = rk3588_combphy_cfg,
> + .force_rxterm_det_rdy = true,
> };
>
> static const struct of_device_id rockchip_combphy_of_match[] = {
--
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^ permalink raw reply
* [PATCH] phy: tegra: xusb: Make USB_CONN_GPIO select conditional on GPIOLIB
From: Sasha Levin @ 2026-04-26 0:03 UTC (permalink / raw)
To: Vinod Koul
Cc: Neil Armstrong, Thierry Reding, Jonathan Hunter, Niklas Cassel,
Vidya Sagar, Sasha Levin, linux-phy, linux-tegra, linux-kernel
kconfiglint reports:
K006: config PHY_TEGRA_XUSB selects USB_CONN_GPIO which depends on
GPIOLIB, but PHY_TEGRA_XUSB does not depend on GPIOLIB
K002: config PHY_TEGRA_XUSB selects visible symbol USB_CONN_GPIO
which has dependencies
USB_CONN_GPIO was introduced in commit 4602f3bff266 ("usb: common: add USB
GPIO based connection detection driver") with a hard dependency on GPIOLIB,
since it needs GPIO pins to detect USB cable connection state.
Commit f67213cee2b3 ("phy: tegra: xusb: Add usb-role-switch support") added
`select USB_CONN_GPIO` to PHY_TEGRA_XUSB to support USB role switching via
GPIO-based detection. At that time, PHY_TEGRA_XUSB depended only on
`ARCH_TEGRA`, and both the ARM32 and ARM64 ARCH_TEGRA Kconfig definitions
select GPIOLIB, so the missing explicit GPIOLIB guard was not a functional
problem — GPIOLIB is always available when ARCH_TEGRA is enabled.
Later, commit 0d5c9bc7c680 ("phy: tegra: Select USB_COMMON for
usb_get_maximum_speed()") added `depends on USB_SUPPORT` but still did not
address the GPIOLIB gap.
The select can force USB_CONN_GPIO on without its GPIOLIB dependency being
satisfied if the Kconfig dependencies were ever restructured. Make the
select conditional with `select USB_CONN_GPIO if GPIOLIB` to make the
dependency explicit. This mirrors how other drivers handle optional
GPIO-dependent selects throughout the kernel.
Assisted-by: Claude:claude-opus-4-6 kconfiglint
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/phy/tegra/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/tegra/Kconfig b/drivers/phy/tegra/Kconfig
index 342fb736da4b1..f0734415fc94c 100644
--- a/drivers/phy/tegra/Kconfig
+++ b/drivers/phy/tegra/Kconfig
@@ -3,7 +3,7 @@ config PHY_TEGRA_XUSB
tristate "NVIDIA Tegra XUSB pad controller driver"
depends on ARCH_TEGRA && USB_SUPPORT
select USB_COMMON
- select USB_CONN_GPIO
+ select USB_CONN_GPIO if GPIOLIB
select USB_PHY
help
Choose this option if you have an NVIDIA Tegra SoC.
--
2.53.0
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^ permalink raw reply related
* [PATCH v3 1/2] dt-bindings: phy: Document PCIe PHY in EcoNet EN751221 and EN7528
From: Caleb James DeLisle @ 2026-04-25 17:36 UTC (permalink / raw)
To: linux-phy
Cc: naseefkm, vkoul, neil.armstrong, robh, krzk+dt, conor+dt,
linux-mips, devicetree, linux-kernel, Caleb James DeLisle,
Krzysztof Kozlowski
In-Reply-To: <20260425173642.406089-1-cjd@cjdns.fr>
EN751221 and EN7528 SoCs have two PCIe slots, and each one has a PHY
which behaves slightly differently because one slot is Gen1/Gen2 while
the other is Gen1 only.
Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
.../phy/econet,en751221-pcie-phy.yaml | 50 +++++++++++++++++++
MAINTAINERS | 6 +++
2 files changed, 56 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml
new file mode 100644
index 000000000000..987d396c1c64
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/econet,en751221-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: EcoNet PCI-Express PHY for EcoNet EN751221 and EN7528
+
+maintainers:
+ - Caleb James DeLisle <cjd@cjdns.fr>
+
+description:
+ The PCIe PHY supports physical layer functionality for PCIe Gen1 and
+ Gen1/Gen2 ports. On these SoCs, port 0 is a Gen1-only port while
+ port 1 is Gen1/Gen2 capable.
+
+properties:
+ compatible:
+ enum:
+ - econet,en751221-pcie-gen1
+ - econet,en751221-pcie-gen2
+ - econet,en7528-pcie-gen1
+ - econet,en7528-pcie-gen2
+
+ reg:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pcie-phy@1faf2000 {
+ compatible = "econet,en7528-pcie-gen1";
+ reg = <0x1faf2000 0x1000>;
+ #phy-cells = <0>;
+ };
+ };
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 62b89d0013d2..6fc1f54c31d2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9185,6 +9185,12 @@ F: drivers/irqchip/irq-econet-en751221.c
F: include/dt-bindings/clock/econet,en751221-scu.h
F: include/dt-bindings/reset/econet,en751221-scu.h
+ECONET PCIE PHY DRIVER
+M: Caleb James DeLisle <cjd@cjdns.fr>
+L: linux-mips@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml
+
ECRYPT FILE SYSTEM
M: Tyler Hicks <code@tyhicks.com>
L: ecryptfs@vger.kernel.org
--
2.39.5
--
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^ permalink raw reply related
* [PATCH v3 2/2] phy: econet: Add PCIe PHY driver for EcoNet EN751221 and EN7528 SoCs.
From: Caleb James DeLisle @ 2026-04-25 17:36 UTC (permalink / raw)
To: linux-phy
Cc: naseefkm, vkoul, neil.armstrong, robh, krzk+dt, conor+dt,
linux-mips, devicetree, linux-kernel, Caleb James DeLisle
In-Reply-To: <20260425173642.406089-1-cjd@cjdns.fr>
Introduce support for EcoNet PCIe PHY controllers found in EN751221
and EN7528 SoCs, these SoCs are not identical but are similar, each
having one Gen1 port, and one Gen1/Gen2 port.
Co-developed-by: Ahmed Naseef <naseefkm@gmail.com>
Signed-off-by: Ahmed Naseef <naseefkm@gmail.com>
[cjd@cjdns.fr: add EN751221 support and refactor for clarity]
Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
---
MAINTAINERS | 1 +
drivers/phy/Kconfig | 12 +++
drivers/phy/Makefile | 1 +
drivers/phy/phy-econet-pcie.c | 182 ++++++++++++++++++++++++++++++++++
4 files changed, 196 insertions(+)
create mode 100644 drivers/phy/phy-econet-pcie.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 6fc1f54c31d2..e7d7672c8ab3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9190,6 +9190,7 @@ M: Caleb James DeLisle <cjd@cjdns.fr>
L: linux-mips@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml
+F: drivers/phy/phy-econet-pcie.c
ECRYPT FILE SYSTEM
M: Tyler Hicks <code@tyhicks.com>
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 227b9a4c612e..9aad68829d72 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -66,6 +66,18 @@ config PHY_CAN_TRANSCEIVER
functional modes using gpios and sets the attribute max link
rate, for CAN drivers.
+config PHY_ECONET_PCIE
+ tristate "EcoNet PCIe-PHY Driver"
+ depends on ECONET || COMPILE_TEST
+ depends on OF
+ select GENERIC_PHY
+ select REGMAP_MMIO
+ help
+ Say Y here to add support for EcoNet PCIe PHY driver.
+ This driver create the basic PHY instance and provides initialize
+ callback for PCIe GEN1 and GEN2 ports. This PHY is found on
+ EcoNet SoCs including EN751221 and EN7528.
+
config PHY_GOOGLE_USB
tristate "Google Tensor SoC USB PHY driver"
select GENERIC_PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index f49d83f00a3d..42959ed383fd 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_GENERIC_PHY) += phy-core.o
obj-$(CONFIG_GENERIC_PHY_MIPI_DPHY) += phy-core-mipi-dphy.o
obj-$(CONFIG_PHY_AIROHA_PCIE) += phy-airoha-pcie.o
obj-$(CONFIG_PHY_CAN_TRANSCEIVER) += phy-can-transceiver.o
+obj-$(CONFIG_PHY_ECONET_PCIE) += phy-econet-pcie.o
obj-$(CONFIG_PHY_GOOGLE_USB) += phy-google-usb.o
obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o
obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o
diff --git a/drivers/phy/phy-econet-pcie.c b/drivers/phy/phy-econet-pcie.c
new file mode 100644
index 000000000000..96be69d1ffeb
--- /dev/null
+++ b/drivers/phy/phy-econet-pcie.c
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Author: Caleb James DeLisle <cjd@cjdns.fr>
+ * Ahmed Naseef <naseefkm@gmail.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/bits.h>
+#include <linux/delay.h>
+
+/* Rx detection timing for EN751221: 16*8 clock cycles */
+#define EN751221_RXDET_VAL 16
+
+/* Rx detection timing when in power mode 3 */
+#define EN75_RXDET_P3_REG 0xa28
+#define EN75_RXDET_P3_MASK GENMASK(17, 9)
+
+/* Rx detection timing when in power mode 2 */
+#define EN75_RXDET_P2_REG 0xa2c
+#define EN75_RXDET_P2_MASK GENMASK(8, 0)
+
+/* Rx impedance */
+#define EN75_RX_IMPEDANCE_REG 0xb2c
+#define EN75_RX_IMPEDANCE_MASK GENMASK(13, 12)
+enum en75_rx_impedance {
+ EN75_RX_IMPEDANCE_100_OHM = 0,
+ EN75_RX_IMPEDANCE_95_OHM = 1,
+ EN75_RX_IMPEDANCE_90_OHM = 2,
+};
+
+/* PLL Invert clock */
+#define EN75_PLL_PH_INV_REG 0x4a0
+#define EN75_PLL_PH_INV_MASK BIT(5)
+
+struct en75_phy_op {
+ u32 reg;
+ u32 mask;
+ u32 val;
+};
+
+struct en7528_pcie_phy {
+ struct regmap *regmap;
+ const struct en75_phy_op *data;
+};
+
+/* Port 0 PHY: set LCDDS_CLK_PH_INV for PLL operation */
+static const struct en75_phy_op en7528_phy_gen1[] = {
+ {
+ .reg = EN75_PLL_PH_INV_REG,
+ .mask = EN75_PLL_PH_INV_MASK,
+ .val = 1,
+ },
+ { /* sentinel */ }
+};
+
+/* EN7528 Port 1 PHY: Rx impedance tuning, target R -5 Ohm */
+static const struct en75_phy_op en7528_phy_gen2[] = {
+ {
+ .reg = EN75_RX_IMPEDANCE_REG,
+ .mask = EN75_RX_IMPEDANCE_MASK,
+ .val = EN75_RX_IMPEDANCE_95_OHM,
+ },
+ { /* sentinel */ }
+};
+
+/* EN751221 Port 1 PHY, set RX detect to 16*8 clock cycles */
+static const struct en75_phy_op en751221_phy_gen2[] = {
+ {
+ .reg = EN75_RXDET_P3_REG,
+ .mask = EN75_RXDET_P3_MASK,
+ .val = EN751221_RXDET_VAL,
+ },
+ {
+ .reg = EN75_RXDET_P2_REG,
+ .mask = EN75_RXDET_P2_MASK,
+ .val = EN751221_RXDET_VAL,
+ },
+ { /* sentinel */ }
+};
+
+static int en75_pcie_phy_init(struct phy *phy)
+{
+ struct en7528_pcie_phy *ephy = phy_get_drvdata(phy);
+ const struct en75_phy_op *data = ephy->data;
+ int i, ret;
+ u32 val;
+
+ for (i = 0; data[i].mask || data[i].val; i++) {
+ if (i)
+ usleep_range(1000, 2000);
+
+ val = field_prep(data[i].mask, data[i].val);
+
+ ret = regmap_update_bits(ephy->regmap, data[i].reg,
+ data[i].mask, val);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct phy_ops en75_pcie_phy_ops = {
+ .init = en75_pcie_phy_init,
+ .owner = THIS_MODULE,
+};
+
+static int en75_pcie_phy_probe(struct platform_device *pdev)
+{
+ struct regmap_config regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ };
+ struct device *dev = &pdev->dev;
+ const struct en75_phy_op *data;
+ struct phy_provider *provider;
+ struct en7528_pcie_phy *ephy;
+ void __iomem *base;
+ struct phy *phy;
+ int i;
+
+ data = of_device_get_match_data(dev);
+ if (!data)
+ return -EINVAL;
+
+ ephy = devm_kzalloc(dev, sizeof(*ephy), GFP_KERNEL);
+ if (!ephy)
+ return -ENOMEM;
+
+ ephy->data = data;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ /* Set max_register to highest used register */
+ for (i = 0; data[i].mask || data[i].val; i++)
+ if (data[i].reg > regmap_config.max_register)
+ regmap_config.max_register = data[i].reg;
+
+ ephy->regmap = devm_regmap_init_mmio(dev, base, ®map_config);
+ if (IS_ERR(ephy->regmap))
+ return PTR_ERR(ephy->regmap);
+
+ phy = devm_phy_create(dev, dev->of_node, &en75_pcie_phy_ops);
+ if (IS_ERR(phy))
+ return PTR_ERR(phy);
+
+ phy_set_drvdata(phy, ephy);
+
+ provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+ return PTR_ERR_OR_ZERO(provider);
+}
+
+static const struct of_device_id en75_pcie_phy_ids[] = {
+ { .compatible = "econet,en7528-pcie-gen1", .data = en7528_phy_gen1 },
+ { .compatible = "econet,en7528-pcie-gen2", .data = en7528_phy_gen2 },
+ { .compatible = "econet,en751221-pcie-gen1", .data = en7528_phy_gen1 },
+ { .compatible = "econet,en751221-pcie-gen2", .data = en751221_phy_gen2 },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, en75_pcie_phy_ids);
+
+static struct platform_driver en75_pcie_phy_driver = {
+ .probe = en75_pcie_phy_probe,
+ .driver = {
+ .name = "econet-pcie-phy",
+ .of_match_table = en75_pcie_phy_ids,
+ },
+};
+module_platform_driver(en75_pcie_phy_driver);
+
+MODULE_AUTHOR("Caleb James DeLisle <cjd@cjdns.fr>");
+MODULE_DESCRIPTION("EcoNet PCIe PHY driver");
+MODULE_LICENSE("GPL");
--
2.39.5
--
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^ permalink raw reply related
* [PATCH v3 0/2] phy: econet: Add PCIe PHY driver for EcoNet SoCs
From: Caleb James DeLisle @ 2026-04-25 17:36 UTC (permalink / raw)
To: linux-phy
Cc: naseefkm, vkoul, neil.armstrong, robh, krzk+dt, conor+dt,
linux-mips, devicetree, linux-kernel, Caleb James DeLisle
I just added explicit includes per the recommendation of
vladimiroltean/sashiko
See https://sashiko.dev/#/patchset/20260404184918.2184070-1-cjd@cjdns.fr
Changes from v2:
* Added includes per recommendation of vladimiroltean/sashiko
* Rebased on commit 7080e32d3f09 ("Add linux-next specific files for 20260424")
* v2: https://lore.kernel.org/linux-mips/20260404184918.2184070-1-cjd@cjdns.fr/
Changes from v1:
* Rebased on commit 2febe6e6ee6e ("Add linux-next specific files for 20260403")
* v1: https://lore.kernel.org/linux-mips/20260312164432.569566-1-cjd@cjdns.fr/
This is split from a larger PCIe patchset which crossed multiple
subsystems. I'm not labeling this a v3 because it's a new patchset, but
I'm keeping the historical record anyway.
Changes from econet-pcie v2: none relevant to this patch set
* econet-pcie v2: https://lore.kernel.org/linux-mips/20260309131818.74467-1-cjd@cjdns.fr
Changes from econet-pcie v1:
* econet,en751221-pcie-phy.yaml Refer to PHYs as "gen1" and "gen2"
* econet-pcie v1: https://lore.kernel.org/linux-mips/20260303190948.694783-1-cjd@cjdns.fr/
Caleb James DeLisle (2):
dt-bindings: phy: Document PCIe PHY in EcoNet EN751221 and EN7528
phy: econet: Add PCIe PHY driver for EcoNet EN751221 and EN7528 SoCs.
.../phy/econet,en751221-pcie-phy.yaml | 50 +++++
MAINTAINERS | 7 +
drivers/phy/Kconfig | 12 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-econet-pcie.c | 182 ++++++++++++++++++
5 files changed, 252 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml
create mode 100644 drivers/phy/phy-econet-pcie.c
base-commit: 7080e32d3f09d8688c4a87d81bdcc71f7f606b16
--
2.39.5
--
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^ permalink raw reply
* Re: [PATCH 3/4] dt-bindings: usb: qcom,snps-dwc3: Add Hawi compatible
From: Krzysztof Kozlowski @ 2026-04-25 10:32 UTC (permalink / raw)
To: Ronak Raheja
Cc: vkoul, krzk+dt, conor+dt, robh, neil.armstrong, gregkh,
dmitry.baryshkov, konrad.dybcio, abel.vesa, wesley.cheng,
linux-arm-msm, linux-phy, devicetree, linux-usb, linux-kernel
In-Reply-To: <20260425070002.348733-4-ronak.raheja@oss.qualcomm.com>
On Sat, Apr 25, 2026 at 12:00:01AM -0700, Ronak Raheja wrote:
> Document the Synopsys DWC3 USB controller found on the Hawi platform.
>
> Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
> ---
> Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml | 3 +++
> 1 file changed, 3 insertions(+)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH 2/4] dt-bindings: phy: qcom,m31-eusb2-phy: Document M31 eUSB2 PHY for Hawi
From: Krzysztof Kozlowski @ 2026-04-25 10:31 UTC (permalink / raw)
To: Ronak Raheja
Cc: vkoul, krzk+dt, conor+dt, robh, neil.armstrong, gregkh,
dmitry.baryshkov, konrad.dybcio, abel.vesa, wesley.cheng,
linux-arm-msm, linux-phy, devicetree, linux-usb, linux-kernel
In-Reply-To: <20260425070002.348733-3-ronak.raheja@oss.qualcomm.com>
On Sat, Apr 25, 2026 at 12:00:00AM -0700, Ronak Raheja wrote:
> Document the M31 eUSB2 PHY for Hawi which handles the USB2 path. Use
> fallback to indicate the compatibility of the M31 eUSB2 PHY on the Hawi
> with that on the SM8750.
>
> Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
> ---
> Documentation/devicetree/bindings/phy/qcom,m31-eusb2-phy.yaml | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
--
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^ permalink raw reply
* Re: [PATCH 1/4] dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add Hawi QMP PHY
From: Krzysztof Kozlowski @ 2026-04-25 10:30 UTC (permalink / raw)
To: Ronak Raheja
Cc: vkoul, krzk+dt, conor+dt, robh, neil.armstrong, gregkh,
dmitry.baryshkov, konrad.dybcio, abel.vesa, wesley.cheng,
linux-arm-msm, linux-phy, devicetree, linux-usb, linux-kernel
In-Reply-To: <20260425070002.348733-2-ronak.raheja@oss.qualcomm.com>
On Fri, Apr 24, 2026 at 11:59:59PM -0700, Ronak Raheja wrote:
> Document the Hawi compatible string for the QMP combo PHY.
Not compatible with Kaanapali and/or SM8750? That's quite obvious
question thus commit msg should briefly answer to it.
Best regards,
Krzysztof
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^ permalink raw reply
* [PATCH 4/4] phy: qualcomm: qmp-combo: Add support for Hawi SoC
From: Ronak Raheja @ 2026-04-25 7:00 UTC (permalink / raw)
To: vkoul, krzk+dt, conor+dt, robh, neil.armstrong, gregkh
Cc: dmitry.baryshkov, konrad.dybcio, abel.vesa, wesley.cheng,
ronak.raheja, linux-arm-msm, linux-phy, devicetree, linux-usb,
linux-kernel
In-Reply-To: <20260425070002.348733-1-ronak.raheja@oss.qualcomm.com>
Add support for the USB3-DP combo PHY found on Hawi platform.
The QMP PHY for Hawi uses QSERDES V10 register layouts. Add the required
PHY sequences from the hardware programming guide and new V10 register
header files. Also add a new v10 offset structure to incorporate the new
COM AON register module.
Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
---
.../phy/qualcomm/phy-qcom-qmp-com-aon-v10.h | 15 ++
drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 232 +++++++++++++++++-
.../phy/qualcomm/phy-qcom-qmp-dp-phy-v10.h | 15 ++
.../phy/qualcomm/phy-qcom-qmp-pcs-aon-v10.h | 13 +
.../phy/qualcomm/phy-qcom-qmp-pcs-usb-v10.h | 19 ++
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10.h | 34 +++
.../qualcomm/phy-qcom-qmp-qserdes-com-v10.h | 89 +++++++
.../qualcomm/phy-qcom-qmp-qserdes-txrx-v10.h | 89 +++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 5 +
9 files changed, 507 insertions(+), 4 deletions(-)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-com-aon-v10.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v10.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-aon-v10.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v10.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v10.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v10.h
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-com-aon-v10.h b/drivers/phy/qualcomm/phy-qcom-qmp-com-aon-v10.h
new file mode 100644
index 000000000000..6542b586be89
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-com-aon-v10.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2026, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_COM_AON_V10_H_
+#define QCOM_PHY_QMP_COM_AON_V10_H_
+
+/* Only for QMP V10 PHY - COM AON registers */
+
+#define QPHY_V10_COM_AON_USB3_AON_TOGGLE_ENABLE 0x00
+#define QPHY_V10_COM_AON_DP_AON_TOGGLE_ENABLE 0x04
+#define QPHY_V10_COM_AON_DUMMY_STATUS 0x08
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
index 93f1aa10d400..cce229101473 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
@@ -32,6 +32,7 @@
#include "phy-qcom-qmp.h"
#include "phy-qcom-qmp-pcs-aon-v6.h"
#include "phy-qcom-qmp-pcs-aon-v8.h"
+#include "phy-qcom-qmp-pcs-aon-v10.h"
#include "phy-qcom-qmp-pcs-misc-v3.h"
#include "phy-qcom-qmp-pcs-misc-v4.h"
#include "phy-qcom-qmp-pcs-misc-v5.h"
@@ -40,6 +41,7 @@
#include "phy-qcom-qmp-pcs-usb-v5.h"
#include "phy-qcom-qmp-pcs-usb-v6.h"
#include "phy-qcom-qmp-pcs-usb-v8.h"
+#include "phy-qcom-qmp-pcs-usb-v10.h"
#include "phy-qcom-qmp-dp-com-v3.h"
@@ -49,9 +51,12 @@
#include "phy-qcom-qmp-dp-phy-v5.h"
#include "phy-qcom-qmp-dp-phy-v6.h"
#include "phy-qcom-qmp-dp-phy-v8.h"
+#include "phy-qcom-qmp-dp-phy-v10.h"
#include "phy-qcom-qmp-usb43-pcs-v8.h"
+#include "phy-qcom-qmp-com-aon-v10.h"
+
/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
/* DP PHY soft reset */
#define SW_DPPHY_RESET BIT(0)
@@ -268,6 +273,36 @@ static const unsigned int qmp_v8_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V8_TX_TRANSCEIVER_BIAS_EN,
};
+static const unsigned int qmp_v10_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
+ [QPHY_SW_RESET] = QPHY_V10_PCS_SW_RESET,
+ [QPHY_START_CTRL] = QPHY_V10_PCS_START_CONTROL,
+ [QPHY_PCS_STATUS] = QPHY_V10_PCS_PCS_STATUS1,
+ [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V10_PCS_POWER_DOWN_CONTROL,
+
+ /* In PCS_USB */
+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V10_PCS_USB3_AUTONOMOUS_MODE_CTRL,
+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V10_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
+
+ [QPHY_PCS_CLAMP_ENABLE] = QPHY_V10_PCS_AON_CLAMP_ENABLE,
+
+ [QPHY_AON_TOGGLE_ENABLE] = QPHY_V10_COM_AON_USB3_AON_TOGGLE_ENABLE,
+ [QPHY_DP_AON_TOGGLE_ENABLE] = QPHY_V10_COM_AON_DP_AON_TOGGLE_ENABLE,
+
+ [QPHY_COM_RESETSM_CNTRL] = QSERDES_V10_COM_RESETSM_CNTRL,
+ [QPHY_COM_C_READY_STATUS] = QSERDES_V10_COM_C_READY_STATUS,
+ [QPHY_COM_CMN_STATUS] = QSERDES_V10_COM_CMN_STATUS,
+ [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V10_COM_BIAS_EN_CLKBUFLR_EN,
+
+ [QPHY_DP_PHY_STATUS] = QSERDES_V10_DP_PHY_STATUS,
+ [QPHY_DP_PHY_VCO_DIV] = QSERDES_V10_DP_PHY_VCO_DIV,
+
+ [QPHY_TX_TX_POL_INV] = QSERDES_V10_TX_TX_POL_INV,
+ [QPHY_TX_TX_DRV_LVL] = QSERDES_V10_TX_TX_DRV_LVL,
+ [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V10_TX_TX_EMP_POST1_LVL,
+ [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V10_TX_HIGHZ_DRVR_EN,
+ [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V10_TX_TRANSCEIVER_BIAS_EN,
+};
+
static const unsigned int qmp_v8_n3_usb43dpphy_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_SW_RESET] = QPHY_V8_USB43_PCS_SW_RESET,
[QPHY_START_CTRL] = QPHY_V8_USB43_PCS_START_CONTROL,
@@ -2058,6 +2093,142 @@ static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_usb_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
};
+static const struct qmp_phy_init_tbl hawi_usb3_serdes_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_STEP_SIZE1_MODE1, 0xc0),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_STEP_SIZE2_MODE1, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_CP_CTRL_MODE1, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_PLL_RCTRL_MODE1, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_PLL_CCTRL_MODE1, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_CORECLK_DIV_MODE1, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_LOCK_CMP1_MODE1, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_LOCK_CMP2_MODE1, 0x41),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_DEC_START_MODE1, 0x41),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_DEC_START_MSB_MODE1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START1_MODE1, 0x55),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START2_MODE1, 0x75),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START3_MODE1, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_HSCLK_SEL_1, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_VCO_TUNE1_MODE1, 0x25),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_VCO_TUNE2_MODE1, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_STEP_SIZE1_MODE0, 0xc0),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_STEP_SIZE2_MODE0, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_CP_CTRL_MODE0, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_PLL_RCTRL_MODE0, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_PLL_CCTRL_MODE0, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_LOCK_CMP1_MODE0, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_LOCK_CMP2_MODE0, 0x1a),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_DEC_START_MODE0, 0x41),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_DEC_START_MSB_MODE0, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START1_MODE0, 0x55),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START2_MODE0, 0x75),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START3_MODE0, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_VCO_TUNE1_MODE0, 0x25),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_VCO_TUNE2_MODE0, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_BG_TIMER, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_EN_CENTER, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_PER1, 0x62),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_PER2, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_SYSCLK_BUF_ENABLE, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_SYSCLK_EN_SEL, 0x1a),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_LOCK_CMP_CFG, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_VCO_TUNE_MAP, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_CORE_CLK_EN, 0x20),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_CMN_CONFIG_1, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4a),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_AUTO_GAIN_ADJ_CTRL_3, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_ADDITIONAL_MISC, 0x0c),
+};
+
+static const struct qmp_phy_init_tbl hawi_usb3_tx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V10_TX_RES_CODE_LANE_TX, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V10_TX_RES_CODE_LANE_RX, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V10_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_V10_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_V10_TX_LANE_MODE_1, 0xe5),
+ QMP_PHY_INIT_CFG(QSERDES_V10_TX_LANE_MODE_2, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V10_TX_LANE_MODE_3, 0x11),
+ QMP_PHY_INIT_CFG(QSERDES_V10_TX_LANE_MODE_4, 0x31),
+ QMP_PHY_INIT_CFG(QSERDES_V10_TX_LANE_MODE_5, 0x5d),
+ QMP_PHY_INIT_CFG(QSERDES_V10_TX_RCV_DETECT_LVL_2, 0x12),
+ QMP_PHY_INIT_CFG_LANE(QSERDES_V10_TX_PI_QEC_CTRL, 0x21, 1),
+ QMP_PHY_INIT_CFG_LANE(QSERDES_V10_TX_PI_QEC_CTRL, 0x05, 2),
+};
+
+static const struct qmp_phy_init_tbl hawi_usb3_rx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_FO_GAIN, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_SO_GAIN, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_PI_CONTROLS, 0x99),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_SB2_THRESH1, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_SB2_THRESH2, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_SB2_GAIN1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_SB2_GAIN2, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_AUX_DATA_TCOARSE_TFINE, 0x20),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_VGA_CAL_CNTRL1, 0x54),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_VGA_CAL_CNTRL2, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_GM_CAL, 0x13),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_IDAC_TSETTLE_LOW, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
+
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_SIGDET_ENABLES, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_SIGDET_CNTRL, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_00_LOW, 0x3f),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_00_HIGH, 0xbf),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_00_HIGH2, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_00_HIGH3, 0xdf),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_00_HIGH4, 0xed),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_01_LOW, 0x19),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_01_HIGH, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_01_HIGH2, 0x91),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_01_HIGH3, 0xb7),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_01_HIGH4, 0xaa),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_DFE_EN_TIMER, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_DCC_CTRL1, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_VTH_CODE, 0x10),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_SIGDET_CAL_CTRL1, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_SIGDET_CAL_TRIM, 0x08),
+};
+
+static const struct qmp_phy_init_tbl hawi_usb3_pcs_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_LOCK_DETECT_CONFIG1, 0xc4),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_LOCK_DETECT_CONFIG2, 0x89),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_LOCK_DETECT_CONFIG3, 0x20),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_LOCK_DETECT_CONFIG6, 0x13),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_REFGEN_REQ_CONFIG1, 0x21),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_RX_SIGDET_LVL, 0x55),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_RX_CONFIG, 0x0a),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_ALIGN_DETECT_CONFIG1, 0x88),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_ALIGN_DETECT_CONFIG2, 0x13),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_PCS_TX_RX_CONFIG, 0x04),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_PCS_TX_RX_CONFIG2, 0x01),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_EQ_CONFIG1, 0x4b),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_EQ_CONFIG5, 0x10),
+};
+
+static const struct qmp_phy_init_tbl hawi_usb3_pcs_usb_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
+};
+
/* list of regulators */
static struct regulator_bulk_data qmp_phy_vreg_l[] = {
{ .supply = "vdda-phy", .init_load_uA = 21800, },
@@ -2198,6 +2369,7 @@ struct qmp_combo_offsets {
u16 dp_txa;
u16 dp_txb;
u16 dp_dp_phy;
+ u16 aon_toggle;
};
struct qmp_phy_cfg {
@@ -2270,6 +2442,7 @@ struct qmp_combo {
const struct qmp_phy_cfg *cfg;
void __iomem *com;
+ void __iomem *aon_toggle;
void __iomem *serdes;
void __iomem *tx;
@@ -2416,6 +2589,24 @@ static const struct qmp_combo_offsets qmp_combo_offsets_v8 = {
.dp_dp_phy = 0x3c00,
};
+static const struct qmp_combo_offsets qmp_combo_offsets_v10 = {
+ .com = 0x0000,
+ .aon_toggle = 0x0400,
+ .txa = 0x1400,
+ .rxa = 0x1600,
+ .txb = 0x1800,
+ .rxb = 0x1a00,
+ .usb3_serdes = 0x1000,
+ .usb3_pcs_misc = 0x1c00,
+ .usb3_pcs = 0x1e00,
+ .usb3_pcs_aon = 0x2000,
+ .usb3_pcs_usb = 0x2100,
+ .dp_serdes = 0x3000,
+ .dp_txa = 0x3400,
+ .dp_txb = 0x3800,
+ .dp_dp_phy = 0x3c00,
+};
+
static const struct qmp_combo_offsets qmp_combo_usb43dp_offsets_v8 = {
.com = 0x0000,
.usb3_pcs_aon = 0x0100,
@@ -2705,6 +2896,27 @@ static const struct qmp_phy_cfg x1e80100_usb3dpphy_cfg = {
.regs = qmp_v6_n4_usb3phy_regs_layout,
};
+static const struct qmp_phy_cfg hawi_usb3dpphy_cfg = {
+ .offsets = &qmp_combo_offsets_v10,
+
+ .serdes_tbl = hawi_usb3_serdes_tbl,
+ .serdes_tbl_num = ARRAY_SIZE(hawi_usb3_serdes_tbl),
+ .tx_tbl = hawi_usb3_tx_tbl,
+ .tx_tbl_num = ARRAY_SIZE(hawi_usb3_tx_tbl),
+ .rx_tbl = hawi_usb3_rx_tbl,
+ .rx_tbl_num = ARRAY_SIZE(hawi_usb3_rx_tbl),
+ .pcs_tbl = hawi_usb3_pcs_tbl,
+ .pcs_tbl_num = ARRAY_SIZE(hawi_usb3_pcs_tbl),
+ .pcs_usb_tbl = hawi_usb3_pcs_usb_tbl,
+ .pcs_usb_tbl_num = ARRAY_SIZE(hawi_usb3_pcs_usb_tbl),
+
+ .regs = qmp_v10_usb3phy_regs_layout,
+ .reset_list = msm8996_usb3phy_reset_l,
+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+};
+
static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = {
.offsets = &qmp_combo_offsets_v3,
@@ -3662,13 +3874,18 @@ static int qmp_combo_com_init(struct qmp_combo *qmp, bool force)
{
const struct qmp_phy_cfg *cfg = qmp->cfg;
void __iomem *com = qmp->com;
- void __iomem *pcs_aon = qmp->pcs_aon;
+ void __iomem *aon_toggle;
int ret;
u32 val;
if (!force && qmp->init_count++)
return 0;
+ if (qmp->aon_toggle)
+ aon_toggle = qmp->aon_toggle;
+ else
+ aon_toggle = qmp->pcs_aon;
+
ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
if (ret) {
dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
@@ -3699,9 +3916,9 @@ static int qmp_combo_com_init(struct qmp_combo *qmp, bool force)
SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
/* override hardware control for reset of qmp phy */
- if (pcs_aon && cfg->regs[QPHY_AON_TOGGLE_ENABLE]) {
- qphy_clrbits(pcs_aon, cfg->regs[QPHY_AON_TOGGLE_ENABLE], 0x1);
- qphy_clrbits(pcs_aon, cfg->regs[QPHY_DP_AON_TOGGLE_ENABLE], 0x1);
+ if (aon_toggle && cfg->regs[QPHY_AON_TOGGLE_ENABLE]) {
+ qphy_clrbits(aon_toggle, cfg->regs[QPHY_AON_TOGGLE_ENABLE], 0x1);
+ qphy_clrbits(aon_toggle, cfg->regs[QPHY_DP_AON_TOGGLE_ENABLE], 0x1);
}
/* Use software based port select and switch on typec orientation */
@@ -4733,6 +4950,9 @@ static int qmp_combo_parse_dt(struct qmp_combo *qmp)
}
qmp->dp_dp_phy = base + offs->dp_dp_phy;
+ if (offs->aon_toggle)
+ qmp->aon_toggle = base + offs->aon_toggle;
+
ret = qmp_combo_clk_init(qmp);
if (ret)
return ret;
@@ -4986,6 +5206,10 @@ static const struct of_device_id qmp_combo_of_match_table[] = {
.compatible = "qcom,glymur-qmp-usb3-dp-phy",
.data = &glymur_usb3dpphy_cfg,
},
+ {
+ .compatible = "qcom,hawi-qmp-usb3-dp-phy",
+ .data = &hawi_usb3dpphy_cfg,
+ },
{
.compatible = "qcom,sar2130p-qmp-usb3-dp-phy",
.data = &sar2130p_usb3dpphy_cfg,
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v10.h b/drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v10.h
new file mode 100644
index 000000000000..6f3ea7d13556
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v10.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2026, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_DP_PHY_V10_H_
+#define QCOM_PHY_QMP_DP_PHY_V10_H_
+
+/* Only for QMP V10 PHY - DP PHY registers */
+
+#define QSERDES_V10_DP_PHY_VCO_DIV 0x070
+#define QSERDES_V10_DP_PHY_AUX_INTERRUPT_STATUS 0x0e0
+#define QSERDES_V10_DP_PHY_STATUS 0x0e4
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-aon-v10.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-aon-v10.h
new file mode 100644
index 000000000000..b858381bc238
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-aon-v10.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2026, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_AON_V10_H_
+#define QCOM_PHY_QMP_PCS_AON_V10_H_
+
+/* Only for QMP V10 PHY - PCS AON registers */
+
+#define QPHY_V10_PCS_AON_CLAMP_ENABLE 0x00
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v10.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v10.h
new file mode 100644
index 000000000000..0cc25e6acf58
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v10.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2026, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_USB_V10_H_
+#define QCOM_PHY_QMP_PCS_USB_V10_H_
+
+/* Only for QMP V10 PHY - USB PCS registers */
+
+#define QPHY_V10_PCS_USB3_POWER_STATE_CONFIG1 0x00
+#define QPHY_V10_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x08
+#define QPHY_V10_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x14
+#define QPHY_V10_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x18
+#define QPHY_V10_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x3c
+#define QPHY_V10_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40
+#define QPHY_V10_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x44
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10.h
new file mode 100644
index 000000000000..ac0fc434984b
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2026, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_V10_H_
+#define QCOM_PHY_QMP_PCS_V10_H_
+
+/* Only for QMP V10 PHY - PCS registers */
+
+#define QPHY_V10_PCS_SW_RESET 0x000
+#define QPHY_V10_PCS_PCS_STATUS1 0x014
+#define QPHY_V10_PCS_POWER_DOWN_CONTROL 0x040
+#define QPHY_V10_PCS_START_CONTROL 0x044
+#define QPHY_V10_PCS_POWER_STATE_CONFIG1 0x090
+#define QPHY_V10_PCS_LOCK_DETECT_CONFIG1 0x0c4
+#define QPHY_V10_PCS_LOCK_DETECT_CONFIG2 0x0c8
+#define QPHY_V10_PCS_LOCK_DETECT_CONFIG3 0x0cc
+#define QPHY_V10_PCS_LOCK_DETECT_CONFIG6 0x0d8
+#define QPHY_V10_PCS_REFGEN_REQ_CONFIG1 0x0dc
+#define QPHY_V10_PCS_RX_SIGDET_LVL 0x188
+#define QPHY_V10_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
+#define QPHY_V10_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
+#define QPHY_V10_PCS_RATE_SLEW_CNTRL1 0x198
+#define QPHY_V10_PCS_RX_CONFIG 0x1b0
+#define QPHY_V10_PCS_ALIGN_DETECT_CONFIG1 0x1c0
+#define QPHY_V10_PCS_ALIGN_DETECT_CONFIG2 0x1c4
+#define QPHY_V10_PCS_PCS_TX_RX_CONFIG 0x1d0
+#define QPHY_V10_PCS_PCS_TX_RX_CONFIG2 0x1d4
+#define QPHY_V10_PCS_EQ_CONFIG1 0x1e0
+#define QPHY_V10_PCS_EQ_CONFIG2 0x1e4
+#define QPHY_V10_PCS_EQ_CONFIG5 0x1f0
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v10.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v10.h
new file mode 100644
index 000000000000..92fbde7c9c7c
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v10.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2026, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_COM_V10_H_
+#define QCOM_PHY_QMP_QSERDES_COM_V10_H_
+
+/* Only for QMP V10 PHY - QSERDES COM registers */
+
+#define QSERDES_V10_COM_SSC_STEP_SIZE1_MODE1 0x00
+#define QSERDES_V10_COM_SSC_STEP_SIZE2_MODE1 0x04
+#define QSERDES_V10_COM_CP_CTRL_MODE1 0x10
+#define QSERDES_V10_COM_PLL_RCTRL_MODE1 0x14
+#define QSERDES_V10_COM_PLL_CCTRL_MODE1 0x18
+#define QSERDES_V10_COM_CORECLK_DIV_MODE1 0x1c
+#define QSERDES_V10_COM_LOCK_CMP1_MODE1 0x20
+#define QSERDES_V10_COM_LOCK_CMP2_MODE1 0x24
+#define QSERDES_V10_COM_DEC_START_MODE1 0x28
+#define QSERDES_V10_COM_DEC_START_MSB_MODE1 0x2c
+#define QSERDES_V10_COM_DIV_FRAC_START1_MODE1 0x30
+#define QSERDES_V10_COM_DIV_FRAC_START2_MODE1 0x34
+#define QSERDES_V10_COM_DIV_FRAC_START3_MODE1 0x38
+#define QSERDES_V10_COM_HSCLK_SEL_1 0x3c
+#define QSERDES_V10_COM_INTEGLOOP_GAIN0_MODE1 0x40
+#define QSERDES_V10_COM_INTEGLOOP_GAIN1_MODE1 0x44
+#define QSERDES_V10_COM_VCO_TUNE1_MODE1 0x48
+#define QSERDES_V10_COM_VCO_TUNE2_MODE1 0x4c
+#define QSERDES_V10_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x50
+#define QSERDES_V10_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x54
+#define QSERDES_V10_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x58
+#define QSERDES_V10_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x5c
+#define QSERDES_V10_COM_SSC_STEP_SIZE1_MODE0 0x60
+#define QSERDES_V10_COM_SSC_STEP_SIZE2_MODE0 0x64
+#define QSERDES_V10_COM_CP_CTRL_MODE0 0x70
+#define QSERDES_V10_COM_PLL_RCTRL_MODE0 0x74
+#define QSERDES_V10_COM_PLL_CCTRL_MODE0 0x78
+#define QSERDES_V10_COM_PLL_CORE_CLK_DIV_MODE0 0x7c
+#define QSERDES_V10_COM_LOCK_CMP1_MODE0 0x80
+#define QSERDES_V10_COM_LOCK_CMP2_MODE0 0x84
+#define QSERDES_V10_COM_DEC_START_MODE0 0x88
+#define QSERDES_V10_COM_DEC_START_MSB_MODE0 0x8c
+#define QSERDES_V10_COM_DIV_FRAC_START1_MODE0 0x90
+#define QSERDES_V10_COM_DIV_FRAC_START2_MODE0 0x94
+#define QSERDES_V10_COM_DIV_FRAC_START3_MODE0 0x98
+#define QSERDES_V10_COM_HSCLK_HS_SWITCH_SEL_1 0x9c
+#define QSERDES_V10_COM_INTEGLOOP_GAIN0_MODE0 0xa0
+#define QSERDES_V10_COM_INTEGLOOP_GAIN1_MODE0 0xa4
+#define QSERDES_V10_COM_VCO_TUNE1_MODE0 0xa8
+#define QSERDES_V10_COM_VCO_TUNE2_MODE0 0xac
+#define QSERDES_V10_COM_BG_TIMER 0xbc
+#define QSERDES_V10_COM_SSC_EN_CENTER 0xc0
+#define QSERDES_V10_COM_SSC_ADJ_PER1 0xc4
+#define QSERDES_V10_COM_SSC_PER1 0xcc
+#define QSERDES_V10_COM_SSC_PER2 0xd0
+#define QSERDES_V10_COM_POST_DIV_MUX 0xd8
+#define QSERDES_V10_COM_BIAS_EN_CLKBUFLR_EN 0xdc
+#define QSERDES_V10_COM_CLK_ENABLE1 0xe0
+#define QSERDES_V10_COM_SYS_CLK_CTRL 0xe4
+#define QSERDES_V10_COM_SYSCLK_BUF_ENABLE 0xe8
+#define QSERDES_V10_COM_PLL_IVCO 0xf4
+#define QSERDES_V10_COM_PLL_IVCO_MODE1 0xf8
+#define QSERDES_V10_COM_CMN_IETRIM 0xfc
+#define QSERDES_V10_COM_CMN_IPTRIM 0x100
+#define QSERDES_V10_COM_SYSCLK_EN_SEL 0x110
+#define QSERDES_V10_COM_RESETSM_CNTRL 0x118
+#define QSERDES_V10_COM_LOCK_CMP_EN 0x120
+#define QSERDES_V10_COM_LOCK_CMP_CFG 0x124
+#define QSERDES_V10_COM_VCO_TUNE_CTRL 0x13c
+#define QSERDES_V10_COM_VCO_TUNE_MAP 0x140
+#define QSERDES_V10_COM_VCO_TUNE_INITVAL2 0x148
+#define QSERDES_V10_COM_VCO_TUNE_MAXVAL2 0x158
+#define QSERDES_V10_COM_CLK_SELECT 0x164
+#define QSERDES_V10_COM_CORE_CLK_EN 0x170
+#define QSERDES_V10_COM_CMN_CONFIG_1 0x174
+#define QSERDES_V10_COM_SVS_MODE_CLK_SEL 0x17c
+#define QSERDES_V10_COM_CMN_MISC_1 0x184
+#define QSERDES_V10_COM_CMN_MODE 0x188
+#define QSERDES_V10_COM_PLL_VCO_DC_LEVEL_CTRL 0x198
+#define QSERDES_V10_COM_AUTO_GAIN_ADJ_CTRL_1 0x1a4
+#define QSERDES_V10_COM_AUTO_GAIN_ADJ_CTRL_2 0x1a8
+#define QSERDES_V10_COM_AUTO_GAIN_ADJ_CTRL_3 0x1ac
+#define QSERDES_V10_COM_ADDITIONAL_MISC 0x1b4
+#define QSERDES_V10_COM_ADDITIONAL_MISC_2 0x1b8
+#define QSERDES_V10_COM_ADDITIONAL_MISC_3 0x1bc
+#define QSERDES_V10_COM_CMN_STATUS 0x2c8
+#define QSERDES_V10_COM_C_READY_STATUS 0x2f0
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v10.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v10.h
new file mode 100644
index 000000000000..84f1adee5ff7
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v10.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2026, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V10_H_
+#define QCOM_PHY_QMP_QSERDES_TXRX_V10_H_
+
+/* Only for QMP V10 PHY - QSERDES TX/RX registers */
+
+/* TX registers */
+#define QSERDES_V10_TX_CLKBUF_ENABLE 0x08
+#define QSERDES_V10_TX_TX_EMP_POST1_LVL 0x0c
+#define QSERDES_V10_TX_TX_DRV_LVL 0x14
+#define QSERDES_V10_TX_RESET_TSYNC_EN 0x1c
+#define QSERDES_V10_TX_PRE_STALL_LDO_BOOST_EN 0x20
+#define QSERDES_V10_TX_TX_BAND 0x24
+#define QSERDES_V10_TX_INTERFACE_SELECT 0x2c
+#define QSERDES_V10_TX_RES_CODE_LANE_TX 0x34
+#define QSERDES_V10_TX_RES_CODE_LANE_RX 0x38
+#define QSERDES_V10_TX_RES_CODE_LANE_OFFSET_TX 0x3c
+#define QSERDES_V10_TX_RES_CODE_LANE_OFFSET_RX 0x40
+#define QSERDES_V10_TX_TRANSCEIVER_BIAS_EN 0x54
+#define QSERDES_V10_TX_HIGHZ_DRVR_EN 0x58
+#define QSERDES_V10_TX_TX_POL_INV 0x5c
+#define QSERDES_V10_TX_PARRATE_REC_DETECT_IDLE_EN 0x60
+#define QSERDES_V10_TX_BIST_PATTERN7 0x7c
+#define QSERDES_V10_TX_LANE_MODE_1 0x84
+#define QSERDES_V10_TX_LANE_MODE_2 0x88
+#define QSERDES_V10_TX_LANE_MODE_3 0x8c
+#define QSERDES_V10_TX_LANE_MODE_4 0x90
+#define QSERDES_V10_TX_LANE_MODE_5 0x94
+#define QSERDES_V10_TX_RCV_DETECT_LVL_2 0xa4
+#define QSERDES_V10_TX_TRAN_DRVR_EMP_EN 0xc0
+#define QSERDES_V10_TX_TX_INTERFACE_MODE 0xc4
+#define QSERDES_V10_TX_VMODE_CTRL1 0xc8
+#define QSERDES_V10_TX_PI_QEC_CTRL 0xe4
+
+/* RX registers */
+#define QSERDES_V10_RX_UCDR_FO_GAIN 0x08
+#define QSERDES_V10_RX_UCDR_SO_GAIN 0x14
+#define QSERDES_V10_RX_UCDR_FASTLOCK_FO_GAIN 0x30
+#define QSERDES_V10_RX_UCDR_SO_SATURATION_AND_ENABLE 0x34
+#define QSERDES_V10_RX_UCDR_FASTLOCK_COUNT_LOW 0x3c
+#define QSERDES_V10_RX_UCDR_FASTLOCK_COUNT_HIGH 0x40
+#define QSERDES_V10_RX_UCDR_PI_CONTROLS 0x44
+#define QSERDES_V10_RX_UCDR_SB2_THRESH1 0x4c
+#define QSERDES_V10_RX_UCDR_SB2_THRESH2 0x50
+#define QSERDES_V10_RX_UCDR_SB2_GAIN1 0x54
+#define QSERDES_V10_RX_UCDR_SB2_GAIN2 0x58
+#define QSERDES_V10_RX_AUX_DATA_TCOARSE_TFINE 0x60
+#define QSERDES_V10_RX_TX_ADAPT_POST_THRESH 0xcc
+#define QSERDES_V10_RX_VGA_CAL_CNTRL1 0xd4
+#define QSERDES_V10_RX_VGA_CAL_CNTRL2 0xd8
+#define QSERDES_V10_RX_GM_CAL 0xdc
+#define QSERDES_V10_RX_RX_EQU_ADAPTOR_CNTRL2 0xec
+#define QSERDES_V10_RX_RX_EQU_ADAPTOR_CNTRL3 0xf0
+#define QSERDES_V10_RX_RX_EQU_ADAPTOR_CNTRL4 0xf4
+#define QSERDES_V10_RX_RX_IDAC_TSETTLE_LOW 0xf8
+#define QSERDES_V10_RX_RX_IDAC_TSETTLE_HIGH 0xfc
+#define QSERDES_V10_RX_RX_IDAC_ENABLES 0x100
+#define QSERDES_V10_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x104
+#define QSERDES_V10_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
+#define QSERDES_V10_RX_SIGDET_ENABLES 0x118
+#define QSERDES_V10_RX_SIGDET_CNTRL 0x11c
+#define QSERDES_V10_RX_SIGDET_DEGLITCH_CNTRL 0x124
+#define QSERDES_V10_RX_RX_MODE_00_LOW 0x15c
+#define QSERDES_V10_RX_RX_MODE_00_HIGH 0x160
+#define QSERDES_V10_RX_RX_MODE_00_HIGH2 0x164
+#define QSERDES_V10_RX_RX_MODE_00_HIGH3 0x168
+#define QSERDES_V10_RX_RX_MODE_00_HIGH4 0x16c
+#define QSERDES_V10_RX_RX_MODE_01_LOW 0x170
+#define QSERDES_V10_RX_RX_MODE_01_HIGH 0x174
+#define QSERDES_V10_RX_RX_MODE_01_HIGH2 0x178
+#define QSERDES_V10_RX_RX_MODE_01_HIGH3 0x17c
+#define QSERDES_V10_RX_RX_MODE_01_HIGH4 0x180
+#define QSERDES_V10_RX_RX_MODE_10_LOW 0x184
+#define QSERDES_V10_RX_RX_MODE_10_HIGH 0x188
+#define QSERDES_V10_RX_RX_MODE_10_HIGH2 0x18c
+#define QSERDES_V10_RX_RX_MODE_10_HIGH3 0x190
+#define QSERDES_V10_RX_RX_MODE_10_HIGH4 0x194
+#define QSERDES_V10_RX_DFE_EN_TIMER 0x1a0
+#define QSERDES_V10_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4
+#define QSERDES_V10_RX_DCC_CTRL1 0x1a8
+#define QSERDES_V10_RX_VTH_CODE 0x1b0
+#define QSERDES_V10_RX_SIGDET_CAL_CTRL1 0x1e4
+#define QSERDES_V10_RX_SIGDET_CAL_TRIM 0x1f8
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index a873bdd7bffe..7af77572970e 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -39,6 +39,9 @@
#include "phy-qcom-qmp-qserdes-txrx-v8.h"
#include "phy-qcom-qmp-qserdes-lalb-v8.h"
+#include "phy-qcom-qmp-qserdes-com-v10.h"
+#include "phy-qcom-qmp-qserdes-txrx-v10.h"
+
#include "phy-qcom-qmp-qserdes-pll.h"
#include "phy-qcom-qmp-pcs-v2.h"
@@ -65,6 +68,8 @@
#include "phy-qcom-qmp-pcs-v8_50.h"
+#include "phy-qcom-qmp-pcs-v10.h"
+
/* QPHY_SW_RESET bit */
#define SW_RESET BIT(0)
/* QPHY_POWER_DOWN_CONTROL */
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH 3/4] dt-bindings: usb: qcom,snps-dwc3: Add Hawi compatible
From: Ronak Raheja @ 2026-04-25 7:00 UTC (permalink / raw)
To: vkoul, krzk+dt, conor+dt, robh, neil.armstrong, gregkh
Cc: dmitry.baryshkov, konrad.dybcio, abel.vesa, wesley.cheng,
ronak.raheja, linux-arm-msm, linux-phy, devicetree, linux-usb,
linux-kernel
In-Reply-To: <20260425070002.348733-1-ronak.raheja@oss.qualcomm.com>
Document the Synopsys DWC3 USB controller found on the Hawi platform.
Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
---
Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
index 8201656b41ed..2d10994f7b44 100644
--- a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
@@ -27,6 +27,7 @@ properties:
- qcom,eliza-dwc3
- qcom,glymur-dwc3
- qcom,glymur-dwc3-mp
+ - qcom,hawi-dwc3
- qcom,ipq4019-dwc3
- qcom,ipq5018-dwc3
- qcom,ipq5332-dwc3
@@ -203,6 +204,7 @@ allOf:
compatible:
contains:
enum:
+ - qcom,hawi-dwc3
- qcom,ipq5424-dwc3
- qcom,ipq9574-dwc3
- qcom,kaanapali-dwc3
@@ -540,6 +542,7 @@ allOf:
contains:
enum:
- qcom,eliza-dwc3
+ - qcom,hawi-dwc3
- qcom,ipq4019-dwc3
- qcom,ipq8064-dwc3
- qcom,kaanapali-dwc3
--
2.34.1
--
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* [PATCH 2/4] dt-bindings: phy: qcom,m31-eusb2-phy: Document M31 eUSB2 PHY for Hawi
From: Ronak Raheja @ 2026-04-25 7:00 UTC (permalink / raw)
To: vkoul, krzk+dt, conor+dt, robh, neil.armstrong, gregkh
Cc: dmitry.baryshkov, konrad.dybcio, abel.vesa, wesley.cheng,
ronak.raheja, linux-arm-msm, linux-phy, devicetree, linux-usb,
linux-kernel
In-Reply-To: <20260425070002.348733-1-ronak.raheja@oss.qualcomm.com>
Document the M31 eUSB2 PHY for Hawi which handles the USB2 path. Use
fallback to indicate the compatibility of the M31 eUSB2 PHY on the Hawi
with that on the SM8750.
Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
---
Documentation/devicetree/bindings/phy/qcom,m31-eusb2-phy.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,m31-eusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,m31-eusb2-phy.yaml
index cd6b84213a7c..c0e7e2963ce6 100644
--- a/Documentation/devicetree/bindings/phy/qcom,m31-eusb2-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,m31-eusb2-phy.yaml
@@ -19,6 +19,7 @@ properties:
- items:
- enum:
- qcom,glymur-m31-eusb2-phy
+ - qcom,hawi-m31-eusb2-phy
- qcom,kaanapali-m31-eusb2-phy
- const: qcom,sm8750-m31-eusb2-phy
- const: qcom,sm8750-m31-eusb2-phy
--
2.34.1
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* [PATCH 1/4] dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add Hawi QMP PHY
From: Ronak Raheja @ 2026-04-25 6:59 UTC (permalink / raw)
To: vkoul, krzk+dt, conor+dt, robh, neil.armstrong, gregkh
Cc: dmitry.baryshkov, konrad.dybcio, abel.vesa, wesley.cheng,
ronak.raheja, linux-arm-msm, linux-phy, devicetree, linux-usb,
linux-kernel
In-Reply-To: <20260425070002.348733-1-ronak.raheja@oss.qualcomm.com>
Document the Hawi compatible string for the QMP combo PHY.
Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
---
.../devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
index 3d537b7f9985..7a7059c659be 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
@@ -22,6 +22,7 @@ properties:
- const: qcom,sm8750-qmp-usb3-dp-phy
- enum:
- qcom,glymur-qmp-usb3-dp-phy
+ - qcom,hawi-qmp-usb3-dp-phy
- qcom,sar2130p-qmp-usb3-dp-phy
- qcom,sc7180-qmp-usb3-dp-phy
- qcom,sc7280-qmp-usb3-dp-phy
@@ -205,6 +206,7 @@ allOf:
contains:
enum:
- qcom,glymur-qmp-usb3-dp-phy
+ - qcom,hawi-qmp-usb3-dp-phy
- qcom,sar2130p-qmp-usb3-dp-phy
- qcom,sc8280xp-qmp-usb43dp-phy
- qcom,sm6350-qmp-usb3-dp-phy
--
2.34.1
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