* Re: [PATCH 1/4] dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add Hawi QMP PHY
From: Rob Herring (Arm) @ 2026-05-06 1:19 UTC (permalink / raw)
To: Ronak Raheja
Cc: linux-usb, dmitry.baryshkov, abel.vesa, krzysztof.kozlowski,
linux-kernel, vkoul, linux-phy, devicetree, gregkh, conor+dt,
konrad.dybcio, wesley.cheng, linux-arm-msm, krzk+dt,
neil.armstrong
In-Reply-To: <20260427214217.2735240-2-ronak.raheja@oss.qualcomm.com>
On Mon, 27 Apr 2026 14:42:14 -0700, Ronak Raheja wrote:
> Document the Hawi compatible string for the QMP combo PHY.
>
> Hawi uses a new QSERDES V10 register layout with a new COM AON module
> and hardware-specific PHY init sequences compared to previous targets,
> requiring a dedicated compatible string.
>
> Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
> ---
> .../devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
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^ permalink raw reply
* [PATCH v3 13/15] phy: mediatek: phy-mtk-hdmi-mt2701: use clk_determine_rate_noop()
From: Brian Masney @ 2026-05-06 0:49 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney
Cc: linux-clk, linux-kernel, Chun-Kuang Hu, Philipp Zabel,
Chunfeng Yun, Vinod Koul, Matthias Brugger,
AngeloGioacchino Del Regno, Neil Armstrong, dri-devel,
linux-mediatek, linux-arm-kernel, linux-phy
In-Reply-To: <20260505-clk-determine-rate-noop-v3-0-f3f829fbacdf@redhat.com>
Drop the driver-specific empty determine_rate() function and use the new
shared clk_determine_rate_noop() helper.
Signed-off-by: Brian Masney <bmasney@redhat.com>
---
To: Chun-Kuang Hu <chunkuang.hu@kernel.org>
To: Philipp Zabel <p.zabel@pengutronix.de>
To: Chunfeng Yun <chunfeng.yun@mediatek.com>
To: Vinod Koul <vkoul@kernel.org>
To: Matthias Brugger <matthias.bgg@gmail.com>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: Michael Turquette <mturquette@baylibre.com>
To: Stephen Boyd <sboyd@kernel.org>
To: Brian Masney <bmasney@redhat.com>
Cc: linux-clk@vger.kernel.org
Cc: Neil Armstrong <neil.armstrong@linaro.org>
Cc: dri-devel@lists.freedesktop.org
Cc: linux-mediatek@lists.infradead.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-phy@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c | 8 +-------
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c
index b0b6497e7eed..c9a1f20e939b 100644
--- a/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c
+++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c
@@ -90,12 +90,6 @@ static void mtk_hdmi_pll_unprepare(struct clk_hw *hw)
usleep_range(80, 100);
}
-static int mtk_hdmi_pll_determine_rate(struct clk_hw *hw,
- struct clk_rate_request *req)
-{
- return 0;
-}
-
static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
@@ -170,7 +164,7 @@ static const struct clk_ops mtk_hdmi_phy_pll_ops = {
.prepare = mtk_hdmi_pll_prepare,
.unprepare = mtk_hdmi_pll_unprepare,
.set_rate = mtk_hdmi_pll_set_rate,
- .determine_rate = mtk_hdmi_pll_determine_rate,
+ .determine_rate = clk_determine_rate_noop,
.recalc_rate = mtk_hdmi_pll_recalc_rate,
};
--
2.54.0
--
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^ permalink raw reply related
* [PATCH v3 02/15] clk: add clk_determine_rate_noop()
From: Brian Masney @ 2026-05-06 0:48 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney
Cc: linux-clk, linux-kernel, Abel Vesa, Peng Fan, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, Anson Huang,
Bjorn Andersson, Geert Uytterhoeven, Andrea della Porta,
Tudor Ambarus, Krzysztof Kozlowski, Sylwester Nawrocki,
Chanwoo Choi, Alim Akhtar, Sudeep Holla, Cristian Marussi,
Orson Zhai, Baolin Wang, Chunyan Zhang, Chun-Kuang Hu,
Philipp Zabel, Chunfeng Yun, Vinod Koul, Neil Armstrong,
Matthias Brugger, AngeloGioacchino Del Regno, Ulf Hansson, imx,
linux-arm-kernel, linux-arm-msm, linux-renesas-soc,
linux-samsung-soc, arm-scmi, dri-devel, linux-mediatek, linux-phy,
linux-pm
In-Reply-To: <20260505-clk-determine-rate-noop-v3-0-f3f829fbacdf@redhat.com>
Add a new helper clk_determine_rate_noop() that's for clocks where the
rate rounding is handled by the firmware/hardware, or the clock is
capable of any rate. The requested rate is passed through unchanged,
and the actual rate will be learned via recalc_rate() after the rate
is set.
This shared helper will be used to get rid of the driver-specific empty
determine rate implementations that are present in the tree.
Signed-off-by: Brian Masney <bmasney@redhat.com>
---
To: Michael Turquette <mturquette@baylibre.com>
To: Stephen Boyd <sboyd@kernel.org>
To: Brian Masney <bmasney@redhat.com>
To: Abel Vesa <abelvesa@kernel.org>
To: Peng Fan <peng.fan@nxp.com>
To: Frank Li <Frank.Li@nxp.com>
To: Sascha Hauer <s.hauer@pengutronix.de>
To: Pengutronix Kernel Team <kernel@pengutronix.de>
To: Fabio Estevam <festevam@gmail.com>
To: Anson Huang <anson.huang@nxp.com>
To: Bjorn Andersson <andersson@kernel.org>
To: Geert Uytterhoeven <geert+renesas@glider.be>
To: Andrea della Porta <andrea.porta@suse.com>
To: Tudor Ambarus <tudor.ambarus@linaro.org>
To: Krzysztof Kozlowski <krzk@kernel.org>
To: Sylwester Nawrocki <s.nawrocki@samsung.com>
To: Chanwoo Choi <cw00.choi@samsung.com>
To: Alim Akhtar <alim.akhtar@samsung.com>
To: Sudeep Holla <sudeep.holla@kernel.org>
To: Cristian Marussi <cristian.marussi@arm.com>
To: Orson Zhai <orsonzhai@gmail.com>
To: Baolin Wang <baolin.wang@linux.alibaba.com>
To: Chunyan Zhang <zhang.lyra@gmail.com>
To: Chun-Kuang Hu <chunkuang.hu@kernel.org>
To: Philipp Zabel <p.zabel@pengutronix.de>
To: Chunfeng Yun <chunfeng.yun@mediatek.com>
To: Vinod Koul <vkoul@kernel.org>
To: Neil Armstrong <neil.armstrong@linaro.org>
To: Matthias Brugger <matthias.bgg@gmail.com>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: Ulf Hansson <ulfh@kernel.org>
Cc: linux-clk@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: imx@lists.linux.dev
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-renesas-soc@vger.kernel.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: arm-scmi@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Cc: linux-mediatek@lists.infradead.org
Cc: linux-phy@lists.infradead.org
Cc: linux-pm@vger.kernel.org
---
drivers/clk/clk.c | 18 ++++++++++++++++++
include/linux/clk-provider.h | 1 +
2 files changed, 19 insertions(+)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 048adfa86a5d..956e147f4d4e 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -882,6 +882,24 @@ int clk_hw_determine_rate_no_reparent(struct clk_hw *hw,
}
EXPORT_SYMBOL_GPL(clk_hw_determine_rate_no_reparent);
+/**
+ * clk_determine_rate_noop - clk_ops::determine_rate noop implementation
+ * @hw: clk to determine rate on
+ * @req: rate request
+ *
+ * Noop determine rate for clocks where the rate rounding is handled by the
+ * firmware/hardware, or the clock is capable of any rate. The requested rate is
+ * passed through unchanged, and the actual rate will be learned via
+ * recalc_rate() after the rate is set.
+ *
+ * Returns: 0 always
+ */
+int clk_determine_rate_noop(struct clk_hw *hw, struct clk_rate_request *req)
+{
+ return 0;
+}
+EXPORT_SYMBOL_GPL(clk_determine_rate_noop);
+
/*** clk api ***/
static void clk_core_rate_unprotect(struct clk_core *core)
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index b01a38fef8cf..334b9211a157 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -1431,6 +1431,7 @@ int clk_mux_determine_rate_flags(struct clk_hw *hw,
unsigned long flags);
int clk_hw_determine_rate_no_reparent(struct clk_hw *hw,
struct clk_rate_request *req);
+int clk_determine_rate_noop(struct clk_hw *hw, struct clk_rate_request *req);
void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
void clk_hw_get_rate_range(struct clk_hw *hw, unsigned long *min_rate,
unsigned long *max_rate);
--
2.54.0
--
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^ permalink raw reply related
* [PATCH v3 00/15] clk: introduce clk_determine_rate_noop() and update drivers to use it
From: Brian Masney @ 2026-05-06 0:48 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney
Cc: linux-clk, linux-kernel, Peng Fan, Abel Vesa, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, imx,
linux-arm-kernel, Anson Huang, Bjorn Andersson,
Geert Uytterhoeven, Andrea della Porta, Tudor Ambarus,
Krzysztof Kozlowski, Sylwester Nawrocki, Chanwoo Choi,
Alim Akhtar, Sudeep Holla, Cristian Marussi, Orson Zhai,
Baolin Wang, Chunyan Zhang, Chun-Kuang Hu, Philipp Zabel,
Chunfeng Yun, Vinod Koul, Neil Armstrong, Matthias Brugger,
AngeloGioacchino Del Regno, Ulf Hansson, linux-arm-msm,
linux-renesas-soc, linux-samsung-soc, arm-scmi, dri-devel,
linux-mediatek, linux-phy, linux-pm
There are some clocks where the determine_rate clk op is just an empty
function that returns 0. This can be either because the rounding is
managed by the firmware/hardware, or the clock is capable of any rate.
Let's add a new new shared function to clk.c named
clk_determine_rate_noop(), and update all of the drivers that have an
empty determine_rate() ops to use this new shared function.
The first patch in this series also includes a minor cleanup to
drivers/clk/imx/clk-scu.c. I included it as the first patch so it
doesn't get buried in the middle of this series. I change this same
driver later in the series to use clk_determine_rate_noop().
Changes since v2:
https://lore.kernel.org/all/20260309-clk-det-rate-fw-managed-v2-0-c48ef5a3100a@redhat.com/
- Dropped the NOOP flag and just use a dedicated noop function.
Merge Strategy
--------------
All of this needs to be directly merged by Stephen as one series into
his tree. Subsystem maintainers: please leave a Reviewed-by or Acked-by
for Stephen. To reduce the noise, I am only CCing people on their
respective drivers.
Since there's only 3 drivers outside of drivers/clk that need to be
updated, I included them in this same series for completeness. These
should go through Stephen's tree as well.
Signed-off-by: Brian Masney <bmasney@redhat.com>
---
Brian Masney (15):
clk: imx: scu: drop redundant init.ops variable assignment
clk: add clk_determine_rate_noop()
clk: hisilicon: hi3660-stub: use clk_determine_rate_noop()
clk: imx: scu: use clk_determine_rate_noop()
clk: qcom: rpm: use clk_determine_rate_noop()
clk: qcom: rpmh: use clk_determine_rate_noop()
clk: qcom: smd-rpm: use clk_determine_rate_noop()
clk: renesas: rzg2l-cpg: use clk_determine_rate_noop()
clk: rp1: use clk_determine_rate_noop()
clk: samsung: acpm: use clk_determine_rate_noop()
clk: scpi: use clk_determine_rate_noop()
clk: sprd: use clk_determine_rate_noop()
phy: mediatek: phy-mtk-hdmi-mt2701: use clk_determine_rate_noop()
pmdomain: mediatek: airoha: use clk_determine_rate_noop()
pmdomain: mediatek: mtk-mfg: use clk_determine_rate_noop()
drivers/clk/clk-rp1.c | 8 +-------
drivers/clk/clk-scpi.c | 14 +-------------
drivers/clk/clk.c | 18 ++++++++++++++++++
drivers/clk/hisilicon/clk-hi3660-stub.c | 12 +-----------
drivers/clk/imx/clk-scu.c | 24 +++---------------------
drivers/clk/qcom/clk-rpm.c | 15 ++-------------
drivers/clk/qcom/clk-rpmh.c | 8 +-------
drivers/clk/qcom/clk-smd-rpm.c | 13 +------------
drivers/clk/renesas/rzg2l-cpg.c | 8 +-------
drivers/clk/samsung/clk-acpm.c | 14 +-------------
drivers/clk/sprd/pll.c | 8 +-------
drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c | 8 +-------
drivers/pmdomain/mediatek/airoha-cpu-pmdomain.c | 8 +-------
drivers/pmdomain/mediatek/mtk-mfg-pmdomain.c | 23 ++---------------------
include/linux/clk-provider.h | 1 +
15 files changed, 36 insertions(+), 146 deletions(-)
---
base-commit: 4cd074ae20bbcc293bbbce9163abe99d68ae6ae0
change-id: 20260505-clk-determine-rate-noop-17a544f78018
Best regards,
--
Brian Masney <bmasney@redhat.com>
--
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^ permalink raw reply
* Re: [PATCH v5 5/6] phy: realtek: usb2: add support for RTL9607C USB2 PHY
From: Vladimir Oltean @ 2026-05-05 19:25 UTC (permalink / raw)
To: Rustam Adilov
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stanley Chang, linux-phy, devicetree, linux-kernel,
Michael Zavertkin
In-Reply-To: <9de0dcc209eab02d2a4e5fcec25e7711@disroot.org>
On Tue, May 05, 2026 at 06:10:42PM +0000, Rustam Adilov wrote:
> On 2026-05-05 11:30, Vladimir Oltean wrote:
> > On Tue, Apr 21, 2026 at 12:19:40AM +0500, Rustam Adilov wrote:
> >> Add support for the usb2 phy of RTL9607C series based SoCs.
> >> Add the macros and phy config struct for rtl9607.
> >>
> >> RTL9607C requires to clear a "force host disconnect" bit in the
> >> specific register (which is at an offset from reg_wrap_vstatus)
> >> before proceeding with phy parameter writes. Since it belongs into
> >> the vstatus register region, it doesn't need bytes swapping.
> >>
> >> Add the bool variable to the driver data struct and hide this whole
> >> procedure under the if statement that checks this new variable.
> >>
> >> Add the appropriate little endian read and write functions for rtl9607
> >> and assign them to its phy config struct.
> >>
> >> As mentioned earlier, the readl/writel are native endian on MIPS arch
> >> if SWAP_IO_SPACE is not enabled. Since enabling SWAP_IO_SPACE results
> >> in boot hang on RTL9607C machine, wrapping le32 around readl/writel
> >> should be a good compromise, but swab32 could be also work.
> >>
> >> Co-developed-by: Michael Zavertkin <misha.zavertkin@mail.ru>
> >> Signed-off-by: Michael Zavertkin <misha.zavertkin@mail.ru>
> >> Signed-off-by: Rustam Adilov <adilov@disroot.org>
> >> ---
> >
> > Have you considered ioread32() instead of wrapping le32 around readl()?
>
> I think you meant ioread32be() and yes i have considered it. If this is what
> it takes to get rid of le32 warning you mentioned from an earlier email then
> so be it.
No, I meant ioread32(). When I read Documentation/driver-api/device-io.rst,
it says ioread32() is for a little endian peripheral and ioread32be()
for big endian peripherals. You have a little endian peripheral (relevant)
and a big endian CPU (not relevant) so I don't see why ioread32() wouldn't
be the correct accessor to use.
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^ permalink raw reply
* Re: [PATCH v5 0/6] phy: realtek: usb2: support for RTL9607C USB2 PHY
From: Rustam Adilov @ 2026-05-05 18:39 UTC (permalink / raw)
To: Vladimir Oltean
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stanley Chang, linux-phy, devicetree, linux-kernel
In-Reply-To: <20260505113721.ur4qd4udu7jas473@skbuf>
On 2026-05-05 11:37, Vladimir Oltean wrote:
> On Tue, Apr 21, 2026 at 12:19:35AM +0500, Rustam Adilov wrote:
>> This patch series for Realtek USB2 PHY driver adds support for RTL9607C
>> USB2 PHY.
>>
>> RTL9607C is a big endian MIPS CPU which is quite far from RTD series SoCs
>> supported by realtek usb2 phy driver, but the phy initilization is found
>> to be very indentical in most areas.
>>
>> Most of the code was based on the Realtek's usb driver from the GPL tarball
>> in [1] and adjusted to fit into the realtek usb2 phy driver code format.
>>
>> The patch series was split into smaller patches that add/change something
>> in the driver that are not exactly related to RTL9607C and that also
>> helps for easier review. That also means, patch 5 depends on all the prior
>> patches that come before it.
>>
>> USB2 PHY on RTL9607C is primarly used for its internal OHCI/EHCI controllers.
>>
>> [1] - https://github.com/jameywine/GPL-for-GP3000/blob/main/linux-5.10.x/arch/mips/rtl9607c/usb.c
>>
>> ---
>
> Could you go through Patchwork and reply inline to the issues found,
> stating whether you are or are not going to resolve them?
> https://patchwork.kernel.org/project/linux-phy/list/?series=1083475
Yeah, sure thing. However i do expect a good bit of refactoring of this patch series
once we get SWAP_IO_SPACE working. It just turned out that some of the realtek drivers
from various subsystems use readl/ioread32 for native endian (which is big endian for
rtl9607c and others under MACH_REALTEK_RTL) and enabling SWAP_IO_SPACE makes them
function in little endian which breaks those things. So that's what we are dealing with
at this moment.
> All of the WARNING: line length of XX exceeds 80 columns
I can resolve them just fine.
> WARNING: msleep < 20ms can sleep for up to 20ms; see function description of msleep().
> #88: FILE: drivers/phy/realtek/phy-rtk-usb2.c:629:
> + msleep(10);
I can resolve it by changing it to usleep_range like i did with reset controller one.
> ../drivers/phy/realtek/phy-rtk-usb2.c:158:16: warning: cast to restricted __le32
> ../drivers/phy/realtek/phy-rtk-usb2.c:163:19: warning: incorrect type in initializer (different base types)
> ../drivers/phy/realtek/phy-rtk-usb2.c:163:19: expected unsigned int [usertype] tmp
> ../drivers/phy/realtek/phy-rtk-usb2.c:163:19: got restricted __le32 [usertype]
That should be fixed by using ioread32be.
> 1 maintainers not CCed: p.zabel@pengutronix.de
When i run scripts/get_maintainer.pl, it doesn't print it out at all but I can include it.
> Detected inline keyword in C files
> +static inline int utmi_wait_register(u32 (*read)(void __iomem *reg), void __iomem *reg, u32 mask,
Even though it was not introduced by this patch series, i think it is relevant as
i am directly modifying its property to include read function to it. Something along
like "While we are here, remove inline from utmi_wait_register"
I believe that is every issue from Checks list apart from Sashiko reviews.
Best,
Rustam
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^ permalink raw reply
* Re: [PATCH v5 5/6] phy: realtek: usb2: add support for RTL9607C USB2 PHY
From: Rustam Adilov @ 2026-05-05 18:10 UTC (permalink / raw)
To: Vladimir Oltean
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stanley Chang, linux-phy, devicetree, linux-kernel,
Michael Zavertkin
In-Reply-To: <20260505113001.idgj7ssikjgcypa2@skbuf>
On 2026-05-05 11:30, Vladimir Oltean wrote:
> On Tue, Apr 21, 2026 at 12:19:40AM +0500, Rustam Adilov wrote:
>> Add support for the usb2 phy of RTL9607C series based SoCs.
>> Add the macros and phy config struct for rtl9607.
>>
>> RTL9607C requires to clear a "force host disconnect" bit in the
>> specific register (which is at an offset from reg_wrap_vstatus)
>> before proceeding with phy parameter writes. Since it belongs into
>> the vstatus register region, it doesn't need bytes swapping.
>>
>> Add the bool variable to the driver data struct and hide this whole
>> procedure under the if statement that checks this new variable.
>>
>> Add the appropriate little endian read and write functions for rtl9607
>> and assign them to its phy config struct.
>>
>> As mentioned earlier, the readl/writel are native endian on MIPS arch
>> if SWAP_IO_SPACE is not enabled. Since enabling SWAP_IO_SPACE results
>> in boot hang on RTL9607C machine, wrapping le32 around readl/writel
>> should be a good compromise, but swab32 could be also work.
>>
>> Co-developed-by: Michael Zavertkin <misha.zavertkin@mail.ru>
>> Signed-off-by: Michael Zavertkin <misha.zavertkin@mail.ru>
>> Signed-off-by: Rustam Adilov <adilov@disroot.org>
>> ---
>
> Have you considered ioread32() instead of wrapping le32 around readl()?
I think you meant ioread32be() and yes i have considered it. If this is what
it takes to get rid of le32 warning you mentioned from an earlier email then
so be it.
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^ permalink raw reply
* [PATCH v2 3/5] dt-bindings: phy: rockchip,inno-usb2phy: Add compatible for RK3528
From: Heiko Stuebner @ 2026-05-05 17:04 UTC (permalink / raw)
To: vkoul
Cc: neil.armstrong, robh, krzk+dt, conor+dt, heiko, linux-phy,
devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, jonas
In-Reply-To: <20260505170410.3265305-1-heiko@sntech.de>
From: Jonas Karlman <jonas@kwiboo.se>
The embedded USB2 PHY on RK3528 is very similar to the one in RK3568,
the main difference being that it only uses two clocks instead of three.
Add compatible to support the USB2 PHY in RK3528.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
.../bindings/phy/rockchip,inno-usb2phy.yaml | 30 ++++++++++++++++---
1 file changed, 26 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml
index b95c9e3e44fe..f50fc69fbbe4 100644
--- a/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml
+++ b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml
@@ -20,6 +20,7 @@ properties:
- rockchip,rk3328-usb2phy
- rockchip,rk3366-usb2phy
- rockchip,rk3399-usb2phy
+ - rockchip,rk3528-usb2phy
- rockchip,rk3562-usb2phy
- rockchip,rk3568-usb2phy
- rockchip,rk3576-usb2phy
@@ -41,11 +42,15 @@ properties:
maxItems: 3
clock-names:
- minItems: 1
- items:
+ oneOf:
- const: phyclk
- - const: aclk
- - const: aclk_slv
+ - items:
+ - const: phyclk
+ - const: pclk
+ - items:
+ - const: phyclk
+ - const: aclk
+ - const: aclk_slv
assigned-clocks:
description:
@@ -65,6 +70,9 @@ properties:
description: Muxed interrupt for both ports
maxItems: 1
+ power-domains:
+ maxItems: 1
+
resets:
maxItems: 2
@@ -150,6 +158,7 @@ allOf:
compatible:
contains:
enum:
+ - rockchip,rk3528-usb2phy
- rockchip,rk3568-usb2phy
- rockchip,rv1108-usb2phy
then:
@@ -218,6 +227,19 @@ allOf:
clock-names:
maxItems: 1
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - rockchip,rk3528-usb2phy
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ clock-names:
+ minItems: 2
+
- if:
properties:
compatible:
--
2.47.3
--
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH v2 2/5] phy: rockchip: inno-usb2: Simplify rockchip,usbgrf handling
From: Heiko Stuebner @ 2026-05-05 17:04 UTC (permalink / raw)
To: vkoul
Cc: neil.armstrong, robh, krzk+dt, conor+dt, heiko, linux-phy,
devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, jonas
In-Reply-To: <20260505170410.3265305-1-heiko@sntech.de>
From: Jonas Karlman <jonas@kwiboo.se>
The logic to decide if usbgrf or grf should be used is more complex than
it needs to be. For RK3568, RV1108 and soon RK3528 we can assign the
rockchip,usbgrf regmap directly to grf instead of doing a usbgrf and grf
dance.
Simplify the code to only use the grf regmap and handle the logic of
what regmap should be used in driver probe instead.
The only expected change from this is that RK3528 can be supported
because of an addition of a of_property_present() check.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 68 +++++--------------
1 file changed, 18 insertions(+), 50 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index 8f4c08e599aa..7cec45192393 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -228,7 +228,6 @@ struct rockchip_usb2phy_port {
* struct rockchip_usb2phy - usb2.0 phy driver data.
* @dev: pointer to device.
* @grf: General Register Files regmap.
- * @usbgrf: USB General Register Files regmap.
* @clks: array of phy input clocks.
* @clk480m: clock struct of phy output clk.
* @clk480m_hw: clock struct of phy output clk management.
@@ -246,7 +245,6 @@ struct rockchip_usb2phy_port {
struct rockchip_usb2phy {
struct device *dev;
struct regmap *grf;
- struct regmap *usbgrf;
struct clk_bulk_data *clks;
struct clk *clk480m;
struct clk_hw clk480m_hw;
@@ -261,11 +259,6 @@ struct rockchip_usb2phy {
struct rockchip_usb2phy_port ports[USB2PHY_NUM_PORTS];
};
-static inline struct regmap *get_reg_base(struct rockchip_usb2phy *rphy)
-{
- return rphy->usbgrf == NULL ? rphy->grf : rphy->usbgrf;
-}
-
static inline int property_enable(struct regmap *base,
const struct usb2phy_reg *reg, bool en)
{
@@ -323,12 +316,11 @@ static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
{
struct rockchip_usb2phy *rphy =
container_of(hw, struct rockchip_usb2phy, clk480m_hw);
- struct regmap *base = get_reg_base(rphy);
int ret;
/* turn on 480m clk output if it is off */
- if (!property_enabled(base, &rphy->phy_cfg->clkout_ctl)) {
- ret = property_enable(base, &rphy->phy_cfg->clkout_ctl, true);
+ if (!property_enabled(rphy->grf, &rphy->phy_cfg->clkout_ctl)) {
+ ret = property_enable(rphy->grf, &rphy->phy_cfg->clkout_ctl, true);
if (ret)
return ret;
@@ -343,19 +335,17 @@ static void rockchip_usb2phy_clk480m_unprepare(struct clk_hw *hw)
{
struct rockchip_usb2phy *rphy =
container_of(hw, struct rockchip_usb2phy, clk480m_hw);
- struct regmap *base = get_reg_base(rphy);
/* turn off 480m clk output */
- property_enable(base, &rphy->phy_cfg->clkout_ctl, false);
+ property_enable(rphy->grf, &rphy->phy_cfg->clkout_ctl, false);
}
static int rockchip_usb2phy_clk480m_prepared(struct clk_hw *hw)
{
struct rockchip_usb2phy *rphy =
container_of(hw, struct rockchip_usb2phy, clk480m_hw);
- struct regmap *base = get_reg_base(rphy);
- return property_enabled(base, &rphy->phy_cfg->clkout_ctl);
+ return property_enabled(rphy->grf, &rphy->phy_cfg->clkout_ctl);
}
static unsigned long
@@ -574,7 +564,6 @@ static int rockchip_usb2phy_power_on(struct phy *phy)
{
struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
- struct regmap *base = get_reg_base(rphy);
int ret;
dev_dbg(&rport->phy->dev, "port power on\n");
@@ -586,7 +575,7 @@ static int rockchip_usb2phy_power_on(struct phy *phy)
if (ret)
return ret;
- ret = property_enable(base, &rport->port_cfg->phy_sus, false);
+ ret = property_enable(rphy->grf, &rport->port_cfg->phy_sus, false);
if (ret) {
clk_disable_unprepare(rphy->clk480m);
return ret;
@@ -615,7 +604,6 @@ static int rockchip_usb2phy_power_off(struct phy *phy)
{
struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
- struct regmap *base = get_reg_base(rphy);
int ret;
dev_dbg(&rport->phy->dev, "port power off\n");
@@ -623,7 +611,7 @@ static int rockchip_usb2phy_power_off(struct phy *phy)
if (rport->suspended)
return 0;
- ret = property_enable(base, &rport->port_cfg->phy_sus, true);
+ ret = property_enable(rphy->grf, &rport->port_cfg->phy_sus, true);
if (ret)
return ret;
@@ -787,28 +775,22 @@ static const char *chg_to_string(enum power_supply_type chg_type)
static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy,
bool en)
{
- struct regmap *base = get_reg_base(rphy);
-
- property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);
- property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en);
+ property_enable(rphy->grf, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);
+ property_enable(rphy->grf, &rphy->phy_cfg->chg_det.idp_src_en, en);
}
static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy,
bool en)
{
- struct regmap *base = get_reg_base(rphy);
-
- property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en);
- property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en);
+ property_enable(rphy->grf, &rphy->phy_cfg->chg_det.vdp_src_en, en);
+ property_enable(rphy->grf, &rphy->phy_cfg->chg_det.idm_sink_en, en);
}
static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy,
bool en)
{
- struct regmap *base = get_reg_base(rphy);
-
- property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en);
- property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en);
+ property_enable(rphy->grf, &rphy->phy_cfg->chg_det.vdm_src_en, en);
+ property_enable(rphy->grf, &rphy->phy_cfg->chg_det.idp_sink_en, en);
}
#define CHG_DCD_POLL_TIME (100 * HZ / 1000)
@@ -820,7 +802,6 @@ static void rockchip_chg_detect_work(struct work_struct *work)
struct rockchip_usb2phy_port *rport =
container_of(work, struct rockchip_usb2phy_port, chg_work.work);
struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
- struct regmap *base = get_reg_base(rphy);
bool is_dcd, tmout, vout, vbus_attach;
unsigned long delay;
@@ -834,7 +815,7 @@ static void rockchip_chg_detect_work(struct work_struct *work)
rockchip_usb2phy_power_off(rport->phy);
/* put the controller in non-driving mode */
if (!vbus_attach)
- property_enable(base, &rphy->phy_cfg->chg_det.opmode, false);
+ property_enable(rphy->grf, &rphy->phy_cfg->chg_det.opmode, false);
/* Start DCD processing stage 1 */
rockchip_chg_enable_dcd(rphy, true);
rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
@@ -898,7 +879,7 @@ static void rockchip_chg_detect_work(struct work_struct *work)
case USB_CHG_STATE_DETECTED:
/* put the controller in normal mode */
if (!vbus_attach)
- property_enable(base, &rphy->phy_cfg->chg_det.opmode, true);
+ property_enable(rphy->grf, &rphy->phy_cfg->chg_det.opmode, true);
rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
dev_dbg(&rport->phy->dev, "charger = %s\n",
chg_to_string(rphy->chg_type));
@@ -1353,27 +1334,14 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev)
if (!rphy)
return -ENOMEM;
- if (!dev->parent || !dev->parent->of_node) {
+ if (!dev->parent || !dev->parent->of_node ||
+ of_property_present(np, "rockchip,usbgrf")) {
rphy->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbgrf");
- if (IS_ERR(rphy->grf)) {
- dev_err(dev, "failed to locate usbgrf\n");
- return PTR_ERR(rphy->grf);
- }
} else {
rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
- if (IS_ERR(rphy->grf))
- return PTR_ERR(rphy->grf);
- }
-
- if (of_device_is_compatible(np, "rockchip,rv1108-usb2phy")) {
- rphy->usbgrf =
- syscon_regmap_lookup_by_phandle(dev->of_node,
- "rockchip,usbgrf");
- if (IS_ERR(rphy->usbgrf))
- return PTR_ERR(rphy->usbgrf);
- } else {
- rphy->usbgrf = NULL;
}
+ if (IS_ERR(rphy->grf))
+ return PTR_ERR(rphy->grf);
if (of_property_read_u32_index(np, "reg", 0, ®)) {
dev_err(dev, "the reg property is not assigned in %pOFn node\n", np);
--
2.47.3
--
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH v2 5/5] phy: rockchip: inno-usb2: Add support for RK3528
From: Heiko Stuebner @ 2026-05-05 17:04 UTC (permalink / raw)
To: vkoul
Cc: neil.armstrong, robh, krzk+dt, conor+dt, heiko, linux-phy,
devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, jonas,
Jianwei Zheng
In-Reply-To: <20260505170410.3265305-1-heiko@sntech.de>
From: Jianwei Zheng <jianwei.zheng@rock-chips.com>
The RK3528 has a single USB2PHY with a otg and host port.
Add support for the RK3528 variant of USB2PHY.
PHY tuning for RK3528:
- Turn off differential receiver in suspend mode to save power
consumption.
- Set HS eye-height to 400mV instead of default 450mV.
- Choose the Tx fs/ls data as linestate from TX driver for otg port
which uses dwc3 controller to improve fs/ls devices compatibility with
long cables.
Undocumented magic-values are based on the linux-stan-6.1-rkr5 tag of
the vendor-kernel.
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 84 +++++++++++++++++++
1 file changed, 84 insertions(+)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index d8879fcd4291..133cfd6624e8 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -1511,6 +1511,38 @@ static int rk3128_usb2phy_tuning(struct rockchip_usb2phy *rphy)
BIT(2) << BIT_WRITEABLE_SHIFT | 0);
}
+static int rk3528_usb2phy_tuning(struct rockchip_usb2phy *rphy)
+{
+ int ret;
+
+ /* Turn off otg port differential receiver in suspend mode */
+ ret = regmap_write(rphy->phy_base, 0x30, BIT(18) | 0x0000);
+ if (ret)
+ return ret;
+
+ /* Turn off host port differential receiver in suspend mode */
+ ret = regmap_write(rphy->phy_base, 0x430, BIT(18) | 0x0000);
+ if (ret)
+ return ret;
+
+ /* Set otg port HS eye height to 400mv (default is 450mv) */
+ ret = regmap_write(rphy->phy_base, 0x30, GENMASK(22, 20) | 0x0000);
+ if (ret)
+ return ret;
+
+ /* Set host port HS eye height to 400mv (default is 450mv) */
+ ret = regmap_write(rphy->phy_base, 0x430, GENMASK(22, 20) | 0x0000);
+ if (ret)
+ return ret;
+
+ /* Choose the Tx fs/ls data as linestate from TX driver for otg port */
+ ret = regmap_write(rphy->phy_base, 0x94, GENMASK(22, 19) | 0x0018);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
static int rk3576_usb2phy_tuning(struct rockchip_usb2phy *rphy)
{
int ret;
@@ -1924,6 +1956,57 @@ static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
{ /* sentinel */ }
};
+static const struct rockchip_usb2phy_cfg rk3528_phy_cfgs[] = {
+ {
+ .reg = 0xffdf0000,
+ .num_ports = 2,
+ .phy_tuning = rk3528_usb2phy_tuning,
+ .clkout_ctl_phy = { 0x041c, 7, 2, 0, 0x27 },
+ .port_cfgs = {
+ [USB2PHY_PORT_OTG] = {
+ .phy_sus = { 0x004c, 8, 0, 0, 0x1d1 },
+ .bvalid_det_en = { 0x0074, 3, 2, 0, 3 },
+ .bvalid_det_st = { 0x0078, 3, 2, 0, 3 },
+ .bvalid_det_clr = { 0x007c, 3, 2, 0, 3 },
+ .idfall_det_en = { 0x0074, 5, 5, 0, 1 },
+ .idfall_det_st = { 0x0078, 5, 5, 0, 1 },
+ .idfall_det_clr = { 0x007c, 5, 5, 0, 1 },
+ .idrise_det_en = { 0x0074, 4, 4, 0, 1 },
+ .idrise_det_st = { 0x0078, 4, 4, 0, 1 },
+ .idrise_det_clr = { 0x007c, 4, 4, 0, 1 },
+ .ls_det_en = { 0x0074, 0, 0, 0, 1 },
+ .ls_det_st = { 0x0078, 0, 0, 0, 1 },
+ .ls_det_clr = { 0x007c, 0, 0, 0, 1 },
+ .utmi_avalid = { 0x006c, 1, 1, 0, 1 },
+ .utmi_bvalid = { 0x006c, 0, 0, 0, 1 },
+ .utmi_id = { 0x006c, 6, 6, 0, 1 },
+ .utmi_ls = { 0x006c, 5, 4, 0, 1 },
+ },
+ [USB2PHY_PORT_HOST] = {
+ .phy_sus = { 0x005c, 8, 0, 0x1d2, 0x1d1 },
+ .ls_det_en = { 0x0090, 0, 0, 0, 1 },
+ .ls_det_st = { 0x0094, 0, 0, 0, 1 },
+ .ls_det_clr = { 0x0098, 0, 0, 0, 1 },
+ .utmi_ls = { 0x006c, 13, 12, 0, 1 },
+ .utmi_hstdet = { 0x006c, 15, 15, 0, 1 },
+ }
+ },
+ .chg_det = {
+ .opmode = { 0x004c, 3, 0, 5, 1 },
+ .cp_det = { 0x006c, 19, 19, 0, 1 },
+ .dcp_det = { 0x006c, 18, 18, 0, 1 },
+ .dp_det = { 0x006c, 20, 20, 0, 1 },
+ .idm_sink_en = { 0x0058, 1, 1, 0, 1 },
+ .idp_sink_en = { 0x0058, 0, 0, 0, 1 },
+ .idp_src_en = { 0x0058, 2, 2, 0, 1 },
+ .rdm_pdwn_en = { 0x0058, 3, 3, 0, 1 },
+ .vdm_src_en = { 0x0058, 5, 5, 0, 1 },
+ .vdp_src_en = { 0x0058, 4, 4, 0, 1 },
+ },
+ },
+ { /* sentinel */ }
+};
+
static const struct rockchip_usb2phy_cfg rk3562_phy_cfgs[] = {
{
.reg = 0xff740000,
@@ -2291,6 +2374,7 @@ static const struct of_device_id rockchip_usb2phy_dt_match[] = {
{ .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
{ .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
{ .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
+ { .compatible = "rockchip,rk3528-usb2phy", .data = &rk3528_phy_cfgs },
{ .compatible = "rockchip,rk3562-usb2phy", .data = &rk3562_phy_cfgs },
{ .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs },
{ .compatible = "rockchip,rk3576-usb2phy", .data = &rk3576_phy_cfgs },
--
2.47.3
--
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH v2 4/5] phy: rockchip: inno-usb2: Add clkout_ctl_phy support
From: Heiko Stuebner @ 2026-05-05 17:04 UTC (permalink / raw)
To: vkoul
Cc: neil.armstrong, robh, krzk+dt, conor+dt, heiko, linux-phy,
devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, jonas
In-Reply-To: <20260505170410.3265305-1-heiko@sntech.de>
From: Jonas Karlman <jonas@kwiboo.se>
The 480m clk is controlled using regs in the PHY address space and not
in the USB GRF address space on e.g. RK3528 and RK3506.
Add a clkout_ctl_phy usb2phy_reg to handle enable/disable of the 480m
clk on these SoCs.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 47 +++++++++++++++----
1 file changed, 38 insertions(+), 9 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index 7cec45192393..d8879fcd4291 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -179,6 +179,7 @@ struct rockchip_usb2phy_cfg {
unsigned int num_ports;
int (*phy_tuning)(struct rockchip_usb2phy *rphy);
struct usb2phy_reg clkout_ctl;
+ struct usb2phy_reg clkout_ctl_phy;
const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
const struct rockchip_chg_det_reg chg_det;
};
@@ -228,6 +229,7 @@ struct rockchip_usb2phy_port {
* struct rockchip_usb2phy - usb2.0 phy driver data.
* @dev: pointer to device.
* @grf: General Register Files regmap.
+ * @phy_base: USB PHY regmap.
* @clks: array of phy input clocks.
* @clk480m: clock struct of phy output clk.
* @clk480m_hw: clock struct of phy output clk management.
@@ -245,6 +247,7 @@ struct rockchip_usb2phy_port {
struct rockchip_usb2phy {
struct device *dev;
struct regmap *grf;
+ struct regmap *phy_base;
struct clk_bulk_data *clks;
struct clk *clk480m;
struct clk_hw clk480m_hw;
@@ -312,15 +315,33 @@ static void rockchip_usb2phy_clk_bulk_disable(void *data)
clk_bulk_disable_unprepare(rphy->num_clks, rphy->clks);
}
-static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
+static void
+rockchip_usb2phy_clk480m_clkout_ctl(struct clk_hw *hw, struct regmap **base,
+ const struct usb2phy_reg **clkout_ctl)
{
struct rockchip_usb2phy *rphy =
container_of(hw, struct rockchip_usb2phy, clk480m_hw);
+
+ if (rphy->phy_cfg->clkout_ctl_phy.enable) {
+ *base = rphy->phy_base;
+ *clkout_ctl = &rphy->phy_cfg->clkout_ctl_phy;
+ } else {
+ *base = rphy->grf;
+ *clkout_ctl = &rphy->phy_cfg->clkout_ctl;
+ }
+}
+
+static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
+{
+ const struct usb2phy_reg *clkout_ctl;
+ struct regmap *base;
int ret;
+ rockchip_usb2phy_clk480m_clkout_ctl(hw, &base, &clkout_ctl);
+
/* turn on 480m clk output if it is off */
- if (!property_enabled(rphy->grf, &rphy->phy_cfg->clkout_ctl)) {
- ret = property_enable(rphy->grf, &rphy->phy_cfg->clkout_ctl, true);
+ if (!property_enabled(base, clkout_ctl)) {
+ ret = property_enable(base, clkout_ctl, true);
if (ret)
return ret;
@@ -333,19 +354,23 @@ static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
static void rockchip_usb2phy_clk480m_unprepare(struct clk_hw *hw)
{
- struct rockchip_usb2phy *rphy =
- container_of(hw, struct rockchip_usb2phy, clk480m_hw);
+ const struct usb2phy_reg *clkout_ctl;
+ struct regmap *base;
+
+ rockchip_usb2phy_clk480m_clkout_ctl(hw, &base, &clkout_ctl);
/* turn off 480m clk output */
- property_enable(rphy->grf, &rphy->phy_cfg->clkout_ctl, false);
+ property_enable(base, clkout_ctl, false);
}
static int rockchip_usb2phy_clk480m_prepared(struct clk_hw *hw)
{
- struct rockchip_usb2phy *rphy =
- container_of(hw, struct rockchip_usb2phy, clk480m_hw);
+ const struct usb2phy_reg *clkout_ctl;
+ struct regmap *base;
+
+ rockchip_usb2phy_clk480m_clkout_ctl(hw, &base, &clkout_ctl);
- return property_enabled(rphy->grf, &rphy->phy_cfg->clkout_ctl);
+ return property_enabled(base, clkout_ctl);
}
static unsigned long
@@ -1336,9 +1361,13 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev)
if (!dev->parent || !dev->parent->of_node ||
of_property_present(np, "rockchip,usbgrf")) {
+ rphy->phy_base = device_node_to_regmap(np);
+ if (IS_ERR(rphy->phy_base))
+ return PTR_ERR(rphy->phy_base);
rphy->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbgrf");
} else {
rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
+ rphy->phy_base = rphy->grf;
}
if (IS_ERR(rphy->grf))
return PTR_ERR(rphy->grf);
--
2.47.3
--
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^ permalink raw reply related
* [PATCH v2 0/5] rockchip: Add USB 2.0 support for RK3528
From: Heiko Stuebner @ 2026-05-05 17:04 UTC (permalink / raw)
To: vkoul
Cc: neil.armstrong, robh, krzk+dt, conor+dt, heiko, linux-phy,
devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, jonas
This series adds support for USB 2.0 on Rockchip RK3528 to the
Innosilicon usbphy driver.
The usb3 support has already been merge for the naneng combophy
last year.
Changes in v2:
- rebase on top of v7.1-rc1
- split off dwc3 compatible and dts changes
- add error handling to regmap_write (Vinod)
- v1 is here
https://lore.kernel.org/linux-rockchip/20250723122323.2344916-1-jonas@kwiboo.se/
Jianwei Zheng (1):
phy: rockchip: inno-usb2: Add support for RK3528
Jonas Karlman (4):
dt-bindings: phy: rockchip,inno-usb2phy: Require GRF for RK3568/RV1108
phy: rockchip: inno-usb2: Simplify rockchip,usbgrf handling
dt-bindings: phy: rockchip,inno-usb2phy: Add compatible for RK3528
phy: rockchip: inno-usb2: Add clkout_ctl_phy support
.../bindings/phy/rockchip,inno-usb2phy.yaml | 44 +++-
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 191 +++++++++++++-----
2 files changed, 176 insertions(+), 59 deletions(-)
--
2.47.3
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^ permalink raw reply
* [PATCH v2 1/5] dt-bindings: phy: rockchip,inno-usb2phy: Require GRF for RK3568/RV1108
From: Heiko Stuebner @ 2026-05-05 17:04 UTC (permalink / raw)
To: vkoul
Cc: neil.armstrong, robh, krzk+dt, conor+dt, heiko, linux-phy,
devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, jonas
In-Reply-To: <20260505170410.3265305-1-heiko@sntech.de>
From: Jonas Karlman <jonas@kwiboo.se>
Typically these Rockchip USB2 PHYs are fully contained within a single
GRF. However, for RK3568 and RV1108 regs to control the USB2 PHY is
located in a different GRF compared to the base address.
Update this binding to require rockchip,usbgrf for RK3568 and RV1108 to
properly reflect that the USB GRF is required to control the USB2 PHYs
on these variants. Also disable use of rockchip,usbgrf for variants
where it is not required.
This should not introduce any breakage as the affected usb2phy nodes for
RK3568 and RV1108 were added together with a rockchip,usbgrf phandle in
their initial commit.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
.../bindings/phy/rockchip,inno-usb2phy.yaml | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml
index 58e735b5dd05..b95c9e3e44fe 100644
--- a/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml
+++ b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml
@@ -145,6 +145,20 @@ anyOf:
- host-port
allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - rockchip,rk3568-usb2phy
+ - rockchip,rv1108-usb2phy
+ then:
+ required:
+ - rockchip,usbgrf
+ else:
+ properties:
+ rockchip,usbgrf: false
+
- if:
properties:
compatible:
--
2.47.3
--
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* Re: [PATCH v8 phy-next 01/31] PCI: cadence: Preserve all error codes in cdns_plat_pcie_probe()
From: Bjorn Helgaas @ 2026-05-05 16:26 UTC (permalink / raw)
To: Vladimir Oltean
Cc: linux-phy, Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-scsi,
linux-sunxi, linux-tegra, linux-usb, netdev, spacemit,
UNGLinuxDriver, Bjorn Helgaas, Krzysztof Wilczyński,
Lorenzo Pieralisi, Manikandan K Pillai, Manivannan Sadhasivam,
Rob Herring, Tom Joseph
In-Reply-To: <20260505100523.1922388-2-vladimir.oltean@nxp.com>
[+cc Tom, author of bd22885aa188 in case there's something subtle here]
On Tue, May 05, 2026 at 01:04:53PM +0300, Vladimir Oltean wrote:
> The blamed commit functionally changed the error path of
> cdns_pcie_host_probe(), now cdns_plat_pcie_probe().
>
> When the old code path executed "goto err_get_sync", the PCIe controller
> probe function propagated the pm_runtime_get_sync() error code. The new
> code doesn't, and returns 0.
>
> Similarly for the "goto err_init" previously triggered by
> cdns_pcie_host_init() errors, and now triggered by
> cdns_pcie_host_setup() and cdns_pcie_ep_setup() errors. These are not
> propagated and will result in probing success, which is incorrect.
>
> Fixes: bd22885aa188 ("PCI: cadence: Refactor driver to use as a core library")
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> ---
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: "Krzysztof Wilczyński" <kwilczynski@kernel.org>
> Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
> Cc: Manikandan K Pillai <mpillai@cadence.com>
> Cc: Manivannan Sadhasivam <mani@kernel.org>
> Cc: Rob Herring <robh@kernel.org>
I guess this driver is orphaned.
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
> v7->v8: patch is new, issue was flagged by Sashiko
> https://sashiko.dev/#/patchset/20260430110652.558622-1-vladimir.oltean@nxp.com
> ---
> drivers/pci/controller/cadence/pcie-cadence-plat.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/cadence/pcie-cadence-plat.c b/drivers/pci/controller/cadence/pcie-cadence-plat.c
> index b067a3296dd3..8b12a46b5601 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence-plat.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence-plat.c
> @@ -126,7 +126,7 @@ static int cdns_plat_pcie_probe(struct platform_device *pdev)
> while (phy_count--)
> device_link_del(cdns_plat_pcie->pcie->link[phy_count]);
>
> - return 0;
> + return ret;
This affects cases where pm_runtime_get_sync(),
cdns_pcie_host_setup(), or cdns_pcie_ep_setup() return failure.
Seems right to me to fail the probe when these fail.
Not all users of pm_runtime_get_sync() check for failure, but I think
all the other controller drivers that do check return failures from
the .probe().
> }
>
> static void cdns_plat_pcie_shutdown(struct platform_device *pdev)
> --
> 2.34.1
>
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^ permalink raw reply
* Re: [PATCH v4 01/16] dt-bindings: phy: rockchip-usbdp: add improved ports scheme
From: Rob Herring (Arm) @ 2026-05-05 15:45 UTC (permalink / raw)
To: Sebastian Reichel
Cc: Conor Dooley, linux-phy, kernel, devicetree, Dmitry Baryshkov,
Neil Armstrong, Andy Yan, linux-arm-kernel, linux-rockchip,
Yubing Zhang, Frank Wang, Krzysztof Kozlowski, linux-kernel,
Alexey Charkov, Heiko Stuebner, Vinod Koul
In-Reply-To: <20260428-rockchip-usbdp-cleanup-v4-1-7775671ece22@collabora.com>
On Tue, 28 Apr 2026 18:13:40 +0200, Sebastian Reichel wrote:
> Currently the Rockchip USBDP PHY is missing a documented port scheme.
> Meanwhile upstream RK3588 DTS files are a bit messy and use different
> port schemes. The upstream USBDP PHY Linux kernel driver does not yet
> parse the ports at all and thus does not create any implicit ABI either.
>
> But with the current mess it is not possible to properly support USB-C
> DP AltMode. Thus this introduces a proper port scheme following roughly
> the ports design of the Qualcomm QMP USB4-USB3-DP PHY controller binding
> with a slight difference that there is an additional port for the
> USB-C SBU port as the Rockchip USB-DP PHY also contains the SBU mux.
>
> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
> ---
> .../bindings/phy/phy-rockchip-usbdp.yaml | 23 ++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
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^ permalink raw reply
* Re: [PATCH v4 01/16] dt-bindings: phy: rockchip-usbdp: add improved ports scheme
From: Rob Herring @ 2026-05-05 15:44 UTC (permalink / raw)
To: Sebastian Reichel
Cc: Vinod Koul, Neil Armstrong, Heiko Stuebner, Frank Wang,
Krzysztof Kozlowski, Conor Dooley, Andy Yan, Dmitry Baryshkov,
Yubing Zhang, Alexey Charkov, linux-phy, linux-arm-kernel,
linux-rockchip, linux-kernel, kernel, devicetree
In-Reply-To: <20260428-rockchip-usbdp-cleanup-v4-1-7775671ece22@collabora.com>
On Tue, Apr 28, 2026 at 06:13:40PM +0200, Sebastian Reichel wrote:
> Currently the Rockchip USBDP PHY is missing a documented port scheme.
> Meanwhile upstream RK3588 DTS files are a bit messy and use different
> port schemes. The upstream USBDP PHY Linux kernel driver does not yet
> parse the ports at all and thus does not create any implicit ABI either.
>
> But with the current mess it is not possible to properly support USB-C
> DP AltMode. Thus this introduces a proper port scheme following roughly
> the ports design of the Qualcomm QMP USB4-USB3-DP PHY controller binding
> with a slight difference that there is an additional port for the
> USB-C SBU port as the Rockchip USB-DP PHY also contains the SBU mux.
>
> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Missing my tag.
> ---
> .../bindings/phy/phy-rockchip-usbdp.yaml | 23 ++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml
> index 8b7059d5b182..f728acf057e4 100644
> --- a/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml
> +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml
> @@ -114,6 +114,29 @@ properties:
> A port node to link the PHY to a TypeC controller for the purpose of
> handling orientation switching.
>
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> + properties:
> + port@0:
> + $ref: /schemas/graph.yaml#/properties/port
> + description:
> + Output endpoint of the PHY for USB (or DP when configured into 4 lane
> + mode), which should point to the superspeed port of a USB connector.
> +
> + port@1:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: Incoming endpoint from the USB controller
> +
> + port@2:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: Incoming endpoint from the DisplayPort controller
> +
> + port@3:
> + $ref: /schemas/graph.yaml#/properties/port
> + description:
> + Output endpoint of the PHY for DP, which should either point to the
> + SBU port of a USB-C connector or a DisplayPort connector input port.
> +
> required:
> - compatible
> - reg
>
> --
> 2.53.0
>
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^ permalink raw reply
* Re: [PATCH v2 2/4] dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: Add support for Shikra
From: Krzysztof Kozlowski @ 2026-05-05 14:00 UTC (permalink / raw)
To: Krishna Kurapati
Cc: Neil Armstrong, Vinod Koul, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Konrad Dybcio, Xiangxu Yin,
Johan Hovold, Loic Poulain, Kathiravan Thirumoorthy,
Dmitry Baryshkov, linux-arm-msm, linux-phy, devicetree,
linux-kernel
In-Reply-To: <62161822-2365-4ec7-80f7-8660bdadb177@oss.qualcomm.com>
On 05/05/2026 15:57, Krishna Kurapati wrote:
>
>
> On 5/5/2026 6:59 PM, Krzysztof Kozlowski wrote:
>> On 05/05/2026 15:27, Krishna Kurapati wrote:
>>>
>>>
>>> On 5/5/2026 4:22 PM, Krzysztof Kozlowski wrote:
>>>> On 05/05/2026 12:49, Krzysztof Kozlowski wrote:
>>>>> On Mon, May 04, 2026 at 10:36:57PM +0530, Krishna Kurapati wrote:
>>>>>> Declare the USB-C QMP PHY present on the Qualcomm Shikra platform.
>>>>>>
>>>>>> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
>>>>>> ---
>>>>>> .../devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml | 2 ++
>>>>>> 1 file changed, 2 insertions(+)
>>>>>
>>>>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
>>>>
>>>> ... and then I looked at the driver. So un-reviewed. Devices are clearly
>>>> compatible. If not, explain what is not compatible.
>>>>
>>> Talos uses GCC_USB3_PRIM_PHY_AUX_CLK.
>>>
>>> In Shikra, we are using GCC_USB3_PRIM_PHY_COM_AUX_CLK. We don't have
>>> GCC_USB3_PRIM_PHY_AUX_CLK.
>>>
>>> Hence, I didn't use a fallback compatible.
>>
>> This still explains nothing. How different clock makes interface for SW
>> incompatible exactly?
>>
> So I went by the naming. AUX vs COM_AUX.
The naming does not matter. If the clock is called
"no_one_expects_spanish_inquisition", does that make software
incompatible? Why would the name itself matter?
>
> Can I use a fallback compatible and in DT vote for "COM_AUX" clock with
> clock-names mentioning "aux" ?
I don't know, I asked what is different in software interface.
Best regards,
Krzysztof
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* Re: [PATCH v2 2/4] dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: Add support for Shikra
From: Krishna Kurapati @ 2026-05-05 13:57 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Neil Armstrong, Vinod Koul, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Konrad Dybcio, Xiangxu Yin,
Johan Hovold, Loic Poulain, Kathiravan Thirumoorthy,
Dmitry Baryshkov, linux-arm-msm, linux-phy, devicetree,
linux-kernel
In-Reply-To: <29571bdd-23bf-42a7-a9e3-918a28c79700@kernel.org>
On 5/5/2026 6:59 PM, Krzysztof Kozlowski wrote:
> On 05/05/2026 15:27, Krishna Kurapati wrote:
>>
>>
>> On 5/5/2026 4:22 PM, Krzysztof Kozlowski wrote:
>>> On 05/05/2026 12:49, Krzysztof Kozlowski wrote:
>>>> On Mon, May 04, 2026 at 10:36:57PM +0530, Krishna Kurapati wrote:
>>>>> Declare the USB-C QMP PHY present on the Qualcomm Shikra platform.
>>>>>
>>>>> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
>>>>> ---
>>>>> .../devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml | 2 ++
>>>>> 1 file changed, 2 insertions(+)
>>>>
>>>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
>>>
>>> ... and then I looked at the driver. So un-reviewed. Devices are clearly
>>> compatible. If not, explain what is not compatible.
>>>
>> Talos uses GCC_USB3_PRIM_PHY_AUX_CLK.
>>
>> In Shikra, we are using GCC_USB3_PRIM_PHY_COM_AUX_CLK. We don't have
>> GCC_USB3_PRIM_PHY_AUX_CLK.
>>
>> Hence, I didn't use a fallback compatible.
>
> This still explains nothing. How different clock makes interface for SW
> incompatible exactly?
>
So I went by the naming. AUX vs COM_AUX.
Can I use a fallback compatible and in DT vote for "COM_AUX" clock with
clock-names mentioning "aux" ?
Regards,
Krishna,
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^ permalink raw reply
* Re: [PATCH v2 2/4] dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: Add support for Shikra
From: Krzysztof Kozlowski @ 2026-05-05 13:29 UTC (permalink / raw)
To: Krishna Kurapati
Cc: Neil Armstrong, Vinod Koul, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Konrad Dybcio, Xiangxu Yin,
Johan Hovold, Loic Poulain, Kathiravan Thirumoorthy,
Dmitry Baryshkov, linux-arm-msm, linux-phy, devicetree,
linux-kernel
In-Reply-To: <95b567cc-b83c-4154-9520-e624555f1882@oss.qualcomm.com>
On 05/05/2026 15:27, Krishna Kurapati wrote:
>
>
> On 5/5/2026 4:22 PM, Krzysztof Kozlowski wrote:
>> On 05/05/2026 12:49, Krzysztof Kozlowski wrote:
>>> On Mon, May 04, 2026 at 10:36:57PM +0530, Krishna Kurapati wrote:
>>>> Declare the USB-C QMP PHY present on the Qualcomm Shikra platform.
>>>>
>>>> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
>>>> ---
>>>> .../devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml | 2 ++
>>>> 1 file changed, 2 insertions(+)
>>>
>>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
>>
>> ... and then I looked at the driver. So un-reviewed. Devices are clearly
>> compatible. If not, explain what is not compatible.
>>
> Talos uses GCC_USB3_PRIM_PHY_AUX_CLK.
>
> In Shikra, we are using GCC_USB3_PRIM_PHY_COM_AUX_CLK. We don't have
> GCC_USB3_PRIM_PHY_AUX_CLK.
>
> Hence, I didn't use a fallback compatible.
This still explains nothing. How different clock makes interface for SW
incompatible exactly?
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH v2 2/4] dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: Add support for Shikra
From: Krishna Kurapati @ 2026-05-05 13:27 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Neil Armstrong, Vinod Koul, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Konrad Dybcio, Xiangxu Yin,
Johan Hovold, Loic Poulain, Kathiravan Thirumoorthy,
Dmitry Baryshkov, linux-arm-msm, linux-phy, devicetree,
linux-kernel
In-Reply-To: <8cd564af-9646-40c5-a8ef-c7197fb3cfe9@kernel.org>
On 5/5/2026 4:22 PM, Krzysztof Kozlowski wrote:
> On 05/05/2026 12:49, Krzysztof Kozlowski wrote:
>> On Mon, May 04, 2026 at 10:36:57PM +0530, Krishna Kurapati wrote:
>>> Declare the USB-C QMP PHY present on the Qualcomm Shikra platform.
>>>
>>> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
>>> ---
>>> .../devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml | 2 ++
>>> 1 file changed, 2 insertions(+)
>>
>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
>
> ... and then I looked at the driver. So un-reviewed. Devices are clearly
> compatible. If not, explain what is not compatible.
>
Talos uses GCC_USB3_PRIM_PHY_AUX_CLK.
In Shikra, we are using GCC_USB3_PRIM_PHY_COM_AUX_CLK. We don't have
GCC_USB3_PRIM_PHY_AUX_CLK.
Hence, I didn't use a fallback compatible.
Regards,
Krishna,
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* Re: [PATCH v5 0/6] phy: realtek: usb2: support for RTL9607C USB2 PHY
From: Vladimir Oltean @ 2026-05-05 11:37 UTC (permalink / raw)
To: Rustam Adilov
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stanley Chang, linux-phy, devicetree, linux-kernel
In-Reply-To: <20260420191941.81834-1-adilov@disroot.org>
On Tue, Apr 21, 2026 at 12:19:35AM +0500, Rustam Adilov wrote:
> This patch series for Realtek USB2 PHY driver adds support for RTL9607C
> USB2 PHY.
>
> RTL9607C is a big endian MIPS CPU which is quite far from RTD series SoCs
> supported by realtek usb2 phy driver, but the phy initilization is found
> to be very indentical in most areas.
>
> Most of the code was based on the Realtek's usb driver from the GPL tarball
> in [1] and adjusted to fit into the realtek usb2 phy driver code format.
>
> The patch series was split into smaller patches that add/change something
> in the driver that are not exactly related to RTL9607C and that also
> helps for easier review. That also means, patch 5 depends on all the prior
> patches that come before it.
>
> USB2 PHY on RTL9607C is primarly used for its internal OHCI/EHCI controllers.
>
> [1] - https://github.com/jameywine/GPL-for-GP3000/blob/main/linux-5.10.x/arch/mips/rtl9607c/usb.c
>
> ---
Could you go through Patchwork and reply inline to the issues found,
stating whether you are or are not going to resolve them?
https://patchwork.kernel.org/project/linux-phy/list/?series=1083475
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* Re: [PATCH v5 5/6] phy: realtek: usb2: add support for RTL9607C USB2 PHY
From: Vladimir Oltean @ 2026-05-05 11:30 UTC (permalink / raw)
To: Rustam Adilov
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stanley Chang, linux-phy, devicetree, linux-kernel,
Michael Zavertkin
In-Reply-To: <20260420191941.81834-6-adilov@disroot.org>
On Tue, Apr 21, 2026 at 12:19:40AM +0500, Rustam Adilov wrote:
> Add support for the usb2 phy of RTL9607C series based SoCs.
> Add the macros and phy config struct for rtl9607.
>
> RTL9607C requires to clear a "force host disconnect" bit in the
> specific register (which is at an offset from reg_wrap_vstatus)
> before proceeding with phy parameter writes. Since it belongs into
> the vstatus register region, it doesn't need bytes swapping.
>
> Add the bool variable to the driver data struct and hide this whole
> procedure under the if statement that checks this new variable.
>
> Add the appropriate little endian read and write functions for rtl9607
> and assign them to its phy config struct.
>
> As mentioned earlier, the readl/writel are native endian on MIPS arch
> if SWAP_IO_SPACE is not enabled. Since enabling SWAP_IO_SPACE results
> in boot hang on RTL9607C machine, wrapping le32 around readl/writel
> should be a good compromise, but swab32 could be also work.
>
> Co-developed-by: Michael Zavertkin <misha.zavertkin@mail.ru>
> Signed-off-by: Michael Zavertkin <misha.zavertkin@mail.ru>
> Signed-off-by: Rustam Adilov <adilov@disroot.org>
> ---
Have you considered ioread32() instead of wrapping le32 around readl()?
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* Re: [PATCH v5 5/6] phy: realtek: usb2: add support for RTL9607C USB2 PHY
From: Vladimir Oltean @ 2026-05-05 11:20 UTC (permalink / raw)
To: Rustam Adilov
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stanley Chang, linux-phy, devicetree, linux-kernel,
Michael Zavertkin
In-Reply-To: <20260420191941.81834-6-adilov@disroot.org>
On Tue, Apr 21, 2026 at 12:19:40AM +0500, Rustam Adilov wrote:
> @@ -146,6 +153,18 @@ static void rtk_usb2phy_write(u32 val, void __iomem *reg)
> writel(val, reg);
> }
>
> +static u32 rtk_usb2phy_read_le(void __iomem *reg)
> +{
> + return le32_to_cpu(readl(reg));
"make C=1" warning:
drivers/phy/realtek/phy-rtk-usb2.c:158:16: warning: cast to restricted __le32
> +}
> +
> +static void rtk_usb2phy_write_le(u32 val, void __iomem *reg)
> +{
> + u32 tmp = cpu_to_le32(val);
"make C=1" warning:
drivers/phy/realtek/phy-rtk-usb2.c:163:19: warning: incorrect type in initializer (different base types)
drivers/phy/realtek/phy-rtk-usb2.c:163:19: expected unsigned int [usertype] tmp
drivers/phy/realtek/phy-rtk-usb2.c:163:19: got restricted __le32 [usertype]
> +
> + writel(tmp, reg);
> +}
> +
> /* mapping 0xE0 to 0 ... 0xE7 to 7, 0xF0 to 8 ,,, 0xF7 to 15 */
> static inline int page_addr_to_array_index(u8 addr)
> {
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* Re: [PATCH v2 2/4] dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: Add support for Shikra
From: Krzysztof Kozlowski @ 2026-05-05 10:52 UTC (permalink / raw)
To: Krishna Kurapati
Cc: Neil Armstrong, Vinod Koul, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Konrad Dybcio, Xiangxu Yin,
Johan Hovold, Loic Poulain, Kathiravan Thirumoorthy,
Dmitry Baryshkov, linux-arm-msm, linux-phy, devicetree,
linux-kernel
In-Reply-To: <20260505-gifted-salamander-of-prowess-5107a6@quoll>
On 05/05/2026 12:49, Krzysztof Kozlowski wrote:
> On Mon, May 04, 2026 at 10:36:57PM +0530, Krishna Kurapati wrote:
>> Declare the USB-C QMP PHY present on the Qualcomm Shikra platform.
>>
>> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
>> ---
>> .../devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml | 2 ++
>> 1 file changed, 2 insertions(+)
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
... and then I looked at the driver. So un-reviewed. Devices are clearly
compatible. If not, explain what is not compatible.
Best regards,
Krzysztof
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* Re: [PATCH v2 4/4] phy: qcom: qmp-usbc: Add qmp configuration for Shikra
From: Krzysztof Kozlowski @ 2026-05-05 10:50 UTC (permalink / raw)
To: Krishna Kurapati
Cc: Dmitry Baryshkov, Neil Armstrong, Vinod Koul, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio,
Xiangxu Yin, Johan Hovold, Loic Poulain, Kathiravan Thirumoorthy,
linux-arm-msm, linux-phy, devicetree, linux-kernel
In-Reply-To: <230aef5f-43da-4b7a-994c-7a63b631ae8e@oss.qualcomm.com>
On Tue, May 05, 2026 at 09:36:31AM +0530, Krishna Kurapati wrote:
>
>
> On 5/5/2026 12:58 AM, Dmitry Baryshkov wrote:
> > On Mon, May 04, 2026 at 10:36:59PM +0530, Krishna Kurapati wrote:
> > > Add init sequence and phy configuration for the Super Speed port
> > > on Shikra SoC.
> > >
> > > Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
> > > ---
> > > drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 3 +++
> > > 1 file changed, 3 insertions(+)
> > >
> > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
> > > index c342479a3798..400dcebf8222 100644
> > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
> > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
> > > @@ -2019,6 +2019,9 @@ static const struct of_device_id qmp_usbc_of_match_table[] = {
> > > }, {
> > > .compatible = "qcom,sdm660-qmp-usb3-phy",
> > > .data = &sdm660_usb3phy_cfg,
> > > + }, {
> > > + .compatible = "qcom,shikra-qmp-usb3-phy",
> > > + .data = &qcs615_usb3phy_cfg,
> >
> > If we are reusing Talos configuration, should Talos also be used for the
> > fallback compat instead of modifying the driver?
> >
>
> The clocks are different and hence I didn't use fallback.
And why can't you use the same clocks?
Best regards,
Krzysztof
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