* Re: [PATCH v4] phy: Add USB3 PHY support to Google Tensor SoC USB PHY driver
From: sashiko-bot @ 2026-07-06 23:27 UTC (permalink / raw)
To: RD Babiera; +Cc: olteanv, linux-phy, vkoul, neil.armstrong
In-Reply-To: <20260706231633.700676-2-rdbabiera@google.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
New issues:
- [High] Data race on `gphy->orientation` causes redundant hardware programming and a 2.5-second timeout.
Pre-existing issues:
- [High] TOCTOU race on `pm_runtime_suspended()` allows hardware access while suspended, causing a bus fault.
--
--- Patch [1]: [PATCH v4] phy: Add USB3 PHY support to Google Tensor SoC USB PHY driver ---
commit 1008e9b0470bdcef99e7408c0e43896673f90ba3
Author: RD Babiera <rdbabiera@google.com>
phy: Add USB3 PHY support to Google Tensor SoC USB PHY driver
This patch adds USB3 PHY support for the Google Tensor G5 USB PHY driver,
including the usb3_tca register, clock, and reset functionality. It also
refactors the probe sequence and implements USB3 phy_ops.
> diff --git a/drivers/phy/phy-google-usb.c b/drivers/phy/phy-google-usb.c
> index ab20bc20f19ea..19256588d50ec 100644
> --- a/drivers/phy/phy-google-usb.c
> +++ b/drivers/phy/phy-google-usb.c
[ ... ]
> @@ -92,6 +261,9 @@ static int google_usb_set_orientation(struct typec_switch_dev *sw,
>
> set_vbus_valid(gphy);
>
> + if (gphy->phy_state == COMBO_PHY_TCA_READY && orientation != TYPEC_ORIENTATION_NONE)
> + return program_tca_locked(gphy);
> +
[Severity: High]
This is a pre-existing issue, but does this function have a race condition
with power management that could cause a bus fault?
google_usb_set_orientation() checks pm_runtime_suspended(gphy->dev) without
holding a PM runtime reference. If the USB core releases its PM reference
immediately after this check, the device could suspend and power off the PHY.
The function would then acquire the lock and call set_vbus_valid() and
program_tca_locked() on unclocked and unpowered MMIO registers, resulting
in a synchronous external abort.
Would it be safer to use pm_runtime_get_sync() to ensure the hardware
remains active during these accesses?
> return 0;
> }
[ ... ]
> +static int google_usb3_phy_power_on(struct phy *_phy)
> +{
> + struct google_usb_phy_instance *inst = phy_get_drvdata(_phy);
> + struct google_usb_phy *gphy = inst->parent;
> + int ret;
> +
> + dev_dbg(gphy->dev, "power on usb3 phy\n");
> +
> + guard(mutex)(&gphy->phy_mutex);
> +
> + if (gphy->phy_state != COMBO_PHY_TCA_READY) {
> + /* Wait for PoR -> NC transitions*/
> + ret = wait_tca_xa_ack(gphy);
> + if (ret) {
> + dev_err(gphy->dev, "PoR->NC transition timeout");
> + return ret;
> + }
> + gphy->phy_state = COMBO_PHY_TCA_READY;
> + }
> +
> + if (gphy->orientation != TYPEC_ORIENTATION_NONE)
> + return program_tca_locked(gphy);
[Severity: High]
Can this lead to redundant TCA programming and a 2.5-second timeout?
Looking at google_usb_set_orientation(), gphy->orientation is updated before
the mutex is acquired:
google_usb_set_orientation() {
gphy->orientation = orientation;
if (pm_runtime_suspended(gphy->dev))
return 0;
guard(mutex)(&gphy->phy_mutex);
...
If a Type-C plug event (Thread A) sets gphy->orientation but is preempted
before taking the lock, and the USB core concurrently calls
google_usb3_phy_power_on() (Thread B), Thread B will see the new
orientation, program the TCA, and release the lock.
When Thread A resumes, it will acquire the mutex, see COMBO_PHY_TCA_READY,
and call program_tca_locked() a second time with the identical configuration.
Since writing the same configuration to the TCA hardware doesn't trigger a
new XA_ACT_EVT interrupt, wait_tca_xa_ack() will stall for its full timeout.
Should the orientation update be moved inside the lock?
> +
> + return 0;
> +}
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260706231633.700676-2-rdbabiera@google.com?part=1
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* Re: [PATCH 6/8] phy: qcom: qmp-combo: Drop qmp_v4_calibrate_dp_phy
From: Dmitry Baryshkov @ 2026-07-07 0:50 UTC (permalink / raw)
To: esteuwu
Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd, Brian Masney,
Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Rob Clark, Will Deacon, Robin Murphy, Joerg Roedel (AMD),
Vinod Koul, Neil Armstrong, linux-arm-msm, linux-clk,
linux-kernel, devicetree, iommu, linux-arm-kernel, linux-phy
In-Reply-To: <20260622-sm8450-qol-v1-6-37e2ee8df9da@proton.me>
On Mon, Jun 22, 2026 at 08:54:27PM -0400, Esteban Urrutia via B4 Relay wrote:
> From: Esteban Urrutia <esteuwu@proton.me>
>
> There are no downstream device trees that specify five values in the
> qcom,aux-cfg1-settings array.
> Plus, after cross referencing both downstream device trees and entries
> which refer this function, only 0x13 is specified.
> Since 0x13 is written at initialization time, drop this function as a
> whole, and remove now unused variable assignations.
>
> Signed-off-by: Esteban Urrutia <esteuwu@proton.me>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 31 -------------------------------
> 1 file changed, 31 deletions(-)
>
Indeed, 10nm and 14nm PHYs used several AUX CFG1 values for calibration.
PHYs starting from 7nm don't use this calibration.
Fixes: aff188feb5e1 ("phy: qcom-qmp: add support for sm8250-usb3-dp phy")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
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* Re: [PATCH 2/8] arm64: dts: qcom: sm8450: Remove unneeded reserved memory nodes
From: Esteban Urrutia @ 2026-07-07 3:19 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Konrad Dybcio, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Brian Masney, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rob Clark, Will Deacon, Robin Murphy,
Joerg Roedel (AMD), Vinod Koul, Neil Armstrong, linux-arm-msm,
linux-clk, linux-kernel, devicetree, iommu, linux-arm-kernel,
linux-phy
In-Reply-To: <4g6y4q2udludhwmoqc34afwj5svra4a4j5bmpqza7h3av2oov7@6k5r7a4meruk>
On 7/6/26 2:24 PM, Dmitry Baryshkov wrote:
> Please verify that you can actually access those areas (boot with
> memtest=1)
Thanks for the suggestion!
I actually did boot an SM8475 based device I'm mainlining (motorola-bronco)
with this parameter.
Deleted regions in DT are as follows:
/delete-node/ &mte_mem;
/delete-node/ &oem_vm_mem; (seems to not exist in SM8475?)
/delete-node/ &qheebsp_reserved_mem;
/delete-node/ &trust_ui_vm_mem;
/delete-node/ &trust_ui_vm_qrtr;
/delete-node/ &trust_ui_vm_swiotlb;
/delete-node/ &trust_ui_vm_vblk0_ring;
/delete-node/ &trusted_apps_ext_mem;
/delete-node/ &trusted_apps_mem;
Here are the results:
[ 0.000000] early_memtest: # of tests: 1
[ 0.000000] 0x00000000808f4000 - 0x0000000080900000 pattern 0000000000000000
[ 0.000000] 0x0000000085200000 - 0x0000000085700000 pattern 0000000000000000
[ 0.000000] 0x0000000087f00000 - 0x0000000088000000 pattern 0000000000000000
[ 0.000000] 0x000000008b91c000 - 0x000000008ba00000 pattern 0000000000000000
[ 0.000000] 0x000000009ff80000 - 0x00000000a6e00000 pattern 0000000000000000
[ 0.000000] 0x00000000a6e40000 - 0x00000000a6f00000 pattern 0000000000000000
[ 0.000000] 0x00000000a7000000 - 0x00000000a8000000 pattern 0000000000000000
[ 0.000000] 0x00000000ab350000 - 0x00000000b70cd000 pattern 0000000000000000
[ 0.000000] 0x00000000b70ebdd1 - 0x00000000b72ce000 pattern 0000000000000000
[ 0.000000] 0x00000000b7fff000 - 0x00000000b8000000 pattern 0000000000000000
[ 0.000000] 0x00000000b89e3400 - 0x00000000e0600000 pattern 0000000000000000
[ 0.000000] 0x00000000e0b00000 - 0x00000000e8800000 pattern 0000000000000000
[ 0.000000] 0x00000000f1400000 - 0x0000000100000000 pattern 0000000000000000
[ 0.000000] 0x0000000800000000 - 0x000000083af00000 pattern 0000000000000000
[ 0.000000] 0x000000083b500000 - 0x000000083d300000 pattern 0000000000000000
[ 0.000000] 0x0000000840000000 - 0x000000097f089d40 pattern 0000000000000000
[ 0.000000] 0x000000097f089d6f - 0x000000097f089d70 pattern 0000000000000000
[ 0.000000] 0x000000097f153ff8 - 0x000000097f154000 pattern 0000000000000000
The device didn't crash at boot, and everything works as expected.
For the record, the manufacturer has made changes in downstream device
trees that state TVM is not used, so it's expected that the device works
without QHEE and TVM regions.
Regards,
Esteban
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* Re: [PATCH] phy: allwinner: sun4i-usb: disable the PHY2 PMU clock after SIDDQ setup
From: Xu Rao @ 2026-07-07 3:21 UTC (permalink / raw)
To: andre.przywara
Cc: jernej.skrabec, linux-arm-kernel, linux-kernel, linux-phy,
linux-sunxi, marco.crivellari, neil.armstrong, raoxu, samuel,
vkoul, wens
In-Reply-To: <d8042dd2-303e-4f24-b7bf-74ae080f4ae6@arm.com>
Hi Andre,
> > - clk_disable_unprepare(phy->clk2);
> > + clk_disable_unprepare(phy2->clk2);
>
> Interesting, this looks about right, and matches the comment above,
> noting that phy2->clk2 is just temporarily needed. I don't remember
> further details, only that this workaround was quite annoying and messy ;-)
>
> However I am wondering how this worked so far: This should sabotage the
> access to the local REG_HCI_PHY_CTL access in the next few lines ...
> Any idea why this worked nevertheless?
Yes, the current code is wrong, but the visible effect is limited.
In sun4i_usb_phy_init(), the auxiliary SIDDQ path explicitly enables
phy2->clk2 and then accesses phy2->pmu + REG_HCI_PHY_CTL. So the clock
that has to be disabled at the end of that block is phy2->clk2.
The current code disables phy->clk2 instead, which is a different object.
That does not undo the temporary phy2->clk2 enable.
The reason this has not shown up as an obvious functional failure is that
phy->clk2 is an optional PMU clock. On systems where the non-PHY2 PMU
clock is not provided, the wrong clk_disable_unprepare(phy->clk2) does
not actually disable a local PMU clock. In that case, the practical
visible issue is simply that the temporary phy2->clk2 enable is not
matched by a corresponding disable.
So the failure is not that the following local REG_HCI_PHY_CTL access is
known to break today. The concrete bug is that the auxiliary path enables
one clock and disables another one.
Thanks,
Xu Rao
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* Re: [PATCH 1/2] dt-bindings: pci: qcom,hawi-pcie: Add Maili PCIe compatible
From: Manivannan Sadhasivam @ 2026-07-07 4:53 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Vivek Pernamitta, Lorenzo Pieralisi, Krzysztof Wilczyński,
Rob Herring, Bjorn Helgaas, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Vinod Koul, Neil Armstrong, linux-arm-msm,
linux-pci, devicetree, linux-kernel, linux-phy
In-Reply-To: <9967f1a0-a9e3-4d62-b5df-7f625610a89d@kernel.org>
On Mon, Jul 06, 2026 at 07:35:52PM +0200, Krzysztof Kozlowski wrote:
> On 06/07/2026 18:36, Manivannan Sadhasivam wrote:
> > On Mon, Jul 06, 2026 at 08:46:41AM +0200, Krzysztof Kozlowski wrote:
> >> On Fri, Jul 03, 2026 at 05:38:40PM +0530, Vivek Pernamitta wrote:
> >>> Add qcom,maili-pcie as a compatible string that falls back to
> >>> qcom,hawi-pcie, as the Maili SoC reuses the Hawi PCIe controller IP.
> >>>
> >>> The Maili SoC is a derivative of Hawi and shares the same PCIe
> >>> controller architecture, allowing reuse of the existing Hawi PCIe
> >>> DT bindings.
> >>>
> >>> Signed-off-by: Vivek Pernamitta <vivek.pernamitta@oss.qualcomm.com>
> >>> ---
> >>> Dependencies:
> >>> - PCI: qcom: Add PCIe support for upcoming Hawi SoC
> >>> https://lore.kernel.org/all/20260625-hawi-pcie-v4-0-1a578603cd86@oss.qualcomm.com/
> >>
> >> Squash the patches then.
> >>
> >
> > But these are two independent SoC additions, isn't it?
>
> It's adding a single compatible, no? If a patch adding a single
> compatible cannot be done without multi-patchset dependencies making
> testing by tooling impossible, then probably that work should not be
> sent separately or even as separate patch. And I am not saying anything
> new because half a year ago (around Kaanapali and Glymur) I voiced
> strong opinion about that.
>
> But really, you do not need to add two compatibles in two separate patches.
>
Ok then. I'll squash this patch with Hawi patch which already got applied.
- Mani
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* Re: [PATCH 9/9] arm64: dts: qcom: shikra-(cqm/cqs/iqs)-evk: Enable PCIe PHY node
From: Sushrut Shree Trivedi @ 2026-07-07 5:21 UTC (permalink / raw)
To: Konrad Dybcio, Vinod Koul, Neil Armstrong, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Helgaas,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Andersson, Chaitanya Chundru,
Bartosz Golaszewski, Konrad Dybcio
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-pci
In-Reply-To: <6e42bc67-9a2f-4e64-bb49-30fd845263a2@oss.qualcomm.com>
On 7/1/2026 4:06 PM, Konrad Dybcio wrote:
> On 6/30/26 9:02 PM, Sushrut Shree Trivedi wrote:
>> Enable the PCIe PHY for the single PCIe intance on the Shikra
>> CQS, CQM and the IQS platforms.
>>
>> IQS platform uses a different powergrid than CQS/CQM which explain
>> the different PHY supplies for IQS variant.
>>
>> Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 7 +++++++
>> arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 7 +++++++
>> arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 7 +++++++
>> 3 files changed, 21 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
>> index 683b5245923b..06ad32041546 100644
>> --- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
>> +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
>> @@ -60,6 +60,13 @@ vreg_pmu_ch1: ldo4 {
>> };
>> };
>>
>> +&pcie_phy {
>> + vdda-phy-supply = <&pm4125_l13>;
>> + vdda-pll-supply = <&pm4125_l9>;
>> +
>> + status = "okay";
>> +};
> I think it makes sense to push the status=okay to the evk file
> (because we already describe the PCIe switch there) and only keep
> the supplies here (because they differ)
>
> Konrad
ACK'd.
Sushrut
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* Re: [PATCH 8/9] arm64: dts: qcom: shikra-evk: Add TC9563 PCIe switch node for PCIe
From: Sushrut Shree Trivedi @ 2026-07-07 5:22 UTC (permalink / raw)
To: Konrad Dybcio, Vinod Koul, Neil Armstrong, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Helgaas,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Andersson, Chaitanya Chundru,
Bartosz Golaszewski, Konrad Dybcio
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-pci
In-Reply-To: <2efcd4b6-0a99-4bb2-b428-4cb4805c20d1@oss.qualcomm.com>
On 7/1/2026 4:05 PM, Konrad Dybcio wrote:
> On 6/30/26 9:02 PM, Sushrut Shree Trivedi wrote:
>> Add a node for the TC9563 PCIe switch connected to PCIe. The switch
>> has three downstream ports.Two embedded Ethernet devices are present
>> on one of the downstream ports. All the ports present in the
>> node represent the downstream ports and embedded endpoints.
>>
>> Power to the TC9563 is supplied through two LDO regulators, which
>> are on by default and are added as fixed regulators. TC9563 can be
>> configured through I2C.
>>
>> Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
>> ---
> [...]
>
>> +&pcie {
>> + wake-gpios = <&tlmm 119 GPIO_ACTIVE_LOW>;
> This property belongs to the port node
>
> Please also mention in the commit message the reason for the
> PERST# pin remaining undescribed
>
> Konrad
ACK'd.
Sushrut
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* Re: [PATCH 7/9] arm64: dts: qcom: shikra: Add PCIe PHY and controller nodes
From: Sushrut Shree Trivedi @ 2026-07-07 5:23 UTC (permalink / raw)
To: Konrad Dybcio, Vinod Koul, Neil Armstrong, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Helgaas,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Andersson, Chaitanya Chundru,
Bartosz Golaszewski, Konrad Dybcio
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-pci
In-Reply-To: <12e86cc4-d96e-44f5-8c87-87a6df321115@oss.qualcomm.com>
On 7/1/2026 4:04 PM, Konrad Dybcio wrote:
> On 6/30/26 9:02 PM, Sushrut Shree Trivedi wrote:
>> Shikra supports single PCIe instance with 5GT/s x1 lane.
>> Add PCIe controller and PHY node for this single instance.
>>
>> Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
>> ---
> [...]
>
>
>> +
>> + max-link-speed = <2>;
> Please add a single-line comment right above explaining that the
> host supports higher speeds, but the attached PHY is only Gen2,
> so we need this manual limitation
>
> Konrad
ACK'd.
Sushrut
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* Re: [PATCH 1/2] dt-bindings: pci: qcom,hawi-pcie: Add Maili PCIe compatible
From: Manivannan Sadhasivam @ 2026-07-07 5:25 UTC (permalink / raw)
To: Vivek Pernamitta
Cc: Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
Bjorn Helgaas, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Vinod Koul, Neil Armstrong, linux-arm-msm, linux-pci, devicetree,
linux-kernel, linux-phy
In-Reply-To: <20260703-vdev_maili_dt_bindings-v1-1-c9df0916cd5e@oss.qualcomm.com>
On Fri, Jul 03, 2026 at 05:38:40PM +0530, Vivek Pernamitta wrote:
> Add qcom,maili-pcie as a compatible string that falls back to
> qcom,hawi-pcie, as the Maili SoC reuses the Hawi PCIe controller IP.
>
> The Maili SoC is a derivative of Hawi and shares the same PCIe
> controller architecture, allowing reuse of the existing Hawi PCIe
> DT bindings.
>
> Signed-off-by: Vivek Pernamitta <vivek.pernamitta@oss.qualcomm.com>
> ---
> Dependencies:
> - PCI: qcom: Add PCIe support for upcoming Hawi SoC
> https://lore.kernel.org/all/20260625-hawi-pcie-v4-0-1a578603cd86@oss.qualcomm.com/
Squashed with the Hawi patch, thanks!
- Mani
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* Re: [PATCH 3/9] dt-bindings: PCI: Add bindings for endpoint gpios
From: Sushrut Shree Trivedi @ 2026-07-07 5:26 UTC (permalink / raw)
To: Krzysztof Kozlowski, Vinod Koul, Neil Armstrong, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Helgaas,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Andersson, Chaitanya Chundru,
Bartosz Golaszewski, Konrad Dybcio
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-pci
In-Reply-To: <59c96d6e-95f4-4b03-b1a7-21e7cf6ce43d@kernel.org>
On 7/1/2026 11:57 AM, Krzysztof Kozlowski wrote:
> On 30/06/2026 21:02, Sushrut Shree Trivedi wrote:
>> toshiba,tx-amplitude-microvolt:
>> description:
>> Change Tx Margin setting for low power consumption.
>> @@ -104,7 +120,7 @@ examples:
>> #address-cells = <3>;
>> #size-cells = <2>;
>>
>> - pcie@0 {
>> + tc9563: pcie@0 {
> And you change indentation because?
>
>
> Just like the other patch, this wasn't tested, right?
>
>
> Best regards,
> Krzysztof
That was a miss from my end, we only ran schema checks.
Will be fixed in v2.
Sushrut
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* Re: [PATCH 2/9] dt-bindings: PCI: qcom: Document the Shikra PCIe Controller
From: Sushrut Shree Trivedi @ 2026-07-07 5:29 UTC (permalink / raw)
To: Krzysztof Kozlowski, Vinod Koul, Neil Armstrong, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Helgaas,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Andersson, Chaitanya Chundru,
Bartosz Golaszewski, Konrad Dybcio
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-pci
In-Reply-To: <dd9e68f3-c33d-47d1-871f-f085550b88b1@kernel.org>
On 7/1/2026 11:56 AM, Krzysztof Kozlowski wrote:
> On 30/06/2026 21:02, Sushrut Shree Trivedi wrote:
>> Add a dedicated schema for the PCIe controller found on the Shikra
>> platform.
>>
>> Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
>> ---
>> .../devicetree/bindings/pci/qcom,shikra-pcie.yaml | 211 +++++++++++++++++++++
>> 1 file changed, 211 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/pci/qcom,shikra-pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,shikra-pcie.yaml
>> new file mode 100644
>> index 000000000000..f9d1dba9dd2e
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/qcom,shikra-pcie.yaml
>> @@ -0,0 +1,211 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/pci/qcom,shikra-pcie.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm Shikra PCI Express Root Complex
>> +
>> +maintainers:
>> + - Bjorn Andersson <andersson@kernel.org>
>> + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
>> +
>> +description:
>> + Qualcomm Shikra SoC (and compatible) PCIe root complex controller is based on
>> + the Synopsys DesignWare PCIe IP.
>> +
>> +properties:
>> + compatible:
>> + const: qcom,shikra-pcie
>> +
>> + reg:
>> + minItems: 5
>> + maxItems: 6
> Same comments as other recent Qualcomm bindings. Don't invent stuff,
> take what was reviewed from the list so we won't have to repeat.
>
> ...
ACK'd. Will use latest binding patches as reference in v2.
>
>
>> + power-domains = <&gcc GCC_PCIE_GDSC>;
>> +
>> + max-link-speed = <2>;
>> +
>> + operating-points-v2 = <&pcie_opp_table>;
>> +
>> + status = "disabled";
> Drop, you never tested the binding in such case.
ACK'd.
>
>> +
>> + pcie_opp_table: opp-table {
>> + compatible = "operating-points-v2";
> Broken indent.
ACK'd.
>
>> +
>> + /* GEN 1 x1 */
>> + opp-2500000 {
>> + opp-hz = /bits/ 64 <2500000>;
>> + required-opps = <&rpmpd_opp_nom>;
>> + opp-peak-kBps = <250000 1>;
>> + opp-level = <1>;
>> + };
>> +
>> + /* GEN 2 x1 */
>> + opp-5000000 {
>> + opp-hz = /bits/ 64 <5000000>;
>> + required-opps = <&rpmpd_opp_nom>;
>> + opp-peak-kBps = <500000 1>;
>> + opp-level = <2>;
>> + };
>> + };
>> + };
>> + };
>>
>
> Best regards,
> Krzysztof
Sushrut
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* Re: [PATCH 3/9] dt-bindings: PCI: Add bindings for endpoint gpios
From: Sushrut Shree Trivedi @ 2026-07-07 5:39 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Helgaas, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Andersson,
Chaitanya Chundru, Bartosz Golaszewski, Konrad Dybcio,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-pci
In-Reply-To: <20260630192236.GA222338@bhelgaas>
On 7/1/2026 12:52 AM, Bjorn Helgaas wrote:
> On Wed, Jul 01, 2026 at 12:32:45AM +0530, Sushrut Shree Trivedi wrote:
>> Add devicetree bindings for TC9563 GPIO's which are
>> used to control endpoint power and reset.
> Include context in subject line. Regrettably, previous commits to
> toshiba,tc9563.yaml don't include that either, but I think something
> like this would be good:
>
> dt-bindings: PCI: toshiba,tc9563: Add endpoint GPIO bindings
>
> s/GPIO's/GPIOs/
>
> Wrap to fill 75 columns.
ACK'd.
Sushrut
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^ permalink raw reply
* Re: [PATCH 6/9] PCI/pwrctrl: tc9563: Add API to control endpoint power and reset
From: Sushrut Shree Trivedi @ 2026-07-07 5:40 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Helgaas, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Andersson,
Chaitanya Chundru, Bartosz Golaszewski, Konrad Dybcio,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-pci
In-Reply-To: <20260630192838.GA223662@bhelgaas>
On 7/1/2026 12:58 AM, Bjorn Helgaas wrote:
> On Wed, Jul 01, 2026 at 12:32:48AM +0530, Sushrut Shree Trivedi wrote:
>> Some platform utilise TC9563 GPIOs to enable power and
>> control reset of endpoints.
>>
>> This patch adds support to parse endpoint reset and power enable
>> gpios from each TC9563 port node in the devicetree. To configure
>> these GPIO's during the POWER ON sequence, two new API's are
>> introduced: tc9563_ep_pwr_en() and tc9563_ep_assert_deassert_reset().
> s/Some platform utilise/Some platforms utilise/
> s/This patch adds/Add/
> s/gpios/GPIOs/
>
> Add tc9563_ep_pwr_en() and tc9563_ep_assert_deassert_reset() to
> configure these GPIOs during the power-on sequence.
>
> Wrap to fill 75 columns.
ACK'd.
Sushrut
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^ permalink raw reply
* Re: [PATCH 7/9] arm64: dts: qcom: shikra: Add PCIe PHY and controller nodes
From: Sushrut Shree Trivedi @ 2026-07-07 5:40 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Helgaas, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Andersson,
Chaitanya Chundru, Bartosz Golaszewski, Konrad Dybcio,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-pci
In-Reply-To: <20260630192944.GA224708@bhelgaas>
On 7/1/2026 12:59 AM, Bjorn Helgaas wrote:
> On Wed, Jul 01, 2026 at 12:32:49AM +0530, Sushrut Shree Trivedi wrote:
>> Shikra supports single PCIe instance with 5GT/s x1 lane.
> s/ / /
> s/lane/link/
ACK'd
Sushrut
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^ permalink raw reply
* Re: [PATCH 8/9] arm64: dts: qcom: shikra-evk: Add TC9563 PCIe switch node for PCIe
From: Sushrut Shree Trivedi @ 2026-07-07 5:41 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Helgaas, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Andersson,
Chaitanya Chundru, Bartosz Golaszewski, Konrad Dybcio,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-pci
In-Reply-To: <20260630193059.GA225112@bhelgaas>
On 7/1/2026 1:00 AM, Bjorn Helgaas wrote:
> On Wed, Jul 01, 2026 at 12:32:50AM +0530, Sushrut Shree Trivedi wrote:
>> Add a node for the TC9563 PCIe switch connected to PCIe. The switch
>> has three downstream ports.Two embedded Ethernet devices are present
>> on one of the downstream ports. All the ports present in the
>> node represent the downstream ports and embedded endpoints.
>>
>> Power to the TC9563 is supplied through two LDO regulators, which
>> are on by default and are added as fixed regulators. TC9563 can be
>> configured through I2C.
> s/ports.Two/ports. Two/
>
> Possibly subject doesn't need two uses of "PCIe".
ACK'd.
Sushrut
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* Re: [PATCH 2/9] dt-bindings: PCI: qcom: Document the Shikra PCIe Controller
From: Sushrut Shree Trivedi @ 2026-07-07 5:41 UTC (permalink / raw)
To: Rob Herring (Arm)
Cc: Lorenzo Pieralisi, Krzysztof Wilczyński, Konrad Dybcio,
Bjorn Andersson, Vinod Koul, Chaitanya Chundru, Bjorn Helgaas,
devicetree, Manivannan Sadhasivam, Krzysztof Kozlowski,
linux-kernel, linux-phy, linux-arm-msm, Conor Dooley,
Neil Armstrong, linux-pci, Bartosz Golaszewski
In-Reply-To: <178285172593.288348.3890129606237873483.robh@kernel.org>
On 7/1/2026 2:05 AM, Rob Herring (Arm) wrote:
> On Wed, 01 Jul 2026 00:32:44 +0530, Sushrut Shree Trivedi wrote:
>> Add a dedicated schema for the PCIe controller found on the Shikra
>> platform.
>>
>> Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
>> ---
>> .../devicetree/bindings/pci/qcom,shikra-pcie.yaml | 211 +++++++++++++++++++++
>> 1 file changed, 211 insertions(+)
>>
> My bot found errors running 'make dt_binding_check' on your patch:
>
> yamllint warnings/errors:
>
> dtschema/dtc warnings/errors:
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:57.29-36 Unexpected 'GIC_SPI'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:57.41-60 Unexpected 'IRQ_TYPE_LEVEL_HIGH'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:58.29-36 Unexpected 'GIC_SPI'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:58.41-60 Unexpected 'IRQ_TYPE_LEVEL_HIGH'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:59.29-36 Unexpected 'GIC_SPI'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:59.41-60 Unexpected 'IRQ_TYPE_LEVEL_HIGH'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:60.29-36 Unexpected 'GIC_SPI'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:60.41-60 Unexpected 'IRQ_TYPE_LEVEL_HIGH'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:61.29-36 Unexpected 'GIC_SPI'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:61.41-60 Unexpected 'IRQ_TYPE_LEVEL_HIGH'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:62.29-36 Unexpected 'GIC_SPI'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:62.41-60 Unexpected 'IRQ_TYPE_LEVEL_HIGH'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:63.29-36 Unexpected 'GIC_SPI'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:63.41-60 Unexpected 'IRQ_TYPE_LEVEL_HIGH'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:64.29-36 Unexpected 'GIC_SPI'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:64.41-60 Unexpected 'IRQ_TYPE_LEVEL_HIGH'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:65.29-36 Unexpected 'GIC_SPI'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:65.41-60 Unexpected 'IRQ_TYPE_LEVEL_HIGH'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:76.56-75 Unexpected 'IRQ_TYPE_LEVEL_HIGH'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:77.56-75 Unexpected 'IRQ_TYPE_LEVEL_HIGH'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:78.56-75 Unexpected 'IRQ_TYPE_LEVEL_HIGH'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:79.56-75 Unexpected 'IRQ_TYPE_LEVEL_HIGH'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:83.30-46 Unexpected 'GCC_PCIE_AUX_CLK'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:84.30-50 Unexpected 'GCC_PCIE_CFG_AHB_CLK'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:85.30-51 Unexpected 'GCC_PCIE_MSTR_AXI_CLK'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:86.30-50 Unexpected 'GCC_PCIE_SLV_AXI_CLK'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:87.30-54 Unexpected 'GCC_PCIE_SLV_Q2A_AXI_CLK'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:88.30-58 Unexpected 'GCC_DDRSS_MEMNOC_PCIE_SF_CLK'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:89.30-59 Unexpected 'GCC_PCIE_TILE_AXI_SYS_NOC_CLK'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:90.30-55 Unexpected 'GCC_QMIP_PCIE_CFG_AHB_CLK'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:100.39-55 Unexpected 'GCC_PCIE_AUX_CLK'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:103.44-58 Unexpected 'MASTER_PCIE2_0'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:103.59-73 Unexpected 'RPM_ALWAYS_TAG'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:104.40-53 Unexpected 'SLAVE_EBI_CH0'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:104.54-68 Unexpected 'RPM_ALWAYS_TAG'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:105.41-56 Unexpected 'MASTER_AMPSS_M0'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:105.57-71 Unexpected 'RPM_ACTIVE_TAG'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:106.43-56 Unexpected 'SLAVE_PCIE2_0'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:106.57-71 Unexpected 'RPM_ACTIVE_TAG'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:114.30-42 Unexpected 'GCC_PCIE_BCR'
> Lexical error: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dts:117.37-50 Unexpected 'GCC_PCIE_GDSC'
> FATAL ERROR: Syntax error parsing input tree
> make[2]: *** [scripts/Makefile.dtbs:140: Documentation/devicetree/bindings/pci/qcom,shikra-pcie.example.dtb] Error 1
> make[2]: *** Waiting for unfinished jobs....
> make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1669: dt_binding_check] Error 2
> make: *** [Makefile:248: __sub-make] Error 2
>
> doc reference errors (make refcheckdocs):
>
> See https://patchwork.kernel.org/project/devicetree/patch/20260701-shikra-upstream-v1-2-e1a721eb8943@oss.qualcomm.com
>
> The base for the series is generally the latest rc1. A different dependency
> should be noted in *this* patch.
>
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> date:
>
> pip3 install dtschema --upgrade
>
> Please check and re-submit after running the above command yourself. Note
> that DT_SCHEMA_FILES can be set to your schema file to speed up checking
> your schema. However, it must be unset to test all examples with your schema.
ACK'd.
Sushrut
>
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^ permalink raw reply
* Re: [PATCH 3/9] dt-bindings: PCI: Add bindings for endpoint gpios
From: Sushrut Shree Trivedi @ 2026-07-07 5:42 UTC (permalink / raw)
To: Rob Herring (Arm)
Cc: Krzysztof Wilczyński, Neil Armstrong, Konrad Dybcio,
linux-phy, linux-kernel, Conor Dooley, Bjorn Andersson,
Bartosz Golaszewski, Vinod Koul, linux-arm-msm,
Manivannan Sadhasivam, Krzysztof Kozlowski, Lorenzo Pieralisi,
Chaitanya Chundru, linux-pci, devicetree, Bjorn Helgaas
In-Reply-To: <178285172702.288391.13610342196466613275.robh@kernel.org>
On 7/1/2026 2:05 AM, Rob Herring (Arm) wrote:
> On Wed, 01 Jul 2026 00:32:45 +0530, Sushrut Shree Trivedi wrote:
>> Add devicetree bindings for TC9563 GPIO's which are
>> used to control endpoint power and reset.
>>
>> Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
>> ---
>> .../devicetree/bindings/pci/toshiba,tc9563.yaml | 22 +++++++++++++++++++++-
>> 1 file changed, 21 insertions(+), 1 deletion(-)
>>
> My bot found errors running 'make dt_binding_check' on your patch:
>
> yamllint warnings/errors:
> ./Documentation/devicetree/bindings/pci/toshiba,tc9563.yaml:32:9: [warning] wrong indentation: expected 4 but found 8 (indentation)
>
> dtschema/dtc warnings/errors:
>
> doc reference errors (make refcheckdocs):
>
> See https://patchwork.kernel.org/project/devicetree/patch/20260701-shikra-upstream-v1-3-e1a721eb8943@oss.qualcomm.com
>
> The base for the series is generally the latest rc1. A different dependency
> should be noted in *this* patch.
>
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> date:
>
> pip3 install dtschema --upgrade
>
> Please check and re-submit after running the above command yourself. Note
> that DT_SCHEMA_FILES can be set to your schema file to speed up checking
> your schema. However, it must be unset to test all examples with your schema.
ACK'd.
Sushrut
>
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* Re: [PATCH 1/2] dt-bindings: pci: qcom,hawi-pcie: Add Maili PCIe compatible
From: Krzysztof Kozlowski @ 2026-07-07 5:55 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Vivek Pernamitta, Lorenzo Pieralisi, Krzysztof Wilczyński,
Rob Herring, Bjorn Helgaas, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Vinod Koul, Neil Armstrong, linux-arm-msm,
linux-pci, devicetree, linux-kernel, linux-phy
In-Reply-To: <43b5xhqvnapamfv4aomid647kaxrudgjcbnnca23t3vxitv67t@njdlthj2oisa>
On 07/07/2026 06:53, Manivannan Sadhasivam wrote:
> On Mon, Jul 06, 2026 at 07:35:52PM +0200, Krzysztof Kozlowski wrote:
>> On 06/07/2026 18:36, Manivannan Sadhasivam wrote:
>>> On Mon, Jul 06, 2026 at 08:46:41AM +0200, Krzysztof Kozlowski wrote:
>>>> On Fri, Jul 03, 2026 at 05:38:40PM +0530, Vivek Pernamitta wrote:
>>>>> Add qcom,maili-pcie as a compatible string that falls back to
>>>>> qcom,hawi-pcie, as the Maili SoC reuses the Hawi PCIe controller IP.
>>>>>
>>>>> The Maili SoC is a derivative of Hawi and shares the same PCIe
>>>>> controller architecture, allowing reuse of the existing Hawi PCIe
>>>>> DT bindings.
>>>>>
>>>>> Signed-off-by: Vivek Pernamitta <vivek.pernamitta@oss.qualcomm.com>
>>>>> ---
>>>>> Dependencies:
>>>>> - PCI: qcom: Add PCIe support for upcoming Hawi SoC
>>>>> https://lore.kernel.org/all/20260625-hawi-pcie-v4-0-1a578603cd86@oss.qualcomm.com/
>>>>
>>>> Squash the patches then.
>>>>
>>>
>>> But these are two independent SoC additions, isn't it?
>>
>> It's adding a single compatible, no? If a patch adding a single
>> compatible cannot be done without multi-patchset dependencies making
>> testing by tooling impossible, then probably that work should not be
>> sent separately or even as separate patch. And I am not saying anything
>> new because half a year ago (around Kaanapali and Glymur) I voiced
>> strong opinion about that.
>>
>> But really, you do not need to add two compatibles in two separate patches.
>>
>
> Ok then. I'll squash this patch with Hawi patch which already got applied.
Applied? That's not what I had in mind. This mentions external
dependency, not something which was applied. Should be squashed there.
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH 2/9] dt-bindings: PCI: qcom: Document the Shikra PCIe Controller
From: Manivannan Sadhasivam @ 2026-07-07 6:01 UTC (permalink / raw)
To: Sushrut Shree Trivedi
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Helgaas, Lorenzo Pieralisi,
Krzysztof Wilczyński, Bjorn Andersson, Chaitanya Chundru,
Bartosz Golaszewski, Konrad Dybcio, linux-arm-msm, linux-phy,
devicetree, linux-kernel, linux-pci
In-Reply-To: <20260701-shikra-upstream-v1-2-e1a721eb8943@oss.qualcomm.com>
On Wed, Jul 01, 2026 at 12:32:44AM +0530, Sushrut Shree Trivedi wrote:
> Add a dedicated schema for the PCIe controller found on the Shikra
> platform.
>
> Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
> ---
> .../devicetree/bindings/pci/qcom,shikra-pcie.yaml | 211 +++++++++++++++++++++
> 1 file changed, 211 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,shikra-pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,shikra-pcie.yaml
> new file mode 100644
> index 000000000000..f9d1dba9dd2e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/qcom,shikra-pcie.yaml
> @@ -0,0 +1,211 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/qcom,shikra-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Shikra PCI Express Root Complex
> +
> +maintainers:
> + - Bjorn Andersson <andersson@kernel.org>
> + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> +
> +description:
> + Qualcomm Shikra SoC (and compatible) PCIe root complex controller is based on
s/PCIe root complex controller/PCIe Root Complex
> + the Synopsys DesignWare PCIe IP.
> +
> +properties:
> + compatible:
> + const: qcom,shikra-pcie
> +
> + reg:
> + minItems: 5
> + maxItems: 6
> +
> + reg-names:
> + minItems: 5
> + items:
> + - const: parf # Qualcomm specific registers
> + - const: dbi # DesignWare PCIe registers
> + - const: elbi # External local bus interface registers
> + - const: atu # ATU address space
> + - const: config # PCIe configuration space
> + - const: mhi # MHI registers
MHI is not optional.
> +
> + clocks:
> + minItems: 7
> + maxItems: 9
> +
> + clock-names:
> + minItems: 7
> + items:
> + - const: aux # Auxiliary clock
> + - const: cfg # Configuration clock
> + - const: bus_master # Master AXI clock
> + - const: bus_slave # Slave AXI clock
> + - const: slave_q2a # Slave Q2A clock
> + - const: ddrss_memnoc_pcie # PCIe SF MEMNOC clock
> + - const: tile # PCIe tile SYS NoC clock
> + - const: qmip_pcie_ahb # QMIP PCIe AHB clock
Why optional clocks?
> +
> + interrupts:
> + minItems: 8
> + maxItems: 9
> +
> + interrupt-names:
> + minItems: 8
> + items:
> + - const: msi0
> + - const: msi1
> + - const: msi2
> + - const: msi3
> + - const: msi4
> + - const: msi5
> + - const: msi6
> + - const: msi7
> + - const: global
Same here, why global interrupt is optional?
> +
> + resets:
> + minItems: 1
> + maxItems: 2
> +
> + reset-names:
> + minItems: 1
> + items:
> + - const: pci # PCIe core reset
> + - const: link_down # PCIe link down reset
Same here.
> +
> +required:
> + - power-domains
> + - resets
> + - reset-names
> +
> +allOf:
> + - $ref: qcom,pcie-common.yaml#
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
> + #include <dt-bindings/clock/qcom,qcm2290-gpucc.h>
What are these includes for?
> + #include <dt-bindings/clock/qcom,rpmcc.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
Get rid of 'soc' node.
> + pcie@45e8000 {
> + device_type = "pci";
> + compatible = "qcom,shikra-pcie";
> + reg = <0x0 0x045e8000 0x0 0x3000>,
> + <0x0 0x60000000 0x0 0xf1d>,
> + <0x0 0x60000f20 0x0 0xa8>,
> + <0x0 0x60001000 0x0 0x1000>,
> + <0x0 0x60100000 0x0 0x100000>,
> + <0x0 0x045eb000 0x0 0x1000>;
> + reg-names = "parf",
> + "dbi",
> + "elbi",
> + "atu",
> + "config",
> + "mhi";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
> + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>,
> + <0x03000000 0x4 0x00000000 0x4 0x00000000 0x3 0x0000000>;
> + bus-range = <0x00 0xff>;
> +
> + linux,pci-domain = <0>;
> + num-lanes = <1>;
> +
> + interrupts = <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH 0>;
> + interrupt-names = "msi0",
> + "msi1",
> + "msi2",
> + "msi3",
> + "msi4",
> + "msi5",
> + "msi6",
> + "msi7",
> + "global";
> +
> + interrupt-map = <0 0 0 1 &intc 0 0 0 499 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 2 &intc 0 0 0 500 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 3 &intc 0 0 0 501 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 4 &intc 0 0 0 502 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + #interrupt-cells = <1>;
> +
> + clocks = <&gcc GCC_PCIE_AUX_CLK>,
> + <&gcc GCC_PCIE_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_MSTR_AXI_CLK>,
> + <&gcc GCC_PCIE_SLV_AXI_CLK>,
> + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
> + <&gcc GCC_DDRSS_MEMNOC_PCIE_SF_CLK>,
> + <&gcc GCC_PCIE_TILE_AXI_SYS_NOC_CLK>,
> + <&gcc GCC_QMIP_PCIE_CFG_AHB_CLK>;
> + clock-names = "aux",
> + "cfg",
> + "bus_master",
> + "bus_slave",
> + "slave_q2a",
> + "ddrss_memnoc_pcie",
> + "tile",
> + "qmip_pcie_ahb";
> +
> + assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>;
> + assigned-clock-rates = <19200000>;
> +
> + interconnects = <&system_noc MASTER_PCIE2_0 RPM_ALWAYS_TAG
> + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
> + <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
> + &config_noc SLAVE_PCIE2_0 RPM_ACTIVE_TAG>;
> +
> + interconnect-names = "pcie-mem",
> + "cpu-pcie";
> +
> + iommu-map = <0x0 &apps_smmu 0x800 0x1>,
> + <0x100 &apps_smmu 0x801 0x1>;
> +
> + resets = <&gcc GCC_PCIE_BCR>;
> + reset-names = "pci";
> +
> + power-domains = <&gcc GCC_PCIE_GDSC>;
> +
> + max-link-speed = <2>;
You don't need 'max-link-speed' unless you want to limit the link speed.
> +
> + operating-points-v2 = <&pcie_opp_table>;
> +
> + status = "disabled";
> +
No, you should not disable the example.
> + pcie_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + /* GEN 1 x1 */
> + opp-2500000 {
> + opp-hz = /bits/ 64 <2500000>;
> + required-opps = <&rpmpd_opp_nom>;
Are you sure that the power domain need to be in NOM for 2.5 GT/s?
> + opp-peak-kBps = <250000 1>;
> + opp-level = <1>;
> + };
> +
> + /* GEN 2 x1 */
> + opp-5000000 {
> + opp-hz = /bits/ 64 <5000000>;
> + required-opps = <&rpmpd_opp_nom>;
Same here.
> + opp-peak-kBps = <500000 1>;
> + opp-level = <2>;
> + };
> + };
Odd indent.
- Mani
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* Re: [PATCH 3/9] dt-bindings: PCI: Add bindings for endpoint gpios
From: Manivannan Sadhasivam @ 2026-07-07 6:48 UTC (permalink / raw)
To: Sushrut Shree Trivedi
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Helgaas, Lorenzo Pieralisi,
Krzysztof Wilczyński, Bjorn Andersson, Chaitanya Chundru,
Bartosz Golaszewski, Konrad Dybcio, linux-arm-msm, linux-phy,
devicetree, linux-kernel, linux-pci
In-Reply-To: <20260701-shikra-upstream-v1-3-e1a721eb8943@oss.qualcomm.com>
On Wed, Jul 01, 2026 at 12:32:45AM +0530, Sushrut Shree Trivedi wrote:
Use proper prefix for the subject.
> Add devicetree bindings for TC9563 GPIO's which are
> used to control endpoint power and reset.
>
> Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
> ---
> .../devicetree/bindings/pci/toshiba,tc9563.yaml | 22 +++++++++++++++++++++-
> 1 file changed, 21 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/toshiba,tc9563.yaml b/Documentation/devicetree/bindings/pci/toshiba,tc9563.yaml
> index b3ad05d90201..f9f71f28aa92 100644
> --- a/Documentation/devicetree/bindings/pci/toshiba,tc9563.yaml
> +++ b/Documentation/devicetree/bindings/pci/toshiba,tc9563.yaml
> @@ -26,6 +26,11 @@ properties:
> reg:
> maxItems: 1
>
> + gpio-controller: true
> +
> + '#gpio-cells':
> + const: 2
Fix indent.
> +
> resx-gpios:
> maxItems: 1
> description:
> @@ -69,6 +74,17 @@ $defs:
> type: object
>
> properties:
> + reset-gpios:
> + description:
> + Specify the TC9563 GPIO used to reset the endpoint
> + connected to the particular TC9563 downstream port.
> +
This the PERST# signal, isn't it? If so, mention it as-is.
> + ep-pwr-en-gpios:
> + description:
> + Specify the TC9563 GPIO used for enabling power to
> + the endpoint connected to the particular TC9563
> + downstream port.
> +
So this GPIO controls 3.3v supply to the endpoint? If so, it should be described
as a GPIO controlled regulator:
vreg_pcie_3v3: regulator-pcie-3v3 {
compatible = "regulator-fixed";
...
gpio = <&tc9563 2 GPIO_ACTIVE_HIGH>;
...
};
And then you should let the pwrctrl driver control the upstream port. The upside
here is that the pwrctrl driver already controls both 3.3v and reset-gpios
(PERST#). So you do not need to have any change in the TC9563 driver.
- Mani
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* Re: [PATCH 1/2] dt-bindings: pci: qcom,hawi-pcie: Add Maili PCIe compatible
From: Manivannan Sadhasivam @ 2026-07-07 7:19 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Vivek Pernamitta, Lorenzo Pieralisi, Krzysztof Wilczyński,
Rob Herring, Bjorn Helgaas, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Vinod Koul, Neil Armstrong, linux-arm-msm,
linux-pci, devicetree, linux-kernel, linux-phy
In-Reply-To: <92b7efac-32c3-4a89-9b08-55da294a6bc0@kernel.org>
On Tue, Jul 07, 2026 at 07:55:45AM +0200, Krzysztof Kozlowski wrote:
> On 07/07/2026 06:53, Manivannan Sadhasivam wrote:
> > On Mon, Jul 06, 2026 at 07:35:52PM +0200, Krzysztof Kozlowski wrote:
> >> On 06/07/2026 18:36, Manivannan Sadhasivam wrote:
> >>> On Mon, Jul 06, 2026 at 08:46:41AM +0200, Krzysztof Kozlowski wrote:
> >>>> On Fri, Jul 03, 2026 at 05:38:40PM +0530, Vivek Pernamitta wrote:
> >>>>> Add qcom,maili-pcie as a compatible string that falls back to
> >>>>> qcom,hawi-pcie, as the Maili SoC reuses the Hawi PCIe controller IP.
> >>>>>
> >>>>> The Maili SoC is a derivative of Hawi and shares the same PCIe
> >>>>> controller architecture, allowing reuse of the existing Hawi PCIe
> >>>>> DT bindings.
> >>>>>
> >>>>> Signed-off-by: Vivek Pernamitta <vivek.pernamitta@oss.qualcomm.com>
> >>>>> ---
> >>>>> Dependencies:
> >>>>> - PCI: qcom: Add PCIe support for upcoming Hawi SoC
> >>>>> https://lore.kernel.org/all/20260625-hawi-pcie-v4-0-1a578603cd86@oss.qualcomm.com/
> >>>>
> >>>> Squash the patches then.
> >>>>
> >>>
> >>> But these are two independent SoC additions, isn't it?
> >>
> >> It's adding a single compatible, no? If a patch adding a single
> >> compatible cannot be done without multi-patchset dependencies making
> >> testing by tooling impossible, then probably that work should not be
> >> sent separately or even as separate patch. And I am not saying anything
> >> new because half a year ago (around Kaanapali and Glymur) I voiced
> >> strong opinion about that.
> >>
> >> But really, you do not need to add two compatibles in two separate patches.
> >>
> >
> > Ok then. I'll squash this patch with Hawi patch which already got applied.
>
> Applied? That's not what I had in mind. This mentions external
> dependency, not something which was applied. Should be squashed there.
>
I merged the dependency for 7.3 before looking at this series. So now, squashed
this patch with that.
- Mani
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* Re: [PATCH v2 2/3] phy: qcom-qusb2: correst PHY description for IPQ6018
From: Konrad Dybcio @ 2026-07-07 7:39 UTC (permalink / raw)
To: Dmitry Baryshkov, Vinod Koul, Neil Armstrong, Kathiravan T,
Baruch Siach, Dmitry Baryshkov, Krishna Kurapati, Manu Gautam,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, linux-kernel
In-Reply-To: <20260706-fix-qusb2-v2-2-8d9cd73b1db7@oss.qualcomm.com>
On 7/6/26 3:53 PM, Dmitry Baryshkov wrote:
> Qualcomm IPQ6018 doesn't need to reach power collapse or retention of
> the USB voltage rails, so autoresume is not used on that platform.
> Instead of programming a fake register bit (BIT(0) of TEST1, while the
> QUSB2 platforms on that platform should use BIT(3) of TEST_CTRL),
> explicitly disable autoresume programming on these devices via the flag
> in the platform data.
>
> Fixes: 2cfbe6765b7a ("phy: qcom-qusb2: add QUSB2 support for IPQ6018")
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
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* [PATCH v10 00/11] SPMI: Implement sub-devices and migrate drivers
From: AngeloGioacchino Del Regno @ 2026-07-07 8:37 UTC (permalink / raw)
To: jic23, sboyd
Cc: dlechner, nuno.sa, andy, arnd, gregkh, srini, vkoul,
neil.armstrong, sre, angelogioacchino.delregno, krzk,
dmitry.baryshkov, quic_wcheng, melody.olvera, quic_nsekar,
ivo.ivanov.ivanov1, abelvesa, luca.weiss, konrad.dybcio,
mitltlatltl, krishna.kurapati, linux-arm-msm, linux-iio,
linux-kernel, linux-phy, linux-pm, kernel
Changes in v10:
- Add use-after-free fix rebased to before this series, as the v1 of
that did not apply cleanly on a tree without this series applied
- Replace unsafe to_spmi_device() with spmi_find_device_by_of_node() (Sashiko)
- Fix -Wformat warning in dev_set_name call (Sashiko)
Changes in v9:
- Added check for dev->parent where missing (Sashiko)
- Changed %d to %u in dev_set_name() call as arg is unsigned (Sashiko)
- Propagating error code from devm_regmap_init_spmi_ext() instead of
returning -ENODEV in phy-qcom-eusb2-repeater.c (Sashiko)
- Rebased over next-20260605 (no conflicts anyway)
Changes in v8:
- Renamed *res to *sub_sdev in devm_spmi_subdevice_remove() (Andy)
- Changed kerneldoc wording to "error pointer" for function
spmi_subdevice_alloc_and_add() (Andy)
- Shuffled around some assignments in spmi_subdevice_alloc_and_add() (Andy)
- Used device_property_read_u32() instead of of_property_read_u32()
in all of the migrated drivers (Andy)
- Changed .max_register field in all of the migrated drivers from
0x100 to 0xff (Andy)
- Kept `sta1` declaration in reversed xmas tree order in function
iadc_poll_wait_eoc() of qcom-spmi-iadc.c (Andy)
Changes in v7:
- Added commit to cleanup redundant dev_name() in the pre-existing
spmi_device_add() function
- Added commit removing unneeded goto and improving spmi_device_add()
readability by returning error in error path, and explicitly zero
for success at the end.
Changes in v6:
- Added commit to convert spmi.c to %pe error format and used
%pe error format in spmi_subdevice code as wanted by Uwe Kleine-Konig
Changes in v5:
- Changed dev_err to dev_err_probe in qcom-spmi-sdam (and done
that even though I disagree - because I wanted this series to
*exclusively* introduce the minimum required changes to
migrate to the new API, but okay, whatever....!);
- Added missing REGMAP dependency in Kconfig for qcom-spmi-sdam,
phy-qcom-eusb2-repeater and qcom-coincell to resolve build
issues when the already allowed COMPILE_TEST is enabled
as pointed out by the test robot's randconfig builds.
Changes in v4:
- Added selection of REGMAP_SPMI in Kconfig for qcom-coincell and
for phy-qcom-eusb2-repeater to resolve undefined references when
compiled with some randconfig
Changes in v3:
- Fixed importing "SPMI" namespace in spmi-devres.c
- Removed all instances of defensive programming, as pointed out by
jic23 and Sebastian
- Removed explicit casting as pointed out by jic23
- Moved ida_free call to spmi_subdev_release() and simplified error
handling in spmi_subdevice_alloc_and_add() as pointed out by jic23
Changes in v2:
- Fixed missing `sparent` initialization in phy-qcom-eusb2-repeater
- Changed val_bits to 8 in all Qualcomm drivers to ensure
compatibility as suggested by Casey
- Added struct device pointer in all conversion commits as suggested
by Andy
- Exported newly introduced functions with a new "SPMI" namespace
and imported the same in all converted drivers as suggested by Andy
- Added missing error checking for dev_set_name() call in spmi.c
as suggested by Andy
- Added comma to last entry of regmap_config as suggested by Andy
While adding support for newer MediaTek platforms, featuring complex
SPMI PMICs, I've seen that those SPMI-connected chips are internally
divided in various IP blocks, reachable in specific contiguous address
ranges... more or less like a MMIO, but over a slow SPMI bus instead.
I recalled that Qualcomm had something similar... and upon checking a
couple of devicetrees, yeah - indeed it's the same over there.
What I've seen then is a common pattern of reading the "reg" property
from devicetree in a struct member and then either
A. Wrapping regmap_{read/write/etc}() calls in a function that adds
the register base with "base + ..register", like it's done with
writel()/readl() calls; or
B. Doing the same as A. but without wrapper functions.
Even though that works just fine, in my opinion it's wrong.
The regmap API is way more complex than MMIO-only readl()/writel()
functions for multiple reasons (including supporting multiple busses
like SPMI, of course) - but everyone seemed to forget that regmap
can manage register base offsets transparently and automatically in
its API functions by simply adding a `reg_base` to the regmap_config
structure, which is used for initializing a `struct regmap`.
So, here we go: this series implements the software concept of an SPMI
Sub-Device (which, well, also reflects how Qualcomm and MediaTek's
actual hardware is laid out anyway).
SPMI Controller
| ______
| / Sub-Device 1
V /
SPMI Device (PMIC) ----------- Sub-Device 2
\
\______ Sub-Device 3
As per this implementation, an SPMI Sub-Device can be allocated/created
and added in any driver that implements a... well.. subdevice (!) with
an SPMI "main" device as its parent: this allows to create and finally
to correctly configure a regmap that is specific to the sub-device,
operating on its specific address range and reading, and writing, to
its registers with the regmap API taking care of adding the base address
of a sub-device's registers as per regmap API design.
All of the SPMI Sub-Devices are therefore added as children of the SPMI
Device (usually a PMIC), as communication depends on the PMIC's SPMI bus
to be available (and the PMIC to be up and running, of course).
Summarizing the dependency chain (which is obvious to whoever knows what
is going on with Qualcomm and/or MediaTek SPMI PMICs):
"SPMI Sub-Device x...N" are children "SPMI Device"
"SPMI Device" is a child of "SPMI Controller"
(that was just another way to say the same thing as the graph above anyway).
Along with the new SPMI Sub-Device registration functions, I have also
performed a conversion of some Qualcomm SPMI drivers and only where the
actual conversion was trivial.
I haven't included any conversion of more complex Qualcomm SPMI drivers
because I don't have the required bandwidth to do so (and besides, I think,
but haven't exactly verified, that some of those require SoCs that I don't
have for testing anyway).
AngeloGioacchino Del Regno (10):
spmi: Remove redundant dev_name() print in spmi_device_add()
spmi: Print error status with %pe format
spmi: Remove unneeded goto in spmi_device_add() error path
spmi: Implement spmi_subdevice_alloc_and_add() and devm variant
nvmem: qcom-spmi-sdam: Migrate to devm_spmi_subdevice_alloc_and_add()
power: reset: qcom-pon: Migrate to devm_spmi_subdevice_alloc_and_add()
phy: qualcomm: eusb2-repeater: Migrate to
devm_spmi_subdevice_alloc_and_add()
misc: qcom-coincell: Migrate to devm_spmi_subdevice_alloc_and_add()
iio: adc: qcom-spmi-iadc: Migrate to
devm_spmi_subdevice_alloc_and_add()
iio: adc: qcom-spmi-iadc: Remove regmap R/W wrapper functions
drivers/iio/adc/qcom-spmi-iadc.c | 118 ++++++++----------
drivers/misc/Kconfig | 2 +
drivers/misc/qcom-coincell.c | 45 +++++--
drivers/nvmem/Kconfig | 1 +
drivers/nvmem/qcom-spmi-sdam.c | 38 ++++--
drivers/phy/qualcomm/Kconfig | 2 +
.../phy/qualcomm/phy-qcom-eusb2-repeater.c | 54 ++++----
drivers/power/reset/qcom-pon.c | 33 +++--
drivers/spmi/spmi-devres.c | 24 ++++
drivers/spmi/spmi.c | 95 ++++++++++++--
include/linux/spmi.h | 16 +++
11 files changed, 299 insertions(+), 129 deletions(-)
--
2.54.0
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* [PATCH v10 02/11] spmi: Remove redundant dev_name() print in spmi_device_add()
From: AngeloGioacchino Del Regno @ 2026-07-07 8:37 UTC (permalink / raw)
To: jic23, sboyd
Cc: dlechner, nuno.sa, andy, arnd, gregkh, srini, vkoul,
neil.armstrong, sre, angelogioacchino.delregno, krzk,
dmitry.baryshkov, quic_wcheng, melody.olvera, quic_nsekar,
ivo.ivanov.ivanov1, abelvesa, luca.weiss, konrad.dybcio,
mitltlatltl, krishna.kurapati, linux-arm-msm, linux-iio,
linux-kernel, linux-phy, linux-pm, kernel, Andy Shevchenko
In-Reply-To: <20260707083730.33977-1-angelogioacchino.delregno@collabora.com>
Function spmi_device_add() uses dev_{dbg,err}() for respectively
debug and error prints, and passes the same device pointer as both
the dev_{dbg,err}() parameters and to a dev_name() that is part of
the actual message.
This means that the device name gets printed twice!
Remove the redundant dev_name() from the messages.
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/spmi/spmi.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/spmi/spmi.c b/drivers/spmi/spmi.c
index 6e701aff6045..cf33262eaeb2 100644
--- a/drivers/spmi/spmi.c
+++ b/drivers/spmi/spmi.c
@@ -68,12 +68,11 @@ int spmi_device_add(struct spmi_device *sdev)
err = device_add(&sdev->dev);
if (err < 0) {
- dev_err(&sdev->dev, "Can't add %s, status %d\n",
- dev_name(&sdev->dev), err);
+ dev_err(&sdev->dev, "Can't add device, status %d\n", err);
goto err_device_add;
}
- dev_dbg(&sdev->dev, "device %s registered\n", dev_name(&sdev->dev));
+ dev_dbg(&sdev->dev, "device registered\n");
err_device_add:
return err;
--
2.54.0
--
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* [PATCH v10 01/11] spmi: Fix potential use-after-free by grabbing of_node reference
From: AngeloGioacchino Del Regno @ 2026-07-07 8:37 UTC (permalink / raw)
To: jic23, sboyd
Cc: dlechner, nuno.sa, andy, arnd, gregkh, srini, vkoul,
neil.armstrong, sre, angelogioacchino.delregno, krzk,
dmitry.baryshkov, quic_wcheng, melody.olvera, quic_nsekar,
ivo.ivanov.ivanov1, abelvesa, luca.weiss, konrad.dybcio,
mitltlatltl, krishna.kurapati, linux-arm-msm, linux-iio,
linux-kernel, linux-phy, linux-pm, kernel, stable, Sashiko Bot
In-Reply-To: <20260707083730.33977-1-angelogioacchino.delregno@collabora.com>
As noticed by Sashiko during a review run of an unrelated patch,
in of_spmi_register_devices(), for_each_available_child_of_node()
is used to loop through children, and to also assign a node to a
newly created SPMI child device.
Problem is that the refcount is dropped at every iteration so, in
the specific case of DT overlays, a use-after-free may occur when
an overlay is dynamically unloaded!
To resolve this, increase the of_node refcount when assigning (in
function of_spmi_register_devices) and release the reference in
spmi_device_remove().
Fixes: bc32bbd04011 ("spmi: Set fwnode for spmi devices")
Cc: stable@vger.kernel.org
Reported-by: Sashiko Bot <sashiko-bot@kernel.org>
Closes: https://sashiko.dev/#/patchset/20260608100949.36309-1-angelogioacchino.delregno@collabora.com?part=2
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/spmi/spmi.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/spmi/spmi.c b/drivers/spmi/spmi.c
index 57b7c0cb4240..6e701aff6045 100644
--- a/drivers/spmi/spmi.c
+++ b/drivers/spmi/spmi.c
@@ -86,6 +86,9 @@ EXPORT_SYMBOL_GPL(spmi_device_add);
*/
void spmi_device_remove(struct spmi_device *sdev)
{
+ if (IS_ENABLED(CONFIG_OF))
+ of_node_put(sdev->dev.of_node);
+
device_unregister(&sdev->dev);
}
EXPORT_SYMBOL_GPL(spmi_device_remove);
@@ -517,13 +520,14 @@ static void of_spmi_register_devices(struct spmi_controller *ctrl)
if (!sdev)
continue;
- device_set_node(&sdev->dev, of_fwnode_handle(node));
+ device_set_node(&sdev->dev, of_fwnode_handle(of_node_get(node)));
sdev->usid = (u8)reg[0];
err = spmi_device_add(sdev);
if (err) {
dev_err(&sdev->dev,
"failure adding device. status %d\n", err);
+ of_node_put(node);
spmi_device_put(sdev);
}
}
--
2.54.0
--
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