Re: [PATCH v2 2/3] arm64: dts: qcom: monaco: add CSI2 PHY common-phy providers

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
- [High] arm64: dts: qcom: monaco: undocumented qcom,qcs8300-csi2-phy compatible
- [High] arm64: dts: qcom: monaco: single power-domain on csiphy0..2 causes -EEXIST
- [Medium] arm64: dts: qcom: monaco: unsupported 300 MHz OPP in csiphy_opp_table
- [Low] arm64: dts: qcom: monaco: csiphy_opp_table placed inside simple-bus soc@0
--

commit 59d7abe471847dc33609b30800a267639ba8de2a
Author: Anusha Arun Nandi <anusha.nandi@oss.qualcomm.com>

arm64: dts: qcom: monaco: add CSI2 PHY common-phy providers

This commit adds standalone qcom,qcs8300-csi2-phy provider nodes (csiphy0..2)
and an opp-table-csiphy node to monaco.dtsi so boards can wire sensors through
the generic PHY path rather than the legacy CAMSS PHY binding.

> diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
> index 35fbee63d4c65..9585bc723fc40 100644
> --- a/arch/arm64/boot/dts/qcom/monaco.dtsi
> +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
> @@ -5577,6 +5577,120 @@ cci2_i2c1: i2c-bus@1 {
>  			};
>  		};
>  
> +		csiphy0: phy@ac9c000 {
> +			compatible = "qcom,qcs8300-csi2-phy";
> +			reg = <0x0 0x0ac9c000 0x0 0x2000>;
> +
> +			clocks = <&camcc CAM_CC_CSIPHY0_CLK>,
> +				 <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
> +				 <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>;
> +			clock-names = "core",
> +				      "timer",
> +				      "csiphy_rx";

[Severity: High]
As reported by Sashiko on v1 [1], is there a binding update and driver support
for "qcom,qcs8300-csi2-phy" that should precede this change?

Currently, Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
only documents qcom,x1e80100-csi2-phy and qcom,glymur-csi2-phy, and
phy_qcom_mipi_csi2_of_match_table[] in
drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c only matches
"qcom,x1e80100-csi2-phy":

    static const struct of_device_id phy_qcom_mipi_csi2_of_match_table[] = {
            { .compatible = "qcom,x1e80100-csi2-phy", .data = &mipi_csi2_dphy_4nm_x1e },
            { }
    };

When a board or overlay enables csiphy0, csiphy1, or csiphy2 and wires a
sensor through it, camss_detect_legacy_phy() selects the non-legacy path and
camss_init_subdevices() -> msm_csiphy_subdev_init() calls
devm_phy_get_by_of_node(). Because no PHY provider driver binds to
"qcom,qcs8300-csi2-phy", devm_phy_get_by_of_node() will return -EPROBE_DEFER
indefinitely.

Additionally, csiphy0..2 specify three clocks ("core", "timer", "csiphy_rx"),
whereas the sibling SA8775P CSIPHY nodes in lemans.dtsi specify two clocks
("core", "timer") and qcom,x1e80100-csi2-phy.yaml specifies "core", "timer",
and "ahb", while phy_qcom_mipi_csi2_probe() enforces an exact match between
the DT clock count and soc_cfg->num_clk.

> +
> +			interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>;
> +
> +			operating-points-v2 = <&csiphy_opp_table>;
> +
> +			power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> +			power-domain-names = "top";

[Severity: High]
Will specifying only a single power-domains entry on csiphy0, csiphy1, and
csiphy2 cause phy_qcom_mipi_csi2_probe() to fail with -EEXIST?

When a platform device has a single power-domains entry in DT,
platform_probe() calls dev_pm_domain_attach() -> genpd_dev_pm_attach(), which
attaches that domain to dev->pm_domain before invoking the driver's probe()
callback:

    if (of_count_phandle_with_args(dev->of_node, "power-domains",
                                   "#power-domain-cells") != 1)
            return 0;

    return __genpd_dev_pm_attach(dev, dev, 0, 1, true);

When phy_qcom_mipi_csi2_probe() subsequently calls
phy_qcom_mipi_csi2_attach_pm_domains() -> devm_pm_domain_attach_list() ->
dev_pm_domain_attach_list(), it rejects the device because dev->pm_domain is
already set:

    if (dev->pm_domain)
            return -EEXIST;

Furthermore, Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
and drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c expect three power
domains ("top", "mmcx", and "mx").

[ ... ]

> +		csiphy_opp_table: opp-table-csiphy {
> +			compatible = "operating-points-v2";
> +
> +			opp-300000000 {
> +				opp-hz = /bits/ 64 <300000000>;
> +			};

[Severity: Medium]
As reported by Sashiko on v1 [2], does the QCS8300 CAMCC hardware and clock
driver support a 300 MHz operating point for the CSIPHY clocks?

In drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c,
phy_qcom_mipi_csi2_set_clock_rates() selects the ceiling OPP for link_freq / 4
and calls dev_pm_opp_set_rate() on the "core" clock (CAM_CC_CSIPHY0..2_CLK).
However, in drivers/clk/qcom/camcc-sa8775p.c (which handles
qcom,qcs8300-camcc), cam_cc_csiphy0..2_clk and cam_cc_csi0..2phytimer_clk_src
use ftbl_cam_cc_cphy_rx_clk_src, which only defines a 400 MHz frequency entry:

    static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
            F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
            { }
    };

Similarly, csiphy_res_8775p in drivers/media/platform/qcom/camss/camss.c only
lists 400000000 Hz for the QCS8300 CSIPHY clocks. Should opp-300000000 be
dropped from csiphy_opp_table?

> +
> +			opp-400000000 {
> +				opp-hz = /bits/ 64 <400000000>;
> +			};
> +		};
> +
>  		camss: isp@ac78000 {
>  			compatible = "qcom,qcs8300-camss";

[Severity: Low]
As reported by Sashiko on v1 [3], should csiphy_opp_table (opp-table-csiphy)
be placed under the root node (like cpu0_opp_table and qup_opp_table in
monaco.dtsi) or inside each PHY node rather than directly under soc@0?

Because soc@0 is a simple-bus, placing opp-table-csiphy directly inside it
without a reg or ranges property triggers a DTC simple_bus_reg warning in
check_simple_bus_reg() ("missing or empty reg/ranges property") and fails
simple-bus.yaml validation in dtbs_check. Also, phy@ac9c000, phy@ac9e000, and
phy@aca0000 are placed before isp@ac78000 rather than after it in ascending
unit-address order.

[1] https://lore.kernel.org/r/20261017001116.2318647-3-anusha.nandi@oss.qualcomm.com
[2] https://lore.kernel.org/r/20261017001116.2318647-3-anusha.nandi@oss.qualcomm.com
[3] https://lore.kernel.org/r/20261017001116.2318647-3-anusha.nandi@oss.qualcomm.com

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Sashiko AI review · https://sashiko.dev/#/patchset/20261103221026.3662383-1-anusha.nandi@oss.qualcomm.com?part=2

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