[PATCH v2 0/3] arm64: dts: qcom: Add CSI2 PHY common-phy providers for SA8775P, QCS8300 and SC7280

[PATCH v2 0/3] arm64: dts: qcom: Add CSI2 PHY common-phy providers for SA8775P, QCS8300 and SC7280

[Anusha Arun Nandi]

This series adds devicetree nodes for the generic Qualcomm MIPI CSI2
PHY driver on the three platforms whose compatibles/soc_cfg were added
by the companion "phy: qcom-mipi-csi2: Add D-PHY support for SA8775P,
QCS8300 and SC7280".

Each CSIPHY is exposed as a standalone generic-PHY provider node at
its existing register address, with its own OF graph (port@0
sensor-facing, port@1 CAMSS-facing), so that camss_detect_legacy_phy()
picks the non-legacy path once a board wires a sensor through one of
them. The camss node's own reg-names/clocks/interrupts for the
CSIPHYs are left unchanged, so boards that don't use a provider still
fall back to the legacy in-driver CSIPHY handling. All provider nodes
are added disabled by default; a board or camera overlay enables the
one(s) it actually uses.

The three patches are otherwise independent and split one-per-SoC
since each touches a different dtsi file:

 - Patch 1 adds the four SA8775P CSIPHYs (csiphy0-3) as
   qcom,SA8775P-csi2-phy nodes.

 - Patch 2 adds the three QCS8300 CSIPHYs (csiphy0-2) as
   qcom,QCS8300-csi2-phy nodes.

 - Patch 3 adds the five SC7280 CSIPHYs (csiphy0-4) as
   qcom,SC7280-csi2-phy nodes.

This series depends on the compatible strings and soc_cfg entries
introduced by the driver series referenced above and should be applied
on top of it.

Depends-on: https://lore.kernel.org/all/20261103214105.3605181-1-anusha.nandi@oss.qualcomm.com/

Anusha Arun Nandi (3):
  arm64: dts: qcom: lemans: add CSI2 D-PHY common-phy providers
  arm64: dts: qcom: monaco: add CSI2 PHY common-phy providers
  arm64: dts: qcom: kodiak: add CSI2 D-PHY common-phy providers

 arch/arm64/boot/dts/qcom/kodiak.dtsi | 172 +++++++++++++++++++++++++++
 arch/arm64/boot/dts/qcom/lemans.dtsi | 140 ++++++++++++++++++++++
 arch/arm64/boot/dts/qcom/monaco.dtsi | 114 ++++++++++++++++++
 3 files changed, 426 insertions(+)

Best regards,
-- 
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-- 
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[PATCH v2 1/3] arm64: dts: qcom: lemans: add CSI2 D-PHY common-phy providers

[Anusha Arun Nandi]

Expose the four SA8775p CSIPHYs as standalone qcom,sa8775p-csi2-phy
generic-PHY provider nodes (csiphy0..3) at their existing register
addresses, each with its own OF graph (port@0 sensor-facing, port@1
CAMSS-facing) so camss_detect_legacy_phy() picks the non-legacy path
once a board wires a sensor through one of them. The camss node's own
reg-names/clocks/interrupts for the CSIPHYs are unchanged, so boards
that don't use a provider still get the legacy binding.

The provider nodes are disabled by default; a board or camera overlay
enables the one(s) it uses.

Reviewed-by: Jigarkumar Zala <jigarkumar.zala@oss.qualcomm.com>
Signed-off-by: Anusha Arun Nandi <anusha.nandi@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/lemans.dtsi | 140 +++++++++++++++++++++++++++
 1 file changed, 140 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
index 1fdb72fa5518..2a30bf1c82af 100644
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
@@ -5164,6 +5164,146 @@ cci3_i2c1: i2c-bus@1 {
 			};
 		};
 
+		csiphy0: phy@ac9c000 {
+			compatible = "qcom,sa8775p-csi2-phy";
+			reg = <0x0 0x0ac9c000 0x0 0x2000>;
+
+			clocks = <&camcc CAM_CC_CSIPHY0_CLK>,
+				 <&camcc CAM_CC_CSI0PHYTIMER_CLK>;
+			clock-names = "core",
+				      "timer";
+
+			interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>;
+
+			operating-points-v2 = <&csiphy_opp_table>;
+
+			power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+			power-domain-names = "top";
+
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+				};
+
+				port@1 {
+					reg = <1>;
+				};
+			};
+		};
+
+		csiphy1: phy@ac9e000 {
+			compatible = "qcom,sa8775p-csi2-phy";
+			reg = <0x0 0x0ac9e000 0x0 0x2000>;
+
+			clocks = <&camcc CAM_CC_CSIPHY1_CLK>,
+				 <&camcc CAM_CC_CSI1PHYTIMER_CLK>;
+			clock-names = "core",
+				      "timer";
+
+			interrupts = <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>;
+
+			operating-points-v2 = <&csiphy_opp_table>;
+
+			power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+			power-domain-names = "top";
+
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+				};
+
+				port@1 {
+					reg = <1>;
+				};
+			};
+		};
+
+		csiphy2: phy@aca0000 {
+			compatible = "qcom,sa8775p-csi2-phy";
+			reg = <0x0 0x0aca0000 0x0 0x2000>;
+
+			clocks = <&camcc CAM_CC_CSIPHY2_CLK>,
+				 <&camcc CAM_CC_CSI2PHYTIMER_CLK>;
+			clock-names = "core",
+				      "timer";
+
+			interrupts = <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>;
+
+			operating-points-v2 = <&csiphy_opp_table>;
+
+			power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+			power-domain-names = "top";
+
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+				};
+
+				port@1 {
+					reg = <1>;
+				};
+			};
+		};
+
+		csiphy3: phy@aca2000 {
+			compatible = "qcom,sa8775p-csi2-phy";
+			reg = <0x0 0x0aca2000 0x0 0x2000>;
+
+			clocks = <&camcc CAM_CC_CSIPHY3_CLK>,
+				 <&camcc CAM_CC_CSI3PHYTIMER_CLK>;
+			clock-names = "core",
+				      "timer";
+
+			interrupts = <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>;
+
+			operating-points-v2 = <&csiphy_opp_table>;
+
+			power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+			power-domain-names = "top";
+
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+				};
+
+				port@1 {
+					reg = <1>;
+				};
+			};
+		};
+
+		csiphy_opp_table: opp-table-csiphy {
+			compatible = "operating-points-v2";
+
+			opp-300000000 {
+				opp-hz = /bits/ 64 <300000000>;
+			};
+
+			opp-400000000 {
+				opp-hz = /bits/ 64 <400000000>;
+			};
+		};
+
 		camss: isp@ac78000 {
 			compatible = "qcom,sa8775p-camss";
 
-- 
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[PATCH v2 2/3] arm64: dts: qcom: monaco: add CSI2 PHY common-phy providers

[Anusha Arun Nandi]

Expose the three QCS8300 CSIPHYs as standalone
qcom,qcs8300-csi2-phy generic-PHY provider nodes (csiphy0..2) at their
existing register addresses, each with its own OF graph (port@0
sensor-facing, port@1 CAMSS-facing) so camss_detect_legacy_phy() picks
the non-legacy path once a board wires a sensor through one of them.
The camss node's own reg-names/clocks/interrupts for the CSIPHYs are
unchanged, so boards that don't use a provider still get the legacy
binding.

The provider nodes are disabled by default; a board or camera overlay
enables the one(s) it uses.

Reviewed-by: Jigarkumar Zala <jigarkumar.zala@oss.qualcomm.com>
Signed-off-by: Anusha Arun Nandi <anusha.nandi@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/monaco.dtsi | 114 +++++++++++++++++++++++++++
 1 file changed, 114 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
index 35fbee63d4c6..9585bc723fc4 100644
--- a/arch/arm64/boot/dts/qcom/monaco.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
@@ -5577,6 +5577,120 @@ cci2_i2c1: i2c-bus@1 {
 			};
 		};
 
+		csiphy0: phy@ac9c000 {
+			compatible = "qcom,qcs8300-csi2-phy";
+			reg = <0x0 0x0ac9c000 0x0 0x2000>;
+
+			clocks = <&camcc CAM_CC_CSIPHY0_CLK>,
+				 <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+				 <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>;
+			clock-names = "core",
+				      "timer",
+				      "csiphy_rx";
+
+			interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>;
+
+			operating-points-v2 = <&csiphy_opp_table>;
+
+			power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+			power-domain-names = "top";
+
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+				};
+
+				port@1 {
+					reg = <1>;
+				};
+			};
+		};
+
+		csiphy1: phy@ac9e000 {
+			compatible = "qcom,qcs8300-csi2-phy";
+			reg = <0x0 0x0ac9e000 0x0 0x2000>;
+
+			clocks = <&camcc CAM_CC_CSIPHY1_CLK>,
+				 <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+				 <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>;
+			clock-names = "core",
+				      "timer",
+				      "csiphy_rx";
+
+			interrupts = <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>;
+
+			operating-points-v2 = <&csiphy_opp_table>;
+
+			power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+			power-domain-names = "top";
+
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+				};
+
+				port@1 {
+					reg = <1>;
+				};
+			};
+		};
+
+		csiphy2: phy@aca0000 {
+			compatible = "qcom,qcs8300-csi2-phy";
+			reg = <0x0 0x0aca0000 0x0 0x2000>;
+
+			clocks = <&camcc CAM_CC_CSIPHY2_CLK>,
+				 <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+				 <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>;
+			clock-names = "core",
+				      "timer",
+				      "csiphy_rx";
+
+			interrupts = <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>;
+
+			operating-points-v2 = <&csiphy_opp_table>;
+
+			power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+			power-domain-names = "top";
+
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+				};
+
+				port@1 {
+					reg = <1>;
+				};
+			};
+		};
+
+		csiphy_opp_table: opp-table-csiphy {
+			compatible = "operating-points-v2";
+
+			opp-300000000 {
+				opp-hz = /bits/ 64 <300000000>;
+			};
+
+			opp-400000000 {
+				opp-hz = /bits/ 64 <400000000>;
+			};
+		};
+
 		camss: isp@ac78000 {
 			compatible = "qcom,qcs8300-camss";
 
-- 
2.34.1


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[PATCH v2 3/3] arm64: dts: qcom: kodiak: add CSI2 D-PHY common-phy providers

[Anusha Arun Nandi]

Expose SC7280's five CSIPHYs as standalone
qcom,sc7280-csi2-phy generic-PHY provider nodes (csiphy0..4) at their
existing register addresses, each with its own OF graph (port@0
sensor-facing, port@1 CAMSS-facing) so camss_detect_legacy_phy() picks
the non-legacy path once a board wires a sensor through one of them.
The camss node's own reg-names/clocks/interrupts for the CSIPHYs are
unchanged, so boards that don't use a provider still get the legacy
binding.

The provider nodes are disabled by default; a board or camera overlay
enables the one(s) it uses.

Reviewed-by: Jigarkumar Zala <jigarkumar.zala@oss.qualcomm.com>
Signed-off-by: Anusha Arun Nandi <anusha.nandi@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/kodiak.dtsi | 172 +++++++++++++++++++++++++++
 1 file changed, 172 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
index 8c7523602d27..3f3a41cfaa00 100644
--- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
+++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
@@ -5164,6 +5164,178 @@ cci1_i2c1: i2c-bus@1 {
 			};
 		};
 
+		csiphy0: phy@ace0000 {
+			compatible = "qcom,sc7280-csi2-phy";
+			reg = <0x0 0x0ace0000 0x0 0x2000>;
+
+			clocks = <&camcc CAM_CC_CSIPHY0_CLK>,
+				 <&camcc CAM_CC_CSI0PHYTIMER_CLK>;
+			clock-names = "core",
+				      "timer";
+
+			interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>;
+
+			operating-points-v2 = <&csiphy_opp_table>;
+
+			power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+			power-domain-names = "top";
+
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+				};
+
+				port@1 {
+					reg = <1>;
+				};
+			};
+		};
+
+		csiphy1: phy@ace2000 {
+			compatible = "qcom,sc7280-csi2-phy";
+			reg = <0x0 0x0ace2000 0x0 0x2000>;
+
+			clocks = <&camcc CAM_CC_CSIPHY1_CLK>,
+				 <&camcc CAM_CC_CSI1PHYTIMER_CLK>;
+			clock-names = "core",
+				      "timer";
+
+			interrupts = <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>;
+
+			operating-points-v2 = <&csiphy_opp_table>;
+
+			power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+			power-domain-names = "top";
+
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+				};
+
+				port@1 {
+					reg = <1>;
+				};
+			};
+		};
+
+		csiphy2: phy@ace4000 {
+			compatible = "qcom,sc7280-csi2-phy";
+			reg = <0x0 0x0ace4000 0x0 0x2000>;
+
+			clocks = <&camcc CAM_CC_CSIPHY2_CLK>,
+				 <&camcc CAM_CC_CSI2PHYTIMER_CLK>;
+			clock-names = "core",
+				      "timer";
+
+			interrupts = <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>;
+
+			operating-points-v2 = <&csiphy_opp_table>;
+
+			power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+			power-domain-names = "top";
+
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+				};
+
+				port@1 {
+					reg = <1>;
+				};
+			};
+		};
+
+		csiphy3: phy@ace6000 {
+			compatible = "qcom,sc7280-csi2-phy";
+			reg = <0x0 0x0ace6000 0x0 0x2000>;
+
+			clocks = <&camcc CAM_CC_CSIPHY3_CLK>,
+				 <&camcc CAM_CC_CSI3PHYTIMER_CLK>;
+			clock-names = "core",
+				      "timer";
+
+			interrupts = <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>;
+
+			operating-points-v2 = <&csiphy_opp_table>;
+
+			power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+			power-domain-names = "top";
+
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+				};
+
+				port@1 {
+					reg = <1>;
+				};
+			};
+		};
+
+		csiphy4: phy@ace8000 {
+			compatible = "qcom,sc7280-csi2-phy";
+			reg = <0x0 0x0ace8000 0x0 0x2000>;
+
+			clocks = <&camcc CAM_CC_CSIPHY4_CLK>,
+				 <&camcc CAM_CC_CSI4PHYTIMER_CLK>;
+			clock-names = "core",
+				      "timer";
+
+			interrupts = <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>;
+
+			operating-points-v2 = <&csiphy_opp_table>;
+
+			power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+			power-domain-names = "top";
+
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+				};
+
+				port@1 {
+					reg = <1>;
+				};
+			};
+		};
+
+		csiphy_opp_table: opp-table-csiphy {
+			compatible = "operating-points-v2";
+
+			opp-300000000 {
+				opp-hz = /bits/ 64 <300000000>;
+			};
+
+			opp-400000000 {
+				opp-hz = /bits/ 64 <400000000>;
+			};
+		};
+
 		camss: isp@acb3000 {
 			compatible = "qcom,sc7280-camss";
 
-- 
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Re: [PATCH v2 1/3] arm64: dts: qcom: lemans: add CSI2 D-PHY common-phy providers

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 5 potential issue(s) to consider:
- [Medium] arm64: dts: qcom: lemans: undocumented qcom,sa8775p-csi2-phy compatible
- [Medium] arm64: dts: qcom: lemans: single power-domain on csiphy0..3 causes -EEXIST
- [Medium] arm64: dts: qcom: lemans: csiphy_opp_table placed inside soc@0 simple-bus
- [Medium] arm64: dts: qcom: lemans: unsupported 300 MHz OPP in csiphy_opp_table
- [Low] arm64: dts: qcom: lemans: csiphy0..3 placed out of address order before camss
--

commit c410d584d10da78b4d7e3c88848890055466fbee
Author: Anusha Arun Nandi <anusha.nandi@oss.qualcomm.com>

arm64: dts: qcom: lemans: add CSI2 D-PHY common-phy providers

This commit adds four disabled standalone qcom,sa8775p-csi2-phy PHY provider
nodes (csiphy0..csiphy3) and an associated operating-points-v2 table in
arch/arm64/boot/dts/qcom/lemans.dtsi so boards can wire camera sensors
through the non-legacy CAMSS PHY path.

> diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
> index 1fdb72fa55184..2a30bf1c82af1 100644
> --- a/arch/arm64/boot/dts/qcom/lemans.dtsi
> +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
> @@ -5164,6 +5164,146 @@ cci3_i2c1: i2c-bus@1 {
>  			};
>  		};
>  
> +		csiphy0: phy@ac9c000 {
> +			compatible = "qcom,sa8775p-csi2-phy";

[Severity: Medium]
As reported by Sashiko on v1 [1], is there a Devicetree binding schema or PHY
driver support for qcom,sa8775p-csi2-phy?

In Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml, only
qcom,x1e80100-csi2-phy and qcom,glymur-csi2-phy are documented, so
dtbs_check will fail on csiphy0..csiphy3.

Similarly, phy_qcom_mipi_csi2_of_match_table in
drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c only matches
qcom,x1e80100-csi2-phy:

    static const struct of_device_id phy_qcom_mipi_csi2_of_match_table[] = {
        { .compatible = "qcom,x1e80100-csi2-phy", .data = &mipi_csi2_dphy_4nm_x1e },
        { }
    };

When a board or overlay enables any of csiphy0..csiphy3 and wires a sensor
endpoint through it to camss, camss_probe() -> camss_init_subdevices() ->
camss_detect_legacy_phy() sets camss->legacy_phy = false, and
msm_csiphy_subdev_init() in drivers/media/platform/qcom/camss/camss-csiphy.c
calls:

    csiphy->phy = devm_phy_get_by_of_node(dev, remote);

Without a driver matching qcom,sa8775p-csi2-phy (which uses the 5nm 2PH
v1.3.0 register layout rather than X1E80100's 4nm 2PH v2.1.2 layout), won't
devm_phy_get_by_of_node() return -EPROBE_DEFER indefinitely?

> +			reg = <0x0 0x0ac9c000 0x0 0x2000>;
> +
> +			clocks = <&camcc CAM_CC_CSIPHY0_CLK>,
> +				 <&camcc CAM_CC_CSI0PHYTIMER_CLK>;
> +			clock-names = "core",
> +				      "timer";
> +
> +			interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>;
> +
> +			operating-points-v2 = <&csiphy_opp_table>;
> +
> +			power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> +			power-domain-names = "top";

[Severity: Medium]
Will phy_qcom_mipi_csi2_probe() fail with -EEXIST when power-domains only
contains a single entry on csiphy0..csiphy3?

When a platform device has a single power-domains phandle in DT,
platform_probe() -> dev_pm_domain_attach() -> genpd_dev_pm_attach() in
drivers/pmdomain/core.c attaches that domain to dev->pm_domain before calling
the driver's probe function:

    if (of_count_phandle_with_args(dev->of_node, "power-domains",
                                   "#power-domain-cells") != 1)
        return 0;

    return __genpd_dev_pm_attach(dev, dev, 0, 1, true);

When phy_qcom_mipi_csi2_probe() in
drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c subsequently calls
phy_qcom_mipi_csi2_attach_pm_domains() -> devm_pm_domain_attach_list() ->
dev_pm_domain_attach_list() in drivers/base/power/common.c, it rejects the
device because dev->pm_domain is already populated:

    if (dev->pm_domain)
        return -EEXIST;

In addition, shouldn't csiphy0..csiphy3 also provide the ahb clock in clocks
and clock-names, the scaled rail power domains (mmcx, mx), and the vdda
regulator supplies expected by
Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml and
drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c?

[ ... ]

> +		csiphy_opp_table: opp-table-csiphy {
> +			compatible = "operating-points-v2";

[Severity: Medium]
As reported by Sashiko on v1 [2], should csiphy_opp_table: opp-table-csiphy
be placed under the root node outside soc: soc@0?

Because soc: soc@0 has compatible = "simple-bus", placing opp-table-csiphy as
a direct child of soc@0 without a unit address, reg, or ranges property
triggers a dtc simple_bus_reg failure in check_simple_bus_reg() in
scripts/dtc/checks.c:

    if (!cells) {
        if (node->parent->parent && !(node->bus == &simple_bus))
            FAIL(c, dti, node, "missing or empty reg/ranges property");
        return;
    }

Shared OPP tables in arch/arm64/boot/dts/qcom/lemans.dtsi (such as
qup_opp_table_100mhz: opp-table-qup100mhz) are placed under the root node
rather than inside soc@0.

> +
> +			opp-300000000 {
> +				opp-hz = /bits/ 64 <300000000>;
> +			};

[Severity: Medium]
As reported by Sashiko on v1 [3], does the SA8775P CAMCC clock driver support
the 300 MHz operating point in csiphy_opp_table?

In drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c, phy_qcom_mipi_csi2_probe()
associates the OPP table with the "core" clock (CAM_CC_CSIPHY0_CLK ..
CAM_CC_CSIPHY3_CLK). In drivers/clk/qcom/camcc-sa8775p.c, both
cam_cc_cphy_rx_clk_src and cam_cc_csi0phytimer_clk_src ..
cam_cc_csi3phytimer_clk_src use ftbl_cam_cc_cphy_rx_clk_src, which only
defines 400 MHz:

    static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
        F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
        { }
    };

This also matches csiphy_res_8775p in
drivers/media/platform/qcom/camss/camss.c, which only lists 400000000 Hz.
Should opp-300000000 be dropped from csiphy_opp_table?

> +
> +			opp-400000000 {
> +				opp-hz = /bits/ 64 <400000000>;
> +			};
> +		};
> +
>  		camss: isp@ac78000 {
>  			compatible = "qcom,sa8775p-camss";

[Severity: Low]
As reported by Sashiko on v1 [4], should csiphy0..csiphy3
(phy@ac9c000..phy@aca2000) be placed after camss: isp@ac78000 and before
camcc: clock-controller@ade0000 so that child nodes under soc: soc@0 remain
sorted by ascending unit address?

[1] https://lore.kernel.org/r/20261017001116.2318647-2-anusha.nandi@oss.qualcomm.com
[2] https://lore.kernel.org/r/20261017001116.2318647-2-anusha.nandi@oss.qualcomm.com
[3] https://lore.kernel.org/r/20261017001116.2318647-2-anusha.nandi@oss.qualcomm.com
[4] https://lore.kernel.org/r/20261017001116.2318647-2-anusha.nandi@oss.qualcomm.com

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Re: [PATCH v2 2/3] arm64: dts: qcom: monaco: add CSI2 PHY common-phy providers

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
- [High] arm64: dts: qcom: monaco: undocumented qcom,qcs8300-csi2-phy compatible
- [High] arm64: dts: qcom: monaco: single power-domain on csiphy0..2 causes -EEXIST
- [Medium] arm64: dts: qcom: monaco: unsupported 300 MHz OPP in csiphy_opp_table
- [Low] arm64: dts: qcom: monaco: csiphy_opp_table placed inside simple-bus soc@0
--

commit 59d7abe471847dc33609b30800a267639ba8de2a
Author: Anusha Arun Nandi <anusha.nandi@oss.qualcomm.com>

arm64: dts: qcom: monaco: add CSI2 PHY common-phy providers

This commit adds standalone qcom,qcs8300-csi2-phy provider nodes (csiphy0..2)
and an opp-table-csiphy node to monaco.dtsi so boards can wire sensors through
the generic PHY path rather than the legacy CAMSS PHY binding.

> diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
> index 35fbee63d4c65..9585bc723fc40 100644
> --- a/arch/arm64/boot/dts/qcom/monaco.dtsi
> +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
> @@ -5577,6 +5577,120 @@ cci2_i2c1: i2c-bus@1 {
>  			};
>  		};
>  
> +		csiphy0: phy@ac9c000 {
> +			compatible = "qcom,qcs8300-csi2-phy";
> +			reg = <0x0 0x0ac9c000 0x0 0x2000>;
> +
> +			clocks = <&camcc CAM_CC_CSIPHY0_CLK>,
> +				 <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
> +				 <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>;
> +			clock-names = "core",
> +				      "timer",
> +				      "csiphy_rx";

[Severity: High]
As reported by Sashiko on v1 [1], is there a binding update and driver support
for "qcom,qcs8300-csi2-phy" that should precede this change?

Currently, Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
only documents qcom,x1e80100-csi2-phy and qcom,glymur-csi2-phy, and
phy_qcom_mipi_csi2_of_match_table[] in
drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c only matches
"qcom,x1e80100-csi2-phy":

    static const struct of_device_id phy_qcom_mipi_csi2_of_match_table[] = {
            { .compatible = "qcom,x1e80100-csi2-phy", .data = &mipi_csi2_dphy_4nm_x1e },
            { }
    };

When a board or overlay enables csiphy0, csiphy1, or csiphy2 and wires a
sensor through it, camss_detect_legacy_phy() selects the non-legacy path and
camss_init_subdevices() -> msm_csiphy_subdev_init() calls
devm_phy_get_by_of_node(). Because no PHY provider driver binds to
"qcom,qcs8300-csi2-phy", devm_phy_get_by_of_node() will return -EPROBE_DEFER
indefinitely.

Additionally, csiphy0..2 specify three clocks ("core", "timer", "csiphy_rx"),
whereas the sibling SA8775P CSIPHY nodes in lemans.dtsi specify two clocks
("core", "timer") and qcom,x1e80100-csi2-phy.yaml specifies "core", "timer",
and "ahb", while phy_qcom_mipi_csi2_probe() enforces an exact match between
the DT clock count and soc_cfg->num_clk.

> +
> +			interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>;
> +
> +			operating-points-v2 = <&csiphy_opp_table>;
> +
> +			power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> +			power-domain-names = "top";

[Severity: High]
Will specifying only a single power-domains entry on csiphy0, csiphy1, and
csiphy2 cause phy_qcom_mipi_csi2_probe() to fail with -EEXIST?

When a platform device has a single power-domains entry in DT,
platform_probe() calls dev_pm_domain_attach() -> genpd_dev_pm_attach(), which
attaches that domain to dev->pm_domain before invoking the driver's probe()
callback:

    if (of_count_phandle_with_args(dev->of_node, "power-domains",
                                   "#power-domain-cells") != 1)
            return 0;

    return __genpd_dev_pm_attach(dev, dev, 0, 1, true);

When phy_qcom_mipi_csi2_probe() subsequently calls
phy_qcom_mipi_csi2_attach_pm_domains() -> devm_pm_domain_attach_list() ->
dev_pm_domain_attach_list(), it rejects the device because dev->pm_domain is
already set:

    if (dev->pm_domain)
            return -EEXIST;

Furthermore, Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
and drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c expect three power
domains ("top", "mmcx", and "mx").

[ ... ]

> +		csiphy_opp_table: opp-table-csiphy {
> +			compatible = "operating-points-v2";
> +
> +			opp-300000000 {
> +				opp-hz = /bits/ 64 <300000000>;
> +			};

[Severity: Medium]
As reported by Sashiko on v1 [2], does the QCS8300 CAMCC hardware and clock
driver support a 300 MHz operating point for the CSIPHY clocks?

In drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c,
phy_qcom_mipi_csi2_set_clock_rates() selects the ceiling OPP for link_freq / 4
and calls dev_pm_opp_set_rate() on the "core" clock (CAM_CC_CSIPHY0..2_CLK).
However, in drivers/clk/qcom/camcc-sa8775p.c (which handles
qcom,qcs8300-camcc), cam_cc_csiphy0..2_clk and cam_cc_csi0..2phytimer_clk_src
use ftbl_cam_cc_cphy_rx_clk_src, which only defines a 400 MHz frequency entry:

    static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
            F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
            { }
    };

Similarly, csiphy_res_8775p in drivers/media/platform/qcom/camss/camss.c only
lists 400000000 Hz for the QCS8300 CSIPHY clocks. Should opp-300000000 be
dropped from csiphy_opp_table?

> +
> +			opp-400000000 {
> +				opp-hz = /bits/ 64 <400000000>;
> +			};
> +		};
> +
>  		camss: isp@ac78000 {
>  			compatible = "qcom,qcs8300-camss";

[Severity: Low]
As reported by Sashiko on v1 [3], should csiphy_opp_table (opp-table-csiphy)
be placed under the root node (like cpu0_opp_table and qup_opp_table in
monaco.dtsi) or inside each PHY node rather than directly under soc@0?

Because soc@0 is a simple-bus, placing opp-table-csiphy directly inside it
without a reg or ranges property triggers a DTC simple_bus_reg warning in
check_simple_bus_reg() ("missing or empty reg/ranges property") and fails
simple-bus.yaml validation in dtbs_check. Also, phy@ac9c000, phy@ac9e000, and
phy@aca0000 are placed before isp@ac78000 rather than after it in ascending
unit-address order.

[1] https://lore.kernel.org/r/20261017001116.2318647-3-anusha.nandi@oss.qualcomm.com
[2] https://lore.kernel.org/r/20261017001116.2318647-3-anusha.nandi@oss.qualcomm.com
[3] https://lore.kernel.org/r/20261017001116.2318647-3-anusha.nandi@oss.qualcomm.com

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Re: [PATCH v2 3/3] arm64: dts: qcom: kodiak: add CSI2 D-PHY common-phy providers

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [Medium] arm64: dts: qcom: kodiak: undocumented qcom,sc7280-csi2-phy compatible
- [Medium] arm64: dts: qcom: kodiak: single power-domain on csiphy0..4 breaks probe
- [Low] arm64: dts: qcom: kodiak: opp-table-csiphy placed inside simple-bus soc@0
--

commit ff6bb490a6a0e1b9df4c47b3f6023f1f2dc0688e
Author: Anusha Arun Nandi <anusha.nandi@oss.qualcomm.com>

arm64: dts: qcom: kodiak: add CSI2 D-PHY common-phy providers

This commit adds standalone qcom,sc7280-csi2-phy generic-PHY provider nodes
(csiphy0..csiphy4) and a shared csiphy_opp_table in kodiak.dtsi so boards can
wire sensors through the non-legacy CAMSS PHY path.

> diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
> index 8c7523602d271..3f3a41cfaa001 100644
> --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
> +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
> @@ -5164,6 +5164,178 @@ cci1_i2c1: i2c-bus@1 {
>  			};
>  		};
>  
> +		csiphy0: phy@ace0000 {
> +			compatible = "qcom,sc7280-csi2-phy";

[Severity: Medium]
As reported by Sashiko on v1 [1], is there a companion DT binding and PHY
driver series for "qcom,sc7280-csi2-phy"?

In the current tree, Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
only documents "qcom,x1e80100-csi2-phy" and "qcom,glymur-csi2-phy", and
phy_qcom_mipi_csi2_of_match_table in drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c
only matches "qcom,x1e80100-csi2-phy":

static const struct of_device_id phy_qcom_mipi_csi2_of_match_table[] = {
	{ .compatible	= "qcom,x1e80100-csi2-phy", .data = &mipi_csi2_dphy_4nm_x1e },
	{ }
};

Without a binding and driver match for "qcom,sc7280-csi2-phy" (used across
csiphy0..csiphy4), dtbs_check fails schema validation, and enabling any of
these nodes on a board or overlay causes camss_detect_legacy_phy() ->
camss_init_subdevices() -> msm_csiphy_subdev_init() ->
devm_phy_get_by_of_node() to fail with permanent -EPROBE_DEFER because no PHY
provider driver binds to the remote node.

> +			reg = <0x0 0x0ace0000 0x0 0x2000>;
> +
> +			clocks = <&camcc CAM_CC_CSIPHY0_CLK>,
> +				 <&camcc CAM_CC_CSI0PHYTIMER_CLK>;
> +			clock-names = "core",
> +				      "timer";
> +
> +			interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>;
> +
> +			operating-points-v2 = <&csiphy_opp_table>;
> +
> +			power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> +			power-domain-names = "top";

[Severity: Medium]
Will specifying only a single power-domains entry on csiphy0..csiphy4 cause
phy_qcom_mipi_csi2_probe() to fail with -EEXIST when a board enables one of
these PHYs?

When a platform device has a single power-domains entry, platform_probe() ->
dev_pm_domain_attach() -> genpd_dev_pm_attach() attaches it directly to
dev->pm_domain before invoking the driver's probe callback:

drivers/pmdomain/core.c:genpd_dev_pm_attach()
	if (of_count_phandle_with_args(dev->of_node, "power-domains",
				       "#power-domain-cells") != 1)
		return 0;

	return __genpd_dev_pm_attach(dev, dev, 0, 1, true);

When phy_qcom_mipi_csi2_probe() then calls
phy_qcom_mipi_csi2_attach_pm_domains() -> devm_pm_domain_attach_list() ->
dev_pm_domain_attach_list(), it sees dev->pm_domain is already populated and
returns -EEXIST:

drivers/base/power/common.c:dev_pm_domain_attach_list()
	if (dev->pm_domain)
		return -EEXIST;

drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c:phy_qcom_mipi_csi2_probe()
	ret = phy_qcom_mipi_csi2_attach_pm_domains(csi2phy);
	if (ret < 0 || csi2phy->pd_list == NULL) {
		if (ret == 0)
			ret = -ENODEV;
		return dev_err_probe(dev, ret, "Failed to attach power-domain list\n");
	}

Should csiphy0..csiphy4 also include the RPMHPD voltage rail power domains
(and corresponding required-opps in csiphy_opp_table) expected by the
Qualcomm CSI2 PHY binding and phy_qcom_mipi_csi2_set_clock_rates()?

[ ... ]

> +		csiphy_opp_table: opp-table-csiphy {
> +			compatible = "operating-points-v2";
> +
> +			opp-300000000 {
> +				opp-hz = /bits/ 64 <300000000>;
> +			};
> +
> +			opp-400000000 {
> +				opp-hz = /bits/ 64 <400000000>;
> +			};
> +		};
> +
>  		camss: isp@acb3000 {

[Severity: Low]
As reported by Sashiko on v1 [2], should csiphy_opp_table be moved out of
soc: soc@0 to the root node (alongside qspi_opp_table and qup_opp_table), and
should csiphy0..csiphy4 (phy@ace0000..phy@ace8000) be placed after
camss: isp@acb3000 to maintain unit-address ordering?

Because soc: soc@0 is a "simple-bus", placing opp-table-csiphy directly inside
it without a reg or ranges property triggers a simple_bus_reg warning in
check_simple_bus_reg() in scripts/dtc/checks.c during W=1 DTB builds as well
as a simple-bus.yaml schema validation error in dtbs_check.

[1] https://lore.kernel.org/r/20261017001116.2318647-4-anusha.nandi@oss.qualcomm.com
[2] https://lore.kernel.org/r/20261017001116.2318647-4-anusha.nandi@oss.qualcomm.com

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Re: [PATCH v2 1/3] arm64: dts: qcom: lemans: add CSI2 D-PHY common-phy providers

[Nihal Kumar Gupta]

On 04-11-2026 03:40, Anusha Arun Nandi wrote:
> Expose the four SA8775p CSIPHYs as standalone qcom,sa8775p-csi2-phy
> generic-PHY provider nodes (csiphy0..3) at their existing register
> addresses, each with its own OF graph (port@0 sensor-facing, port@1
> CAMSS-facing) so camss_detect_legacy_phy() picks the non-legacy path
> once a board wires a sensor through one of them. The camss node's own
> reg-names/clocks/interrupts for the CSIPHYs are unchanged, so boards
> that don't use a provider still get the legacy binding.
> 
> The provider nodes are disabled by default; a board or camera overlay
> enables the one(s) it uses.
> 
> Reviewed-by: Jigarkumar Zala <jigarkumar.zala@oss.qualcomm.com>
> Signed-off-by: Anusha Arun Nandi <anusha.nandi@oss.qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/lemans.dtsi | 140 +++++++++++++++++++++++++++
>  1 file changed, 140 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
> index 1fdb72fa5518..2a30bf1c82af 100644
> --- a/arch/arm64/boot/dts/qcom/lemans.dtsi
> +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
> @@ -5164,6 +5164,146 @@ cci3_i2c1: i2c-bus@1 {
>  			};
>  		};
>  
> +		csiphy0: phy@ac9c000 {
> +			compatible = "qcom,sa8775p-csi2-phy";
> +			reg = <0x0 0x0ac9c000 0x0 0x2000>;
...

> +		csiphy3: phy@aca2000 {
> +			compatible = "qcom,sa8775p-csi2-phy";

phy@ac9c000 through phy@aca2000 nodes precede the existing
isp@ac78000 node.
Sort CSIPHY nodes by unit-address numerically.

> +			reg = <0x0 0x0aca2000 0x0 0x2000>;
> +
> +			clocks = <&camcc CAM_CC_CSIPHY3_CLK>,
> +				 <&camcc CAM_CC_CSI3PHYTIMER_CLK>;
> +			clock-names = "core",
> +				      "timer";
> +
> +			interrupts = <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>;
> +
> +			operating-points-v2 = <&csiphy_opp_table>;
> +
> +			power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> +			power-domain-names = "top";
> +
> +			status = "disabled";
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				port@0 {
> +					reg = <0>;
> +				};
> +
> +				port@1 {
> +					reg = <1>;
> +				};
> +			};
> +		};
> +
> +		csiphy_opp_table: opp-table-csiphy {
> +			compatible = "operating-points-v2";
> +
> +			opp-300000000 {
> +				opp-hz = /bits/ 64 <300000000>;
> +			};
> +
> +			opp-400000000 {
> +				opp-hz = /bits/ 64 <400000000>;
> +			};
> +		};
> +
>  		camss: isp@ac78000 {
>  			compatible = "qcom,sa8775p-camss";
>  

-- 
Regards,
Nihal Kumar Gupta


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