Re: [PATCH 1/2] soc: mediatek: pm-domains: add smi_larb_reset function when power on

[AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>]

Il 25/03/24 13:19, yu-chang.lee ha scritto:
> This patch avoid mtcmos power glitch from happening by set and clear
> smi larb reset.
> 
> Signed-off-by: yu-chang.lee <yu-chang.lee@mediatek.com>
> ---
>   drivers/pmdomain/mediatek/mt8188-pm-domains.h | 28 +++++++++
>   drivers/pmdomain/mediatek/mtk-pm-domains.c    | 59 +++++++++++++++++++
>   drivers/pmdomain/mediatek/mtk-pm-domains.h    | 12 ++++
>   3 files changed, 99 insertions(+)
> 
> diff --git a/drivers/pmdomain/mediatek/mt8188-pm-domains.h b/drivers/pmdomain/mediatek/mt8188-pm-domains.h
> index 06834ab6597c..7bbba4d56a77 100644
> --- a/drivers/pmdomain/mediatek/mt8188-pm-domains.h
> +++ b/drivers/pmdomain/mediatek/mt8188-pm-domains.h
> @@ -573,6 +573,18 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
>   		.pwr_sta2nd_offs = 0x170,
>   		.sram_pdn_bits = BIT(8),
>   		.sram_pdn_ack_bits = BIT(12),
> +		.reset_smi = {
> +			SMI_RESET_WR(MT8188_SMI_LARB10_RESET,
> +				     MT8188_SMI_LARB10_RESET_ADDR),
> +			SMI_RESET_WR(MT8188_SMI_LARB11A_RESET,
> +				     MT8188_SMI_LARB11A_RESET_ADDR),
> +			SMI_RESET_WR(MT8188_SMI_LARB11C_RESET,
> +				     MT8188_SMI_LARB11C_RESET_ADDR),
> +			SMI_RESET_WR(MT8188_SMI_LARB11B_RESET,
> +				     MT8188_SMI_LARB11B_RESET_ADDR),
> +			SMI_RESET_WR(MT8188_SMI_LARB15_RESET,
> +				     MT8188_SMI_LARB15_RESET_ADDR),
> +		},
>   		.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
>   	},
>   	[MT8188_POWER_DOMAIN_IPE] = {
> @@ -583,6 +595,10 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
>   		.pwr_sta2nd_offs = 0x170,
>   		.sram_pdn_bits = BIT(8),
>   		.sram_pdn_ack_bits = BIT(12),
> +		.reset_smi = {
> +			SMI_RESET_WR(MT8188_SMI_LARB12_RESET,
> +				     MT8188_SMI_LARB12_RESET_ADDR),
> +		},
>   		.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
>   	},
>   	[MT8188_POWER_DOMAIN_CAM_VCORE] = {
> @@ -660,6 +676,12 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
>   		.pwr_sta2nd_offs = 0x170,
>   		.sram_pdn_bits = BIT(8),
>   		.sram_pdn_ack_bits = BIT(12),
> +		.reset_smi = {
> +			SMI_RESET_WR(MT8188_SMI_LARB16A_RESET,
> +				     MT8188_SMI_LARB16A_RESET_ADDR),
> +			SMI_RESET_WR(MT8188_SMI_LARB17A_RESET,
> +				     MT8188_SMI_LARB17A_RESET_ADDR),
> +		},
>   		.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
>   	},
>   	[MT8188_POWER_DOMAIN_CAM_SUBB] = {
> @@ -670,6 +692,12 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
>   		.pwr_sta2nd_offs = 0x170,
>   		.sram_pdn_bits = BIT(8),
>   		.sram_pdn_ack_bits = BIT(12),
> +		.reset_smi = {
> +			SMI_RESET_WR(MT8188_SMI_LARB16B_RESET,
> +				     MT8188_SMI_LARB16B_RESET_ADDR),
> +			SMI_RESET_WR(MT8188_SMI_LARB17B_RESET,
> +				     MT8188_SMI_LARB17B_RESET_ADDR),
> +		},
>   		.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
>   	},
>   };
> diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/mediatek/mtk-pm-domains.c
> index e274e3315fe7..9ab6fa105c8c 100644
> --- a/drivers/pmdomain/mediatek/mtk-pm-domains.c
> +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c
> @@ -48,6 +48,8 @@ struct scpsys_domain {
>   	struct regmap *infracfg_nao;
>   	struct regmap *infracfg;
>   	struct regmap *smi;
> +	struct regmap **larb;
> +	int num_larb;
>   	struct regulator *supply;
>   };
>   
> @@ -230,6 +232,39 @@ static int scpsys_regulator_disable(struct regulator *supply)
>   	return supply ? regulator_disable(supply) : 0;
>   }
>   
> +static int _scpsys_smi_larb_reset(const struct smi_reset_data bpd,
> +				  struct regmap *regmap)
> +{
> +	int ret;
> +	u32 mask = bpd.smi_reset_mask;
> +
> +	if (!mask)
> +		return 0;
> +
> +	ret = regmap_set_bits(regmap, bpd.smi_reset_addr, mask);
> +	if (ret)
> +		return ret;
> +
> +	ret = regmap_clear_bits(regmap, bpd.smi_reset_addr, mask);
> +	if (ret)
> +		return ret;
> +
> +	return 0;
> +}
> +
> +static int scpsys_smi_larb_reset(struct scpsys_domain *pd)
> +{
> +	int ret, i;
> +
> +	for (i = 0; i < pd->num_larb; i++) {
> +		ret = _scpsys_smi_larb_reset(pd->data->reset_smi[i], pd->larb[i]);
> +		if (ret)
> +			return ret;
> +	}
> +
> +	return 0;
> +}
> +
>   static int scpsys_power_on(struct generic_pm_domain *genpd)
>   {
>   	struct scpsys_domain *pd = container_of(genpd, struct scpsys_domain, genpd);
> @@ -279,6 +314,10 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
>   	if (ret < 0)
>   		goto err_disable_subsys_clks;
>   
> +	ret = scpsys_smi_larb_reset(pd);
> +	if (ret < 0)
> +		goto err_disable_subsys_clks;
> +
>   	ret = scpsys_bus_protect_disable(pd);
>   	if (ret < 0)
>   		goto err_disable_sram;
> @@ -355,6 +394,7 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no
>   	struct scpsys_domain *pd;
>   	struct device_node *root_node = scpsys->dev->of_node;
>   	struct device_node *smi_node;
> +	struct device_node *larb_node;
>   	struct property *prop;
>   	const char *clk_name;
>   	int i, ret, num_clks;
> @@ -418,6 +458,25 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no
>   			return ERR_CAST(pd->smi);
>   	}
>   
> +	pd->num_larb = of_count_phandle_with_args(node, "mediatek,larb", NULL);

You must update bindings/power/mediatek,power-controller.yaml to allow the
mediatek,larb property in the power controller binding, otherwise this will
be unusable. Please do so.

Cheers,
Angelo