From: Lee Jones <lee.jones@linaro.org>
To: sathyanarayanan.kuppuswamy@linux.intel.com
Cc: gnurou@gmail.com, linus.walleij@linaro.org, edubezval@gmail.com,
dvhart@infradead.org, rui.zhang@intel.com, andy@infradead.org,
hdegoede@redhat.com, linux-gpio@vger.kernel.org,
platform-driver-x86@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org,
sathyaosid@gmail.com
Subject: Re: [PATCH v1 1/7] mfd: intel_soc_pmic_bxtwc: fix TMU interrupt index
Date: Wed, 12 Apr 2017 11:45:51 +0100 [thread overview]
Message-ID: <20170412104551.g2xkpihz2n2hju4m@dell> (raw)
In-Reply-To: <b8e952de94ed1902b922224de11f0814371b08b0.1491848776.git.sathyanarayanan.kuppuswamy@linux.intel.com>
On Mon, 10 Apr 2017, sathyanarayanan.kuppuswamy@linux.intel.com wrote:
> From: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
>
> TMU interrupts are registered as a separate interrupt chip, and
> hence it should start its interrupt index(BXTWC_TMU_IRQ) number
> from 0. But currently, BXTWC_TMU_IRQ is defined as part of enum
> bxtwc_irqs_level2 and its index value is 11. Since this index
> value is used when calculating .num_irqs of regmap_irq_chip_tmu,
> it incorrectly reports number of irqs as 12 instead of actual
> value of 1.
>
> static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = {
> REGMAP_IRQ_REG(BXTWC_TMU_IRQ, 0, 0x06),
> };
>
> static struct regmap_irq_chip bxtwc_regmap_irq_chip_tmu = {
> .name = "bxtwc_irq_chip_tmu",
> .status_base = BXTWC_TMUIRQ,
> .mask_base = BXTWC_MTMUIRQ,
> .irqs = bxtwc_regmap_irqs_tmu,
> .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_tmu),
> .num_regs = 1,
> };
>
> This patch fixes this issue by creating new enum of tmu irqs and
> resetting its starting index to 0.
>
> Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
> ---
> drivers/mfd/intel_soc_pmic_bxtwc.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
Patch looks fine, but please remove the code segment from the commit
log.
For the code:
For my own reference:
Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
> diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c b/drivers/mfd/intel_soc_pmic_bxtwc.c
> index 699c8c7..bb18e20 100644
> --- a/drivers/mfd/intel_soc_pmic_bxtwc.c
> +++ b/drivers/mfd/intel_soc_pmic_bxtwc.c
> @@ -94,7 +94,10 @@ enum bxtwc_irqs_level2 {
> BXTWC_GPIO0_IRQ,
> BXTWC_GPIO1_IRQ,
> BXTWC_CRIT_IRQ,
> - BXTWC_TMU_IRQ,
> +};
> +
> +enum bxtwc_irqs_tmu {
> + BXTWC_TMU_IRQ = 0,
> };
>
> static const struct regmap_irq bxtwc_regmap_irqs[] = {
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
next prev parent reply other threads:[~2017-04-12 10:45 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-10 18:52 [PATCH v1 1/7] mfd: intel_soc_pmic_bxtwc: fix TMU interrupt index sathyanarayanan.kuppuswamy
2017-04-10 18:52 ` [PATCH v1 2/7] mfd: intel_soc_pmic_bxtwc: remove thermal second level irqs sathyanarayanan.kuppuswamy
2017-04-12 11:45 ` Lee Jones
2017-04-10 18:52 ` [PATCH v1 3/7] thermal: intel_bxt_pmic_thermal: use first level PMIC thermal irq sathyanarayanan.kuppuswamy
2017-04-10 18:52 ` [PATCH v1 4/7] mfd: intel_soc_pmic_bxtwc: remove second level irq for gpio device sathyanarayanan.kuppuswamy
2017-04-12 11:46 ` Lee Jones
2017-04-10 18:52 ` [PATCH v1 5/7] gpio: gpio-wcove: use first level PMIC GPIO irq sathyanarayanan.kuppuswamy
2017-04-10 18:52 ` [PATCH v1 6/7] mfd: intel_soc_pmic_bxtwc: use chained irqs for second level irq chips sathyanarayanan.kuppuswamy
2017-04-12 11:53 ` Lee Jones
2017-04-13 21:45 ` sathyanarayanan kuppuswamy
2017-04-10 18:52 ` [PATCH v1 7/7] platform: x86: intel_bxtwc_tmu: remove first level irq unmask sathyanarayanan.kuppuswamy
2017-04-12 10:45 ` Lee Jones [this message]
2017-04-12 17:59 ` [PATCH v1 1/7] mfd: intel_soc_pmic_bxtwc: fix TMU interrupt index Sathyanarayanan Kuppuswamy Natarajan
2017-04-12 20:59 ` Lee Jones
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