From: bchihi@baylibre.com
To: daniel.lezcano@linaro.org,
angelogioacchino.delregno@collabora.com, rafael@kernel.org,
amitk@kernel.org, rui.zhang@intel.com, matthias.bgg@gmail.com,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
rdunlap@infradead.org, ye.xingchen@zte.com.cn,
p.zabel@pengutronix.de
Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org,
khilman@baylibre.com, james.lo@mediatek.com,
rex-bc.chen@mediatek.com
Subject: [PATCH v14 6/6] arm64: dts: mediatek: mt8195: Add temperature mitigation threshold
Date: Thu, 9 Feb 2023 11:56:28 +0100 [thread overview]
Message-ID: <20230209105628.50294-7-bchihi@baylibre.com> (raw)
In-Reply-To: <20230209105628.50294-1-bchihi@baylibre.com>
From: Balsam CHIHI <bchihi@baylibre.com>
The mt8195 SoC has several hotspots around the CPUs. Specify the
targeted temperature threshold when to apply the mitigation and define
the associated cooling devices.
Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 169 ++++++++++++++++++++---
1 file changed, 153 insertions(+), 16 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index c7e958f8f1b5a..10c8fb0856bc4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -14,6 +14,7 @@
#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
#include <dt-bindings/power/mt8195-power.h>
#include <dt-bindings/reset/mt8195-resets.h>
+#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/thermal/mediatek,lvts-thermal.h>
/ {
@@ -2413,107 +2414,243 @@ dp_tx: dp-tx@1c600000 {
thermal_zones: thermal-zones {
cpu0-thermal {
- polling-delay = <0>;
- polling-delay-passive = <0>;
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>;
+
trips {
+ cpu0_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
cpu0_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu0_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu1-thermal {
- polling-delay = <0>;
- polling-delay-passive = <0>;
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU1>;
+
trips {
+ cpu1_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
cpu1_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu1_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu2-thermal {
- polling-delay = <0>;
- polling-delay-passive = <0>;
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU2>;
+
trips {
+ cpu2_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
cpu2_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu2_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu3-thermal {
- polling-delay = <0>;
- polling-delay-passive = <0>;
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU3>;
+
trips {
+ cpu3_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
cpu3_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu3_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu4-thermal {
- polling-delay = <0>;
- polling-delay-passive = <0>;
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU0>;
+
trips {
+ cpu4_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
cpu4_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu4_alert>;
+ cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu5-thermal {
- polling-delay = <0>;
- polling-delay-passive = <0>;
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU1>;
+
trips {
+ cpu5_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
cpu5_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu5_alert>;
+ cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu6-thermal {
- polling-delay = <0>;
- polling-delay-passive = <0>;
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU2>;
+
trips {
+ cpu6_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
cpu6_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu6_alert>;
+ cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu7-thermal {
- polling-delay = <0>;
- polling-delay-passive = <0>;
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU3>;
+
trips {
+ cpu7_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
cpu7_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu7_alert>;
+ cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
};
};
--
2.34.1
next prev parent reply other threads:[~2023-02-09 10:57 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-09 10:56 [PATCH v14 0/6] Add LVTS Thermal Architecture bchihi
2023-02-09 10:56 ` [PATCH v14 1/6] thermal: drivers: mediatek: Relocate driver to mediatek folder bchihi
2023-02-09 10:56 ` [PATCH v14 2/6] dt-bindings: thermal: mediatek: Add LVTS thermal controllers bchihi
2023-02-09 19:07 ` Rob Herring
2023-02-10 9:09 ` Balsam CHIHI
2023-02-09 10:56 ` [PATCH v14 3/6] arm64: dts: mt8195: Add efuse node to mt8195 bchihi
2023-02-09 16:28 ` Matthias Brugger
2023-02-10 9:08 ` Balsam CHIHI
2023-02-09 10:56 ` [PATCH v14 4/6] thermal: drivers: mediatek: Add the Low Voltage Thermal Sensor driver bchihi
2023-02-09 10:56 ` [PATCH v14 5/6] arm64: dts: mediatek: mt8195: Add thermal zones and thermal nodes bchihi
2023-02-14 14:42 ` Balsam CHIHI
2023-02-09 10:56 ` bchihi [this message]
2023-02-14 14:43 ` [PATCH v14 6/6] arm64: dts: mediatek: mt8195: Add temperature mitigation threshold Balsam CHIHI
2023-02-15 12:50 ` AngeloGioacchino Del Regno
2023-02-15 13:13 ` Balsam CHIHI
2023-03-07 11:10 ` Balsam CHIHI
2023-03-31 10:36 ` Matthias Brugger
2023-03-31 11:11 ` Balsam CHIHI
2023-02-10 6:44 ` [PATCH v14 0/6] Add LVTS Thermal Architecture Daniel Lezcano
2023-02-10 9:12 ` Balsam CHIHI
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