[PATCH v2 0/2] Update highest frequency of a CPU after boot

[PATCH v2 0/2] Update highest frequency of a CPU after boot

[Srinivas Pandruvada]

Intel Xeon servers, which are capable of dynamic highest performance
change, are unable to achieve the highest frequency when the performance
profile is changed.

The highest frequency at which a CPU can operate is not fixed and can
vary after the system boots. These changes can be initiated by switching
to different performance profiles using the Intel Speed Select Technology
interface. Additionally, adjustments can be made remotely through a BMC
(Baseboard Management Controller) interface. Administrators can select
various performance profiles to align with specific performance
requirements, as these choices will directly influence the total power
consumption and cooling requirements.

Whenever an administrator switches to a different performance profile that
alters the highest frequency, the hardware sends an interrupt and update
the new highest frequency at which the system can operate. This interrupt
can be enabled via the MSR_HWP_INTERRUPT register, and only if support is
indicated by the CPUID[6].EAX[15] = 1.

To enable changes to the highest frequency, add a CPU features flag and 
enable the HWP (Hardware P-states) highest performance change interrupt
when it is supported by the CPU.

v2:
- Prevent display in /proc/cpuinfo flags
- Use cpu_feature_enabled() instead of boot_cpu_has()

Srinivas Pandruvada (2):
  x86/cpufeatures: Add HWP highest perf change feature flag
  cpufreq: intel_pstate: Support highest performance change interrupt

 arch/x86/include/asm/cpufeatures.h |  1 +
 drivers/cpufreq/intel_pstate.c     | 23 +++++++++++++++++++----
 2 files changed, 20 insertions(+), 4 deletions(-)

-- 
2.40.1

[PATCH v2 1/2] x86/cpufeatures: Add HWP highest perf change feature flag

[Srinivas Pandruvada]

When CPUID[6].EAX[15] is set to 1, this CPU supports notification for
HWP (Hardware P-states) highest performance change.

Add a feature flag to check if the CPU supports HWP highest performance
change.

Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
---
v2:
- Prevent display in /proc/cpuinfo flags as suggested by Borris

 arch/x86/include/asm/cpufeatures.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 3c7434329661..4cf929c457bb 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -361,6 +361,7 @@
 #define X86_FEATURE_HWP_ACT_WINDOW	(14*32+ 9) /* HWP Activity Window */
 #define X86_FEATURE_HWP_EPP		(14*32+10) /* HWP Energy Perf. Preference */
 #define X86_FEATURE_HWP_PKG_REQ		(14*32+11) /* HWP Package Level Request */
+#define X86_FEATURE_HWP_HIGHEST_PERF_CHANGE (14*32+15) /* "" HWP Highest perf change */
 #define X86_FEATURE_HFI			(14*32+19) /* Hardware Feedback Interface */
 
 /* AMD SVM Feature Identification, CPUID level 0x8000000a (EDX), word 15 */
-- 
2.40.1

[PATCH v2 2/2] cpufreq: intel_pstate: Support highest performance change interrupt

[Srinivas Pandruvada]

On some systems, the HWP (Hardware P-states) highest performance level
can change from the value set at boot-up. This behavior can lead to two
issues:

- The 'cpuinfo_max_freq' within the 'cpufreq' sysfs will not reflect
the CPU's highest achievable performance.
- Even if the CPU's highest performance level is increased after booting,
the CPU may not reach the full expected performance.

The availability of this feature is indicated by the CPUID instruction:
if CPUID[6].EAX[15] is set to 1, the feature is supported. When supported,
setting bit 2 of the MSR_HWP_INTERRUPT register enables notifications of
the highest performance level changes. Therefore, as part of enabling the
HWP interrupt, bit 2 of the MSR_HWP_INTERRUPT should also be set when this
feature is supported.

Upon a change in the highest performance level, a new HWP interrupt is
generated, with bit 3 of the MSR_HWP_STATUS register set, and the
MSR_HWP_CAPABILITIES register is updated with the new highest performance
limit.

The processing of the interrupt is the same as the guaranteed performance
change. Notify change to cpufreq core and update MSR_HWP_REQUEST with new
performance limits.

The current driver implementation already takes care of the highest
performance change as part of:
commit dfeeedc1bf57 ("cpufreq: intel_pstate: Update cpuinfo.max_freq
on HWP_CAP changes")

For example:
Before highest performance change interrupt:
cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
3700000
cat /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq
3700000

After highest performance changes interrupt:
cat /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq
3900000
cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
3900000

Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
---
v2
- Change from boot_cpu_has() to cpu_feature_enabled()
	as suggested by Borris

 drivers/cpufreq/intel_pstate.c | 23 +++++++++++++++++++----
 1 file changed, 19 insertions(+), 4 deletions(-)

diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c
index 15de5e3d96fd..8652555cbaae 100644
--- a/drivers/cpufreq/intel_pstate.c
+++ b/drivers/cpufreq/intel_pstate.c
@@ -1626,17 +1626,24 @@ static void intel_pstate_notify_work(struct work_struct *work)
 static DEFINE_SPINLOCK(hwp_notify_lock);
 static cpumask_t hwp_intr_enable_mask;
 
+#define HWP_GUARANTEED_PERF_CHANGE_STATUS      BIT(0)
+#define HWP_HIGHEST_PERF_CHANGE_STATUS         BIT(3)
+
 void notify_hwp_interrupt(void)
 {
 	unsigned int this_cpu = smp_processor_id();
+	u64 value, status_mask;
 	unsigned long flags;
-	u64 value;
 
 	if (!hwp_active || !boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
 		return;
 
+	status_mask = HWP_GUARANTEED_PERF_CHANGE_STATUS;
+	if (cpu_feature_enabled(X86_FEATURE_HWP_HIGHEST_PERF_CHANGE))
+		status_mask |= HWP_HIGHEST_PERF_CHANGE_STATUS;
+
 	rdmsrl_safe(MSR_HWP_STATUS, &value);
-	if (!(value & 0x01))
+	if (!(value & status_mask))
 		return;
 
 	spin_lock_irqsave(&hwp_notify_lock, flags);
@@ -1674,17 +1681,25 @@ static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata)
 		cancel_delayed_work_sync(&cpudata->hwp_notify_work);
 }
 
+#define HWP_GUARANTEED_PERF_CHANGE_REQ BIT(0)
+#define HWP_HIGHEST_PERF_CHANGE_REQ    BIT(2)
+
 static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata)
 {
-	/* Enable HWP notification interrupt for guaranteed performance change */
+	/* Enable HWP notification interrupt for performance change */
 	if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) {
+		u64 interrupt_mask = HWP_GUARANTEED_PERF_CHANGE_REQ;
+
 		spin_lock_irq(&hwp_notify_lock);
 		INIT_DELAYED_WORK(&cpudata->hwp_notify_work, intel_pstate_notify_work);
 		cpumask_set_cpu(cpudata->cpu, &hwp_intr_enable_mask);
 		spin_unlock_irq(&hwp_notify_lock);
 
+		if (cpu_feature_enabled(X86_FEATURE_HWP_HIGHEST_PERF_CHANGE))
+			interrupt_mask |= HWP_HIGHEST_PERF_CHANGE_REQ;
+
 		/* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
-		wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x01);
+		wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, interrupt_mask);
 		wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
 	}
 }
-- 
2.40.1

Re: [PATCH v2 1/2] x86/cpufeatures: Add HWP highest perf change feature flag

[Borislav Petkov]

On Mon, Jun 24, 2024 at 09:11:08AM -0700, Srinivas Pandruvada wrote:
> When CPUID[6].EAX[15] is set to 1, this CPU supports notification for
> HWP (Hardware P-states) highest performance change.
> 
> Add a feature flag to check if the CPU supports HWP highest performance
> change.
> 
> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
> ---
> v2:
> - Prevent display in /proc/cpuinfo flags as suggested by Borris
> 
>  arch/x86/include/asm/cpufeatures.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index 3c7434329661..4cf929c457bb 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -361,6 +361,7 @@
>  #define X86_FEATURE_HWP_ACT_WINDOW	(14*32+ 9) /* HWP Activity Window */
>  #define X86_FEATURE_HWP_EPP		(14*32+10) /* HWP Energy Perf. Preference */
>  #define X86_FEATURE_HWP_PKG_REQ		(14*32+11) /* HWP Package Level Request */
> +#define X86_FEATURE_HWP_HIGHEST_PERF_CHANGE (14*32+15) /* "" HWP Highest perf change */

Yeah, in the meantime I made it even simpler:

https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git/commit/?h=x86/cpu&id=78ce84b9e0a54a0c91a7449f321c1f852c0cd3fc

so in case you have to send your patch again, you can drop the "" too.

New flags are not exposed in /proc/cpuinfo by default after the above change.

Thx.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

Re: [PATCH v2 0/2] Update highest frequency of a CPU after boot

[Rafael J. Wysocki]

On Mon, Jun 24, 2024 at 6:11 PM Srinivas Pandruvada
<srinivas.pandruvada@linux.intel.com> wrote:
>
> Intel Xeon servers, which are capable of dynamic highest performance
> change, are unable to achieve the highest frequency when the performance
> profile is changed.
>
> The highest frequency at which a CPU can operate is not fixed and can
> vary after the system boots. These changes can be initiated by switching
> to different performance profiles using the Intel Speed Select Technology
> interface. Additionally, adjustments can be made remotely through a BMC
> (Baseboard Management Controller) interface. Administrators can select
> various performance profiles to align with specific performance
> requirements, as these choices will directly influence the total power
> consumption and cooling requirements.
>
> Whenever an administrator switches to a different performance profile that
> alters the highest frequency, the hardware sends an interrupt and update
> the new highest frequency at which the system can operate. This interrupt
> can be enabled via the MSR_HWP_INTERRUPT register, and only if support is
> indicated by the CPUID[6].EAX[15] = 1.
>
> To enable changes to the highest frequency, add a CPU features flag and
> enable the HWP (Hardware P-states) highest performance change interrupt
> when it is supported by the CPU.
>
> v2:
> - Prevent display in /proc/cpuinfo flags
> - Use cpu_feature_enabled() instead of boot_cpu_has()
>
> Srinivas Pandruvada (2):
>   x86/cpufeatures: Add HWP highest perf change feature flag
>   cpufreq: intel_pstate: Support highest performance change interrupt
>
>  arch/x86/include/asm/cpufeatures.h |  1 +
>  drivers/cpufreq/intel_pstate.c     | 23 +++++++++++++++++++----
>  2 files changed, 20 insertions(+), 4 deletions(-)
>
> --

Please let me know if there are objections against this from the x86 angle.

If not, I'll pick it up.

Thanks!

Re: [PATCH v2 0/2] Update highest frequency of a CPU after boot

[Rafael J. Wysocki]

On Tue, Jun 25, 2024 at 9:04 PM Rafael J. Wysocki <rafael@kernel.org> wrote:
>
> On Mon, Jun 24, 2024 at 6:11 PM Srinivas Pandruvada
> <srinivas.pandruvada@linux.intel.com> wrote:
> >
> > Intel Xeon servers, which are capable of dynamic highest performance
> > change, are unable to achieve the highest frequency when the performance
> > profile is changed.
> >
> > The highest frequency at which a CPU can operate is not fixed and can
> > vary after the system boots. These changes can be initiated by switching
> > to different performance profiles using the Intel Speed Select Technology
> > interface. Additionally, adjustments can be made remotely through a BMC
> > (Baseboard Management Controller) interface. Administrators can select
> > various performance profiles to align with specific performance
> > requirements, as these choices will directly influence the total power
> > consumption and cooling requirements.
> >
> > Whenever an administrator switches to a different performance profile that
> > alters the highest frequency, the hardware sends an interrupt and update
> > the new highest frequency at which the system can operate. This interrupt
> > can be enabled via the MSR_HWP_INTERRUPT register, and only if support is
> > indicated by the CPUID[6].EAX[15] = 1.
> >
> > To enable changes to the highest frequency, add a CPU features flag and
> > enable the HWP (Hardware P-states) highest performance change interrupt
> > when it is supported by the CPU.
> >
> > v2:
> > - Prevent display in /proc/cpuinfo flags
> > - Use cpu_feature_enabled() instead of boot_cpu_has()
> >
> > Srinivas Pandruvada (2):
> >   x86/cpufeatures: Add HWP highest perf change feature flag
> >   cpufreq: intel_pstate: Support highest performance change interrupt
> >
> >  arch/x86/include/asm/cpufeatures.h |  1 +
> >  drivers/cpufreq/intel_pstate.c     | 23 +++++++++++++++++++----
> >  2 files changed, 20 insertions(+), 4 deletions(-)
> >
> > --
>
> Please let me know if there are objections against this from the x86 angle.
>
> If not, I'll pick it up.

Applied now, as 6.11 material.

Thanks!