From: Andrew Jones <ajones@ventanamicro.com>
To: Nick Hu <nick.hu@sifive.com>
Cc: greentime.hu@sifive.com, zong.li@sifive.com,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
"Rafael J. Wysocki" <rafael@kernel.org>,
Pavel Machek <pavel@ucw.cz>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Anup Patel <anup@brainfault.org>,
Mayuresh Chitale <mchitale@ventanamicro.com>,
Conor Dooley <conor.dooley@microchip.com>,
Atish Patra <atishp@rivosinc.com>,
Samuel Holland <samuel.holland@sifive.com>,
Samuel Ortiz <sameo@rivosinc.com>,
Sunil V L <sunilvl@ventanamicro.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-pm@vger.kernel.org
Subject: Re: [PATCH v2 3/3] clocksource/drivers/timer-riscv: Stop stimecmp when cpu hotplug
Date: Thu, 26 Sep 2024 11:47:11 +0200 [thread overview]
Message-ID: <20240926-b0d87e489410fd9f83796a71@orel> (raw)
In-Reply-To: <20240926065422.226518-4-nick.hu@sifive.com>
On Thu, Sep 26, 2024 at 02:54:18PM GMT, Nick Hu wrote:
> Stop the stimecmp when the cpu is going to be off otherwise the timer
> stimecmp register while cpu non retention suspend.
This commit message seems to be missing some words. The comment below
reads much better.
Thanks,
drew
>
> Suggested-by: Anup Patel <anup@brainfault.org>
> Link: https://lore.kernel.org/lkml/20240829033904.477200-3-nick.hu@sifive.com/T/#u
> Signed-off-by: Nick Hu <nick.hu@sifive.com>
> ---
> drivers/clocksource/timer-riscv.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
> index 48ce50c5f5e6..166dee14e46b 100644
> --- a/drivers/clocksource/timer-riscv.c
> +++ b/drivers/clocksource/timer-riscv.c
> @@ -127,6 +127,12 @@ static int riscv_timer_starting_cpu(unsigned int cpu)
> static int riscv_timer_dying_cpu(unsigned int cpu)
> {
> disable_percpu_irq(riscv_clock_event_irq);
> + /*
> + * Stop the timer when the cpu is going to be offline otherwise
> + * the timer interrupt may be pending while performing power-down.
> + */
> + riscv_clock_event_stop();
> +
> return 0;
> }
>
> --
> 2.34.1
>
prev parent reply other threads:[~2024-09-26 9:47 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-26 6:54 [PATCH v2 0/3] Support SSTC while PM operations Nick Hu
2024-09-26 6:54 ` [PATCH v2 1/3] riscv: Add csr_read/write_hi_lo support Nick Hu
2024-09-26 7:59 ` Andrew Jones
[not found] ` <CAKddAkCJt5t_WyMuwSMb8qE4LHWy8GZ4QWZy6ViJvx-p5YBfuQ@mail.gmail.com>
2024-10-02 1:57 ` Nick Hu
2024-09-26 6:54 ` [PATCH v2 2/3] riscv: Add stimecmp save and restore Nick Hu
2024-09-26 6:54 ` [PATCH v2 3/3] clocksource/drivers/timer-riscv: Stop stimecmp when cpu hotplug Nick Hu
2024-09-26 9:40 ` Anup Patel
2024-09-26 9:47 ` Andrew Jones [this message]
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