From: Laura Nao <laura.nao@collabora.com>
To: srini@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, rafael@kernel.org,
daniel.lezcano@linaro.org, rui.zhang@intel.com,
lukasz.luba@arm.com, matthias.bgg@gmail.com,
angelogioacchino.delregno@collabora.com
Cc: wenst@chromium.org, nfraprado@collabora.com, arnd@arndb.de,
colin.i.king@gmail.com, u.kleine-koenig@baylibre.com,
andrew-ct.chen@mediatek.com, lala.lin@mediatek.com,
bchihi@baylibre.com, frank-w@public-files.de,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, kernel@collabora.com,
Laura Nao <laura.nao@collabora.com>
Subject: [PATCH v2 2/9] thermal/drivers/mediatek/lvts: Make number of calibration offsets configurable
Date: Wed, 30 Jul 2025 17:21:21 +0200 [thread overview]
Message-ID: <20250730152128.311109-3-laura.nao@collabora.com> (raw)
In-Reply-To: <20250730152128.311109-1-laura.nao@collabora.com>
MT8196/MT6991 use 2-byte eFuse calibration data, whereas other SoCs
supported by the driver rely on 3 bytes. Make the number of calibration
bytes per sensor configurable, enabling support for SoCs with varying
calibration formats.
Signed-off-by: Laura Nao <laura.nao@collabora.com>
---
drivers/thermal/mediatek/lvts_thermal.c | 32 +++++++++++++++++--------
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c
index f4d1e66d7db9..05aa8895ccce 100644
--- a/drivers/thermal/mediatek/lvts_thermal.c
+++ b/drivers/thermal/mediatek/lvts_thermal.c
@@ -96,12 +96,14 @@
#define LVTS_MINIMUM_THRESHOLD 20000
+#define LVTS_MAX_CAL_OFFSETS 3
+
static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT;
static int golden_temp_offset;
struct lvts_sensor_data {
int dt_id;
- u8 cal_offsets[3];
+ u8 cal_offsets[LVTS_MAX_CAL_OFFSETS];
};
struct lvts_ctrl_data {
@@ -127,6 +129,7 @@ struct lvts_data {
const struct lvts_ctrl_data *lvts_ctrl;
const u32 *conn_cmd;
const u32 *init_cmd;
+ int num_cal_offsets;
int num_lvts_ctrl;
int num_conn_cmd;
int num_init_cmd;
@@ -711,7 +714,7 @@ static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl
u8 *efuse_calibration,
size_t calib_len)
{
- int i;
+ int i, j;
u32 gt;
/* A zero value for gt means that device has invalid efuse data */
@@ -720,17 +723,18 @@ static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl
lvts_for_each_valid_sensor(i, lvts_ctrl_data) {
const struct lvts_sensor_data *sensor =
&lvts_ctrl_data->lvts_sensor[i];
+ u32 calib = 0;
- if (sensor->cal_offsets[0] >= calib_len ||
- sensor->cal_offsets[1] >= calib_len ||
- sensor->cal_offsets[2] >= calib_len)
- return -EINVAL;
+ for (j = 0; j < lvts_ctrl->lvts_data->num_cal_offsets; j++) {
+ u8 offset = sensor->cal_offsets[j];
+
+ if (offset >= calib_len)
+ return -EINVAL;
+ calib |= efuse_calibration[offset] << (8 * j);
+ }
if (gt) {
- lvts_ctrl->calibration[i] =
- (efuse_calibration[sensor->cal_offsets[0]] << 0) +
- (efuse_calibration[sensor->cal_offsets[1]] << 8) +
- (efuse_calibration[sensor->cal_offsets[2]] << 16);
+ lvts_ctrl->calibration[i] = calib;
} else if (lvts_ctrl->lvts_data->def_calibration) {
lvts_ctrl->calibration[i] = lvts_ctrl->lvts_data->def_calibration;
} else {
@@ -1763,6 +1767,7 @@ static const struct lvts_data mt7988_lvts_ap_data = {
.temp_factor = LVTS_COEFF_A_MT7988,
.temp_offset = LVTS_COEFF_B_MT7988,
.gt_calib_bit_offset = 24,
+ .num_cal_offsets = 3,
};
static const struct lvts_data mt8186_lvts_data = {
@@ -1776,6 +1781,7 @@ static const struct lvts_data mt8186_lvts_data = {
.temp_offset = LVTS_COEFF_B_MT7988,
.gt_calib_bit_offset = 24,
.def_calibration = 19000,
+ .num_cal_offsets = 3,
};
static const struct lvts_data mt8188_lvts_mcu_data = {
@@ -1789,6 +1795,7 @@ static const struct lvts_data mt8188_lvts_mcu_data = {
.temp_offset = LVTS_COEFF_B_MT8195,
.gt_calib_bit_offset = 20,
.def_calibration = 35000,
+ .num_cal_offsets = 3,
};
static const struct lvts_data mt8188_lvts_ap_data = {
@@ -1802,6 +1809,7 @@ static const struct lvts_data mt8188_lvts_ap_data = {
.temp_offset = LVTS_COEFF_B_MT8195,
.gt_calib_bit_offset = 20,
.def_calibration = 35000,
+ .num_cal_offsets = 3,
};
static const struct lvts_data mt8192_lvts_mcu_data = {
@@ -1815,6 +1823,7 @@ static const struct lvts_data mt8192_lvts_mcu_data = {
.temp_offset = LVTS_COEFF_B_MT8195,
.gt_calib_bit_offset = 24,
.def_calibration = 35000,
+ .num_cal_offsets = 3,
};
static const struct lvts_data mt8192_lvts_ap_data = {
@@ -1828,6 +1837,7 @@ static const struct lvts_data mt8192_lvts_ap_data = {
.temp_offset = LVTS_COEFF_B_MT8195,
.gt_calib_bit_offset = 24,
.def_calibration = 35000,
+ .num_cal_offsets = 3,
};
static const struct lvts_data mt8195_lvts_mcu_data = {
@@ -1841,6 +1851,7 @@ static const struct lvts_data mt8195_lvts_mcu_data = {
.temp_offset = LVTS_COEFF_B_MT8195,
.gt_calib_bit_offset = 24,
.def_calibration = 35000,
+ .num_cal_offsets = 3,
};
static const struct lvts_data mt8195_lvts_ap_data = {
@@ -1854,6 +1865,7 @@ static const struct lvts_data mt8195_lvts_ap_data = {
.temp_offset = LVTS_COEFF_B_MT8195,
.gt_calib_bit_offset = 24,
.def_calibration = 35000,
+ .num_cal_offsets = 3,
};
static const struct of_device_id lvts_of_match[] = {
--
2.39.5
next prev parent reply other threads:[~2025-07-30 15:22 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-30 15:21 [PATCH v2 0/9] Add thermal sensor driver support for Mediatek MT8196 Laura Nao
2025-07-30 15:21 ` [PATCH v2 1/9] dt-bindings: thermal: mediatek: Add LVTS thermal controller support for MT8196 Laura Nao
2025-07-31 7:31 ` AngeloGioacchino Del Regno
2025-07-30 15:21 ` Laura Nao [this message]
2025-07-31 3:10 ` [PATCH v2 2/9] thermal/drivers/mediatek/lvts: Make number of calibration offsets configurable Fei Shao
2025-08-01 7:28 ` AngeloGioacchino Del Regno
2025-07-30 15:21 ` [PATCH v2 3/9] thermal/drivers/mediatek/lvts: Guard against zero temp_factor in lvts_raw_to_temp Laura Nao
2025-07-31 3:46 ` Fei Shao
2025-08-01 7:28 ` AngeloGioacchino Del Regno
2025-07-30 15:21 ` [PATCH v2 4/9] thermal: mediatek: lvts: Add platform ops to support alternative conversion logic Laura Nao
2025-07-31 4:03 ` Fei Shao
2025-08-01 7:28 ` AngeloGioacchino Del Regno
2025-07-30 15:21 ` [PATCH v2 5/9] thermal/drivers/mediatek/lvts: Add lvts_temp_to_raw variant Laura Nao
2025-07-31 4:06 ` Fei Shao
2025-07-31 9:10 ` Chen-Yu Tsai
2025-08-01 7:28 ` AngeloGioacchino Del Regno
2025-07-30 15:21 ` [PATCH v2 6/9] thermal/drivers/mediatek/lvts: Add support for ATP mode Laura Nao
2025-07-31 4:25 ` Fei Shao
2025-07-31 10:14 ` Laura Nao
2025-08-01 4:44 ` Fei Shao
2025-08-01 7:28 ` AngeloGioacchino Del Regno
2025-07-30 15:21 ` [PATCH v2 7/9] thermal/drivers/mediatek/lvts: Support MSR offset for 16-bit calibration data Laura Nao
2025-08-01 7:28 ` AngeloGioacchino Del Regno
2025-07-30 15:21 ` [PATCH v2 8/9] thermal/drivers/mediatek/lvts_thermal: Add MT8196 support Laura Nao
2025-08-01 7:28 ` AngeloGioacchino Del Regno
2025-07-30 15:21 ` [PATCH v2 9/9] dt-bindings: nvmem: mediatek: efuse: Add support for MT8196 Laura Nao
2025-07-30 23:54 ` Rob Herring
2025-07-31 10:26 ` Laura Nao
2025-08-03 8:18 ` Krzysztof Kozlowski
2025-07-31 7:26 ` AngeloGioacchino Del Regno
2025-07-31 7:28 ` AngeloGioacchino Del Regno
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