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* Re: [PATCH AUTOSEL 6.18] tools/power/turbostat: Fix microcode patch level output for AMD/Hygon
@ 2026-04-20 21:03 Christian Ludloff
  2026-04-21  0:09 ` Serhii Pievniev
  0 siblings, 1 reply; 5+ messages in thread
From: Christian Ludloff @ 2026-04-20 21:03 UTC (permalink / raw)
  To: Sasha Levin
  Cc: Serhii Pievniev, Len Brown, lenb, patryk.wlazlyn, linux-pm,
	linux-kernel

> + if (get_msr(sched_getcpu(), MSR_IA32_UCODE_REV, &ucode_patch)) {

Intel prescribes a sequence of WRMSR(0x8B,0) + CPUID(1) + RDMSR.

This goes back to the original P6, where the upper half of the
BBL_CR_D3 L2 cache test register was abused to report the microcode
revision, and CPUID was abused to actually load the revision into said
MSR. Afaik the WRMSR(0x8B,0) is still required today.

turbostat has the prescribed CPUID(1) – by chance, a few lines earlier
– but it lacks the prescribed WRMSR(0x8B,0).

Also, note that the prescribed Intel sequence is neither required for
AMD, nor actually works for AMD – there the MSR is read-only.

--
C.

^ permalink raw reply	[flat|nested] 5+ messages in thread

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     [not found] <20260420132314.1023554-1-sashal@kernel.org>
2026-04-20 13:20 ` [PATCH AUTOSEL 6.18] tools/power turbostat: Fix --show/--hide for individual cpuidle counters Sasha Levin
2026-04-20 13:20 ` [PATCH AUTOSEL 7.0-5.10] power: supply: sbs-manager: normalize return value of gpio_get Sasha Levin
2026-04-20 13:20 ` [PATCH AUTOSEL 6.18] tools/power/turbostat: Fix microcode patch level output for AMD/Hygon Sasha Levin
2026-04-20 21:03 Christian Ludloff
2026-04-21  0:09 ` Serhii Pievniev

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