[PATCH] cpufreq: intel_pstate: Use CPPC to get scaling factor for Bartlett Lake

[Henry Tseng <henrytseng@qnap.com>]

Previously, hwp_get_cpu_scaling() returned INTEL_PSTATE_CORE_SCALING
(100000) as the scaling factor for non-hybrid CPUs.  However, this
value is too large for Bartlett Lake processors, where HWP
performance levels do not map 1:1 to PERF_CTL P-state ratios.

Per the Intel datasheet [1], the Intel Core 9 273PE specifies:

  Performance-cores:                                 12
  Efficient-cores:                                   0
  Max Turbo Frequency:                               5.7 GHz
  Intel Thermal Velocity Boost Frequency:            5.7 GHz
  Intel Turbo Boost Max Technology 3.0 Frequency:    5.6 GHz
  Performance-core Max Turbo Frequency:              5.4 GHz
  Performance-core Base Frequency:                   2.3 GHz

Because this CPU has no E-cores and does not report
X86_FEATURE_HYBRID_CPU, hwp_get_cpu_scaling() returns 100000.  In
intel_pstate_get_cpu_pstates(), the condition
cpu->pstate.scaling == perf_ctl_scaling then takes the early path
that simply multiplies HWP performance levels by 100000, producing
cpuinfo_max_freq values that exceed the documented maximum turbo
frequency:

  intel_pstate: CPU0: PERF_CTL turbo = 57
  intel_pstate: CPU0: HWP_CAP guaranteed = 30
  intel_pstate: CPU0: HWP_CAP highest = 70
  intel_pstate: CPU0: HWP-to-frequency scaling factor: 100000
  intel_pstate: set_policy cpuinfo.max 7000000 policy->max 7000000
  ...
  intel_pstate: CPU12: HWP_CAP highest = 73
  intel_pstate: CPU12: HWP-to-frequency scaling factor: 100000
  intel_pstate: set_policy cpuinfo.max 7300000 policy->max 7300000

To avoid impacting traditional non-hybrid CPUs, introduce a new
intel_cppc_scaling_ids[] table that lists non-hybrid CPU models
requiring dynamic scaling factor computation via CPPC.  CPUs in
this list call intel_pstate_cppc_get_scaling() instead of
core_get_scaling().

Because the scaling factor is now obtained from CPPC,
intel_pstate_hybrid_hwp_adjust() no longer takes the early return
on these CPUs.  To prevent hwp_is_hybrid from being set incorrectly
on non-hybrid systems (which would enable asymmetric capacity
scaling and disable ITMT), guard the assignment with
X86_FEATURE_HYBRID_CPU.

Since intel_pstate_hybrid_hwp_adjust() now also handles non-hybrid
processors, rename it to intel_pstate_hwp_adjust() and update the
kerneldoc and inline comments accordingly.

After this patch (Intel Core 9 273PE):

  intel_pstate: CPU0: PERF_CTL turbo = 57
  intel_pstate: CPU0: HWP_CAP guaranteed = 30
  intel_pstate: CPU0: HWP_CAP highest = 70
  intel_pstate: CPU0: HWP-to-frequency scaling factor: 79310
  intel_pstate: set_policy cpuinfo.max 5500000 policy->max 5500000
  ...
  intel_pstate: CPU12: HWP_CAP highest = 73
  intel_pstate: CPU12: HWP-to-frequency scaling factor: 79310
  intel_pstate: set_policy cpuinfo.max 5700000 policy->max 5700000

The scaling factor 79310 is computed from CPPC
nominal_freq=2300 MHz and nominal_perf=29.

The resulting sysfs values are:

  $ cat /sys/devices/system/cpu/cpufreq/policy*/cpuinfo_max_freq
  5500000  (20 CPUs with HWP_CAP highest = 70)
  5700000  ( 4 CPUs with HWP_CAP highest = 73)
  $ cat /sys/devices/system/cpu/cpufreq/policy*/scaling_max_freq
  5500000
  5700000

The reported maximum turbo frequency now matches the datasheet's
Max Turbo Frequency of 5.7 GHz.

[1] https://www.intel.com/content/www/us/en/products/sku/245717/intel-core-9-processor-273pe-36m-cache-up-to-5-70-ghz/specifications.html

Signed-off-by: Henry Tseng <henrytseng@qnap.com>
---
 drivers/cpufreq/intel_pstate.c | 37 +++++++++++++++++++++++-----------
 1 file changed, 25 insertions(+), 12 deletions(-)

diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c
index 1292da53e5fc..4d3dbea19eb7 100644
--- a/drivers/cpufreq/intel_pstate.c
+++ b/drivers/cpufreq/intel_pstate.c
@@ -557,17 +557,17 @@ static int intel_pstate_freq_to_hwp(struct cpudata *cpu, int freq)
 }
 
 /**
- * intel_pstate_hybrid_hwp_adjust - Calibrate HWP performance levels.
+ * intel_pstate_hwp_adjust - Calibrate HWP performance levels.
  * @cpu: Target CPU.
  *
- * On hybrid processors, HWP may expose more performance levels than there are
+ * On some processors, HWP may expose more performance levels than there are
  * P-states accessible through the PERF_CTL interface.  If that happens, the
  * scaling factor between HWP performance levels and CPU frequency will be less
  * than the scaling factor between P-state values and CPU frequency.
  *
  * In that case, adjust the CPU parameters used in computations accordingly.
  */
-static void intel_pstate_hybrid_hwp_adjust(struct cpudata *cpu)
+static void intel_pstate_hwp_adjust(struct cpudata *cpu)
 {
 	int perf_ctl_max_phys = cpu->pstate.max_pstate_physical;
 	int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
@@ -585,7 +585,8 @@ static void intel_pstate_hybrid_hwp_adjust(struct cpudata *cpu)
 	if (scaling == perf_ctl_scaling)
 		return;
 
-	hwp_is_hybrid = true;
+	if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU))
+		hwp_is_hybrid = true;
 
 	cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_pstate * scaling,
 					   perf_ctl_scaling);
@@ -1815,6 +1816,7 @@ static const struct attribute_group intel_pstate_attr_group = {
 };
 
 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[];
+static const struct x86_cpu_id intel_cppc_scaling_ids[];
 
 static struct kobject *intel_pstate_kobject;
 
@@ -2285,15 +2287,16 @@ static int hwp_get_cpu_scaling(int cpu)
 		return core_get_scaling();
 	}
 
-	/* Use core scaling on non-hybrid systems. */
-	if (!cpu_feature_enabled(X86_FEATURE_HYBRID_CPU))
-		return core_get_scaling();
-
 	/*
-	 * The system is hybrid, but the hybrid scaling factor is not known or
-	 * the CPU type is not one of the above, so use CPPC to compute the
-	 * scaling factor for this CPU.
+	 * Use core scaling on non-hybrid systems, except for those whose
+	 * perf-to-frequency scaling factor differs from the default
+	 * (e.g. Bartlett Lake) and must be computed via CPPC.
 	 */
+	if (!cpu_feature_enabled(X86_FEATURE_HYBRID_CPU) &&
+	    !x86_match_cpu(intel_cppc_scaling_ids))
+		return core_get_scaling();
+
+	/* Compute the scaling factor via CPPC. */
 	return intel_pstate_cppc_get_scaling(cpu);
 }
 
@@ -2328,7 +2331,7 @@ static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
 
 		if (pstate_funcs.get_cpu_scaling) {
 			cpu->pstate.scaling = pstate_funcs.get_cpu_scaling(cpu->cpu);
-			intel_pstate_hybrid_hwp_adjust(cpu);
+			intel_pstate_hwp_adjust(cpu);
 		} else {
 			cpu->pstate.scaling = perf_ctl_scaling;
 		}
@@ -3739,6 +3742,16 @@ static const struct x86_cpu_id intel_hybrid_scaling_factor[] = {
 	{}
 };
 
+/*
+ * Non-hybrid CPUs whose perf-to-frequency scaling factor differs from
+ * INTEL_PSTATE_CORE_SCALING. For these, compute the scaling factor
+ * dynamically via CPPC.
+ */
+static const struct x86_cpu_id intel_cppc_scaling_ids[] = {
+	X86_MATCH_VFM(INTEL_BARTLETTLAKE, NULL),
+	{}
+};
+
 static bool hwp_check_epp(void)
 {
 	if (boot_cpu_has(X86_FEATURE_HWP_EPP))
-- 
2.43.0