[PATCH v6 0/15] ACPI: CPPC: Fix register access and lifetime bugs

[PATCH v6 0/15] ACPI: CPPC: Fix register access and lifetime bugs

[Christian Loehle]

This series fixes correctness and robustness issues found while reviewing
the CPPC control path. They affect malformed _CPC handling, error
propagation, PCC ownership and cleanup, CPC object lifetime, register field
access, cross-processor aliases, and Performance Limited clearing.

Series structure
================

Patches 1-8 are deliberately small, independently useful fixes. They
validate the _CPC encoding consumed by cppc-acpi, propagate control-write
errors, serialize PCC payload updates, correct 64-bit field masks, and fix
descriptor and PCC lifetime handling.

Patches 9-15 are the register-layout hardening portion. Geometry validation
is more substantial because safe RMW and alias handling depend on the
physical access unit, not merely on a logical _CPC entry or _PSD domain.
These patches normalize and validate each supported address space before
building probe-only physical interval registries. Keeping this work in the
same posting gives the complete safety boundary and a single base for
review, while each transport and bug retains its own Fixes provenance.
Feel free to treat the two parts as independent series, I didn't split it
because they're all technically fixes and to get Sashiko review for the
whole lot.

No interval lookup is added to the scheduler hot path. Full-width
SystemMemory writes remain lockless. RMW locking remains necessary only for
a partial field, where we must preserve the other bits in its access
unit. The existing per-descriptor raw lock continues to cover disjoint
partial fields within one _CPC package; probe rejects cross-descriptor
layouts that it cannot protect.

Parsing and control semantics
=============================

The parser now validates the package header before indexing it, bounds the
BYTE and DWORD Integer forms before conversion, and validates the Generic
Register descriptor consumed by cppc-acpi. NumEntries may not exceed the
AML package count, but additional trailing package elements are ignored
because doing so is safe and preserves compatibility with padded firmware.
The parser likewise tolerates trailing ResourceTemplate data instead of
imposing a new EndTag compatibility requirement.

Capability values read from registers must also fit the u32 fields exposed
to CPPC callers. Reject wider values instead of truncating them, which could
otherwise turn Highest Performance into a zero divisor.

Writable controls must be Buffer-encoded registers. Minimum and Maximum
Performance are checked as the pair required by ACPI 6.6 Sections
8.4.6.1.2.1 and 8.4.6.1.2.2. Object presence is kept separate from the
Integer-zero convention for absent optional fields, so Lowest Performance
may retain the valid abstract value zero.

Performance Limited is one deliberate compatibility exception. ACPI lists
it as required, but permits a platform with no limiting indication to
always return zero, and deployed firmware represents that case with a NULL
descriptor. CPPC control does not depend on this status register, so we
continue to accept that encoding. A present _CPC package which otherwise
fails parsing or initialization now emits an error instead of silently
preventing cpufreq registration.

Compound performance and EPP updates propagate errors and perform every
fallible non-PCC write before modifying the PCC payload. Updates across
address spaces cannot be atomic, but a known non-PCC failure can no longer
commit only the PCC portion or leave an unsent value for a later command.
All requested PCC fields are validated before the first payload store, so
a malformed later field cannot leave an earlier value for a subsequent
doorbell to commit. Writable Minimum and Maximum Performance controls are
programmed even when their requested value is zero, because zero can be a
valid abstract performance level rather than an omitted update.

SystemMemory locking and support boundary
=========================================

A partial SystemMemory field requires RMW to preserve the rest of its
access unit. Commit 60949b7b8054 ("ACPI: CPPC: Fix MASK_VAL() usage") used
a per-_CPC lock and noted that a global lock would be needed if physical
registers were shared between packages.

ACPI does not make _PSD a physical-register ownership boundary. Rather than
put a global raw lock or lookup into the scheduler path, this series makes
the cheaper per-descriptor model's assumptions enforceable at probe.

Supported SystemMemory layouts are:

  - naturally aligned 8-, 16-, 32-, and 64-bit access units;
  - lockless full-width controls;
  - read-only aliases;
  - exact writable aliases, including partial aliases of the same logical
    field, when the complete access is one aligned native transaction;
  - disjoint partial writers within one descriptor, serialized by its
    rmw_lock, when neither must preserve another write-only field; and
  - a partial writer sharing an access unit with a disjoint read-only
    field, except Performance Limited.

Probe rejects overlapping logical fields involving a writer, another field
inside a full-width writable access unit, non-identical cross-descriptor
partial writers, writers sharing Performance Limited's access unit, writers
which would preserve a write-only neighbour, unaligned accesses, and exact
writable 64-bit aliases on 32-bit kernels. These layouts were not safely
supported by the old per-descriptor lock or generic writeq(); rejecting them
turns possible corruption into a visible probe failure rather than removing
working support.

PCC access and locking
======================

The PCC protocol requires OSPM to acquire the subspace before changing its
command or payload. Single-register and EPP updates now hold pcc_lock
across ownership acquisition, payload staging, and command submission.
Concurrent Phase-I callers intentionally store the same true value to the
pending-command flag under the shared side of pcc_lock, so that store uses
WRITE_ONCE(); transitions back to false remain exclusively locked.

ACPI 6.6's implementation example places a mandatory 32-bit Delivered
Performance Counter at unaligned PCC offset 0x116. Performance controls may
also use byte-multiple widths such as 24 bits. PCC therefore uses
byte-oriented I/O with explicit little-endian encoding for zero-offset,
byte-multiple fields from 8 through 64 bits. A short per-subspace payload
lock protects concurrent aliased copies made under the shared side of
pcc_lock; it does not replace the protocol ownership lock.

Bit-level PCC fields require RMW and remain unsupported. An unsupported
optional field is marked absent, but a present inaccessible CPPC Enable
fails probe because OSPM must write it before using CPPC. Thus the
ACPI-legal one-bit CPPC Enable used by the specification example is a
documented kernel limitation. The old accessor could not program it
correctly either, so an explicit error is safer than silently proceeding
without enabling CPPC.

Every retained PCC field is bounds checked against the shared-memory
region. A subspace-keyed interval registry permits read-only overlap and
exact same-control aliases while rejecting every other writable overlap
across processors. A lifecycle mutex serializes allocation, reference
updates, first channel setup, and teardown of each shared PCC object.

SystemIO support boundary
=========================

SystemIO supports Bit Offset zero, naturally aligned, full 8-, 16-, or
32-bit accesses ending at or below port 0xffff, including legacy Access
Size zero when Bit Width supplies the size. Partial fields never worked
because the driver neither shifted them nor preserved adjacent bits, so
they now fail visibly instead of being misprogrammed.

On kernels without CONFIG_HAS_IOPORT, SystemIO entries are rejected or
disabled according to the affected control's semantics. Runtime accessors
also return -EOPNOTSUPP rather than treating an I/O port as a
physical-memory address. A global port interval registry rejects
cross-processor writable overlap.

Write-only and Performance Limited controls
===========================================

Between _CPC revisions 3 and 4, Desired Performance changed from
Read/Write to Write, and revision 4 added write-only OSPM Nominal
Performance. ACPI 6.6 Section 4.6.3 says reads from write-only positions
are undefined. Explicit reads of both controls are rejected. Partial
SystemMemory fields remain writable because RMW replaces every bit of the
field and therefore does not propagate its undefined readback, provided no
other writer shares the access unit and would preserve that field.

Performance Limited is sticky, write-zero-to-clear, and requires
interlocked accesses under ACPI 6.6 Section 8.4.6.1.3.2. The old separate
read and write could clear a new event reported between transactions. The
clear path now writes zero only to requested status bits and one to the
other defined bits. Partial SystemMemory forms remain readable but cannot
be cleared because a spinlock cannot interlock an enclosing RMW with
platform updates. Probe also rejects another writable field sharing its
access unit. QWord forms cannot be used on 32-bit kernels, where the MMIO
accessor may be split into two 32-bit operations; naturally aligned,
full-width QWords remain supported on 64-bit kernels. Since CPPC control
does not depend on Performance Limited status, an unreadable description
marks status access unsupported instead of rejecting the processor's
otherwise usable _CPC. Its physical range remains visible to overlap
validation so another writer cannot evade the status-register conflict.

Lifetime and cleanup
====================

CPC descriptors are released through their kobject callback, keeping their
storage and mappings alive for outstanding sysfs references. Every PCC
allocation, reference, and acquired channel is unwound on probe failure,
and the per-CPU PCC index is initialized before every early return. PCC
allocation uses a separate temporary result, so its success cannot turn a
later parse failure into a successful probe return. Shared PCC allocation,
reference updates, channel initialization, and teardown are serialized. A
repeated processor start reuses an already published descriptor instead of
resetting its PCC index and leaking or detaching the existing state.

Changes since v5
================

  - Kept Lowest Performance zero valid while starting the arm64 artificial
    energy model at its first positive capacity step, and made every
    present _CPC initialization failure emit the common CPU/errno
    diagnostic.
  - Checked completion of a preceding PCC command before writing the direct
    half of a mixed-address-space performance request.
  - Coalesced exact SystemMemory aliases behind one interval-tree node and
    promoted a live alias on teardown, avoiding quadratic probe work on
    large systems. Also skipped registry allocations for descriptors with
    no entries in the corresponding address space.
  - Stopped treating unused Performance Reduction Tolerance and Time Window
    entries as writers, and retained disjoint fields when a narrower
    full-width write cannot touch the overlapping read-only access unit.
  - Preserved inaccessible write-only controls in physical overlap
    validation, and tested whether the other writer's access unit actually
    covers the write-only field before rejecting an asymmetric layout.
  - Restricted writable PCC controls to their DWORD width, coherently
    disabled an inaccessible Minimum/Maximum pair, and ordered PCC payload
    bytes against completion and doorbell accesses.
  - Classified a SystemMemory field as writable during overlap validation
    only when both its _CPC semantics and validated access permit writes.
    This keeps partial Performance Limited status fields shareable after
    their unsafe clear path has been disabled, while still rejecting an
    actual writer sharing the status access unit.
  - Preserved an inaccessible 64-bit Performance Limited physical range on
    32-bit kernels while marking reads and writes unsupported, so a
    neighbouring writer remains detectable without mapping a split access.

Changes since v4
================

  - Validated all requested PCC control widths before the first payload
    store, preventing a later malformed field from leaving an earlier
    staged value for a subsequent doorbell to commit.
  - Marked the intentional concurrent same-value pending-command store with
    WRITE_ONCE().
  - Serialized shared PCC allocation, reference updates, channel setup, and
    teardown, and published channel readiness only after initializing its
    lock and wait queue.
  - Rejected another writable field sharing a SystemMemory access unit with
    a write-only field, because its RMW would preserve and replay undefined
    readback.
  - Rejected capability values which do not fit the u32 interface instead
    of allowing truncation and a possible zero divisor.
  - Programmed writable Minimum and Maximum Performance controls when the
    requested value is zero, which is valid when Lowest Performance is zero.
  - Reused an existing CPC descriptor on a repeated processor start instead
    of resetting its PCC index before a retry could fail.

Changes since v3
================

  - Allowed partial SystemMemory Desired and OSPM Nominal controls when RMW
    discards their undefined readback, supporting NVIDIA's separate 9-bit
    controls in _CPC revision 4.
  - Reported an unavailable Desired Performance control as unsupported from
    the common getter instead of returning a synthetic zero.
  - Required natural alignment for SystemIO access units, preventing faults
    on architectures which implement port I/O through Device-memory MMIO.
  - Kept partial Performance Limited fields readable but not clearable,
    rejected another writer sharing their access unit, reported fully
    inaccessible forms as unsupported instead of returning a synthetic
    zero, and consolidated each nonfatal fallback into a single warning.

Changes since v2
================

  - Relaxed the exact NumEntries/package-count match to tolerate safe
    trailing package elements while still rejecting any count that could
    cause an out-of-bounds walk.
  - Made patch 10 independently preserve immutable-autonomous setups whose
    inaccessible Desired Performance register requires RMW, rather than
    relying on patch 11 to restore that exception.

Sashiko v2 review not addressed
===============================

  - Kept Guaranteed Performance Buffer-only. The suggestion was to accept a
    nonzero Integer, but ACPI 6.6 Table 8.23 permits only a Buffer for this
    entry.

Sashiko v4/v5 review requiring no code change
=============================================

  - Kept nonzero Integers restricted to entries whose object type includes
    Integer in ACPI 6.6 Table 8.23. Guaranteed Performance and Energy
    Performance Preference are Buffer-only registers.
  - Kept Desired Performance optional only when OSPM advertises CPPC2 and
    Autonomous Selection Enable is encoded as Integer 1. ACPI 6.6 Section
    8.4.6.1.2.3 explicitly requires that immutable encoding; a writable
    Buffer does not qualify.

Deferred follow-up work
=======================

Sashiko also identified a broader pre-existing lifetime question which this
series does not attempt to solve. In-kernel accessors read the per-CPU
cpc_desc_ptr without acquiring a reference, while processor teardown can
unpublish and eventually release the descriptor and its PCC data. The
kobject change here fixes the concrete sysfs lifetime bug, but a NULL
pcc_data check would not protect a caller which already holds a stale
pointer. Closing this properly requires defining the kernel accessor
lifetime contract and then using CPU-hotplug serialization / safe
referencing across all callers, therefore will be handled by a follow-up.

ACPI-legal bit-level PCC and SystemIO fields also remain unsupported. In
particular, the ACPI example's one-bit PCC CPPC Enable register cannot be
implemented by the old whole-value accessors. Supporting these
descriptions requires transport-specific field extraction and an RMW
operation which obeys PCC ownership or safely preserves adjacent SystemIO
bits, just accepting the descriptors would silently program the wrong
value. Therefore continue to disable optional inaccessible fields where
safe and reject a present inaccessible CPPC Enable control.
Full support, if even needed, belongs in a separate follow-up.

The review additionally suggested validating the complete AML
ResourceTemplate, including its EndTag. We currently validate the Register
descriptor we consume and tolerate trailing firmware data. I don't really
see the point of ever doing this, but definitely not in this series,
where I'm trying to guarantee that no reasonably working platform is
regressing.

Patches 1, 2, 4-7, and 9 address findings reported by Sashiko while
reviewing:

  https://sashiko.dev/#/patchset/20260724134251.1632824-1-christian.loehle%40arm.com

Patches 3, 5, 6, 9, 10, and 15 address findings from the follow-up review:

  https://sashiko.dev/#/patchset/20260807111303.1062391-1-christian.loehle%40arm.com

Patches 1 and 10 address findings from the v2 review:

  https://sashiko.dev/#/patchset/20260808082644.1251332-1-christian.loehle%40arm.com

Christian Loehle (15):
  ACPI: CPPC: Validate the _CPC package header
  ACPI: CPPC: Validate _CPC entry and control semantics
  ACPI: CPPC: Propagate performance-control write errors
  ACPI: CPPC: Use 64-bit masks for register fields
  ACPI: CPPC: Serialize PCC single-register payload updates
  ACPI: CPPC: Serialize PCC EPP payload updates
  ACPI: CPPC: Release CPC descriptors through kobject
  ACPI: CPPC: Release PCC data after probe failures
  ACPI: CPPC: Reject unsafe cross-CPU SystemMemory RMW
  ACPI: CPPC: Reject direct reads of write-only controls
  ACPI: CPPC: Validate and access PCC register layouts
  ACPI: CPPC: Validate SystemIO register layouts
  ACPI: CPPC: Validate PCC overlaps across processors
  ACPI: CPPC: Validate SystemIO overlaps across processors
  ACPI: CPPC: Clear Performance Limited without a stale read

 drivers/acpi/cppc_acpi.c     | 1807 ++++++++++++++++++++++++++++++++++++------
 drivers/cpufreq/amd-pstate.c |   12 +-
 include/acpi/cppc_acpi.h     |   11 +-
 3 files changed, 1569 insertions(+), 261 deletions(-)

base-commit: 08dbfad3f5040f5bdb6c529da20d6d4e81fefd72
--
2.34.1

[PATCH v6 01/15] ACPI: CPPC: Validate the _CPC package header

[Christian Loehle]

The _CPC NumEntries field includes every package element, including
NumEntries and Revision. acpi_cppc_processor_probe() nevertheless reads
those first two elements before checking that they exist and trusts
NumEntries when walking the remaining elements.

Reject packages with fewer than two elements and NumEntries values which
exceed the package count before accessing Revision or iterating over
register descriptors. Although the specification defines NumEntries as the
number of package elements, tolerate additional trailing elements because
ignoring them is safe and avoids rejecting padded firmware.

Revision is specified as a BYTE, but the parser assigns its 64-bit AML
Integer to an unsigned int before validating it. Reject values above U8_MAX
before conversion so, for example, 0x100000004 cannot truncate to revision
4.

Fixes: 337aadff8e45 ("ACPI: Introduce CPU performance controls using CPPC")
Reported-by: Sashiko <sashiko-bot@kernel.org>
Link: https://sashiko.dev/#/patchset/20260724134251.1632824-1-christian.loehle%40arm.com
Link: https://sashiko.dev/#/patchset/20260808082644.1251332-1-christian.loehle%40arm.com
Signed-off-by: Christian Loehle <christian.loehle@arm.com>
---
 drivers/acpi/cppc_acpi.c | 22 ++++++++++++++++++----
 1 file changed, 18 insertions(+), 4 deletions(-)

diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
index fef54fcd00b7..3b8cdf88e31d 100644
--- a/drivers/acpi/cppc_acpi.c
+++ b/drivers/acpi/cppc_acpi.c
@@ -793,6 +793,11 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 	}
 
 	out_obj = (union acpi_object *) output.pointer;
+	if (out_obj->package.count < 2) {
+		pr_debug("Unexpected _CPC package count (%u) for CPU:%d\n",
+			 out_obj->package.count, pr->id);
+		goto out_buf_free;
+	}
 
 	cpc_ptr = kzalloc_obj(struct cpc_desc);
 	if (!cpc_ptr) {
@@ -803,12 +808,15 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 	/* First entry is NumEntries. */
 	cpc_obj = &out_obj->package.elements[0];
 	if (cpc_obj->type == ACPI_TYPE_INTEGER)	{
-		num_ent = cpc_obj->integer.value;
-		if (num_ent <= 1) {
-			pr_debug("Unexpected _CPC NumEntries value (%d) for CPU:%d\n",
-				 num_ent, pr->id);
+		if (cpc_obj->integer.value < 2 ||
+		    cpc_obj->integer.value > out_obj->package.count) {
+			pr_debug("Invalid _CPC NumEntries (%llu) for package count (%u) on CPU:%d\n",
+				 cpc_obj->integer.value, out_obj->package.count,
+				 pr->id);
 			goto out_free;
 		}
+
+		num_ent = cpc_obj->integer.value;
 	} else {
 		pr_debug("Unexpected _CPC NumEntries entry type (%d) for CPU:%d\n",
 			 cpc_obj->type, pr->id);
@@ -818,6 +826,12 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 	/* Second entry should be revision. */
 	cpc_obj = &out_obj->package.elements[1];
 	if (cpc_obj->type == ACPI_TYPE_INTEGER)	{
+		if (cpc_obj->integer.value > U8_MAX) {
+			pr_debug("Invalid _CPC Revision (%llu) for CPU:%d\n",
+				 cpc_obj->integer.value, pr->id);
+			ret = -EINVAL;
+			goto out_free;
+		}
 		cpc_rev = cpc_obj->integer.value;
 	} else {
 		pr_debug("Unexpected _CPC Revision entry type (%d) for CPU:%d\n",
-- 
2.34.1

[PATCH v6 02/15] ACPI: CPPC: Validate _CPC entry and control semantics

[Christian Loehle]

Writable _CPC controls are Register descriptors encoded as Buffer objects.
Integer entries represent fixed values or unsupported optional registers;
Autonomous Selection Integer 1 is the special immutable form which enables
operation without Desired Performance.

The parser accepts arbitrary object types and cpc_write() assumes that its
argument contains a GAS. Malformed firmware can therefore make it interpret
an Integer union member as a register.

Validate the portion of each encoding consumed by the driver: bound Integer
DWORD forms to 32 bits, and require Buffer entries to start with a complete
Generic Register descriptor with the expected header. Continue tolerating
Integer 0 for an absent optional register and retain type checks in
cpc_write() as defense in depth. Reject an attempt to disable immutable
Autonomous Selection instead of silently applying only the EPP part of the
request.

Capability registers are read into u64 temporaries but exposed through u32
fields. Reject values above U32_MAX instead of allowing them to be
truncated. In particular, a truncated Highest Performance value can become
a zero divisor in the performance-to-frequency conversion. Enforce the
required ordering from Highest through Nominal, Lowest Nonlinear, and
Lowest Performance, and constrain a present Guaranteed Performance to the
inclusive Lowest-to-Nominal range. Also reject reversed frequency anchors
and unequal frequency anchors with identical performance anchors. Those
invalid tuples otherwise make affine-conversion differences wrap or divide
by zero.

Check mandatory object presence separately from the Integer-zero convention
for absent optional fields. ACPI does not reserve zero in the abstract
Lowest Performance scale, so accept a present Lowest Performance DWORD of
zero when distinct frequency anchors provide a usable nonzero physical
minimum. Retain the old rejection when that mapping is unavailable and the
fallback conversion would expose a 0 kHz cpufreq endpoint.

Minimum Performance also defines zero as a real no-limit value, but the
exported cppc_set_perf() interface historically used zero to omit a bound.
Add explicit validity flags so callers can request zero without changing
that legacy convention. Populate the flags when reading the controls and
mark the bounds supplied by amd-pstate explicitly.

Performance Limited is listed as a required Buffer, but the interface does
not depend on it to control performance and the specification permits a
platform with no limiting indication to always report zero. Preserve
the compatibility with firmware that represents that case using a NULL
register descriptor instead of disabling CPPC entirely.

Emit an error when a present _CPC package fails parsing or initialization
so such firmware and resource failures no longer silently suppress cpufreq.
Initialize malformed-package failures to -EINVAL and preserve specific
allocation, mapping, and unsupported-access errors in that diagnostic.

Fixes: 337aadff8e45 ("ACPI: Introduce CPU performance controls using CPPC")
Reported-by: Sashiko <sashiko-bot@kernel.org>
Link: https://sashiko.dev/#/patchset/20260724134251.1632824-1-christian.loehle%40arm.com
Signed-off-by: Christian Loehle <christian.loehle@arm.com>
---
 drivers/acpi/cppc_acpi.c     | 172 ++++++++++++++++++++++++++++++-----
 drivers/cpufreq/amd-pstate.c |  12 ++-
 include/acpi/cppc_acpi.h     |   2 +
 3 files changed, 159 insertions(+), 27 deletions(-)

diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
index 3b8cdf88e31d..6f3ffa4a1845 100644
--- a/drivers/acpi/cppc_acpi.c
+++ b/drivers/acpi/cppc_acpi.c
@@ -129,6 +129,21 @@ static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
 				!!(cpc)->cpc_entry.int_value :		\
 				!IS_NULL_REG(&(cpc)->cpc_entry.reg))
 
+static bool cpc_is_writable(const struct cpc_register_resource *cpc)
+{
+	return cpc->type == ACPI_TYPE_BUFFER &&
+	       !IS_NULL_REG(&cpc->cpc_entry.reg);
+}
+
+static bool cpc_entry_present(const struct cpc_register_resource *cpc)
+{
+	if (cpc->type == ACPI_TYPE_INTEGER)
+		return true;
+
+	return cpc->type == ACPI_TYPE_BUFFER &&
+	       !IS_NULL_REG(&cpc->cpc_entry.reg);
+}
+
 /*
  * Each bit indicates the optionality of the register in per-cpu
  * cpc_regs[] with the corresponding index. 0 means mandatory and 1
@@ -142,6 +157,29 @@ static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
  */
 #define IS_OPTIONAL_CPC_REG(reg_idx) (REG_OPTIONAL & (1U << (reg_idx)))
 
+static bool cpc_integer_entry_valid(unsigned int reg_idx, u64 value)
+{
+	switch (reg_idx) {
+	case HIGHEST_PERF:
+	case NOMINAL_PERF:
+	case LOW_NON_LINEAR_PERF:
+	case LOWEST_PERF:
+	case CTR_WRAP_TIME:
+	case REFERENCE_PERF:
+	case LOWEST_FREQ:
+	case NOMINAL_FREQ:
+		return value <= U32_MAX;
+	case AUTO_SEL_ENABLE:
+		return value <= 1;
+	case DESIRED_PERF:
+		/* Validated against Autonomous Selection after parsing. */
+		return value == 0;
+	default:
+		/* Tolerate the customary Integer 0 for an absent option. */
+		return value == 0 && IS_OPTIONAL_CPC_REG(reg_idx);
+	}
+}
+
 /*
  * Arbitrary Retries in case the remote processor is slow to respond
  * to PCC commands. Keeping it high enough to cover emulators where
@@ -150,6 +188,8 @@ static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
 #define NUM_RETRIES 500ULL
 
 #define OVER_16BTS_MASK ~0xFFFFULL
+#define CPC_GENERIC_REGISTER_DESCRIPTOR 0x82
+#define CPC_GENERIC_REGISTER_LENGTH (sizeof(struct cpc_reg) - 3)
 
 #define define_one_cppc_ro(_name)		\
 static struct kobj_attribute _name =		\
@@ -773,8 +813,10 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 	acpi_handle handle = pr->handle;
 	unsigned int num_ent, i, cpc_rev;
 	int pcc_subspace_id = -1;
+	bool cpc_present = false;
 	acpi_status status;
 	int ret = -ENODATA;
+	int err;
 
 	if (!osc_sb_cppc2_support_acked) {
 		pr_debug("CPPC v2 _OSC not acked\n");
@@ -791,6 +833,8 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 		ret = -ENODEV;
 		goto out_buf_free;
 	}
+	cpc_present = true;
+	ret = -EINVAL;
 
 	out_obj = (union acpi_object *) output.pointer;
 	if (out_obj->package.count < 2) {
@@ -871,11 +915,32 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 		cpc_obj = &out_obj->package.elements[i];
 
 		if (cpc_obj->type == ACPI_TYPE_INTEGER)	{
-			cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER;
-			cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value;
+			if (!cpc_integer_entry_valid(i - 2,
+						     cpc_obj->integer.value)) {
+				pr_debug("Invalid Integer _CPC register %u for CPU:%d\n",
+					 i - 2, pr->id);
+				ret = -EINVAL;
+				goto out_free;
+			}
+			cpc_ptr->cpc_regs[i - 2].type = ACPI_TYPE_INTEGER;
+			cpc_ptr->cpc_regs[i - 2].cpc_entry.int_value = cpc_obj->integer.value;
 		} else if (cpc_obj->type == ACPI_TYPE_BUFFER) {
+			if (cpc_obj->buffer.length < sizeof(*gas_t)) {
+				pr_debug("Invalid register descriptor for CPU:%d\n",
+					 pr->id);
+				ret = -EINVAL;
+				goto out_free;
+			}
+
 			gas_t = (struct cpc_reg *)
 				cpc_obj->buffer.pointer;
+			if (gas_t->descriptor != CPC_GENERIC_REGISTER_DESCRIPTOR ||
+			    gas_t->length != CPC_GENERIC_REGISTER_LENGTH) {
+				pr_debug("Invalid register resource for CPU:%d\n",
+					 pr->id);
+				ret = -EINVAL;
+				goto out_free;
+			}
 
 			/*
 			 * The PCC Subspace index is encoded inside
@@ -886,8 +951,11 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 			if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
 				if (pcc_subspace_id < 0) {
 					pcc_subspace_id = gas_t->access_width;
-					if (pcc_data_alloc(pcc_subspace_id))
+					err = pcc_data_alloc(pcc_subspace_id);
+					if (err) {
+						ret = err;
 						goto out_free;
+					}
 				} else if (pcc_subspace_id != gas_t->access_width) {
 					pr_debug("Mismatched PCC ids in _CPC for CPU:%d\n",
 						 pr->id);
@@ -900,14 +968,18 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 
 					if (!osc_cpc_flexible_adr_space_confirmed) {
 						pr_debug("Flexible address space capability not supported\n");
+						ret = -EOPNOTSUPP;
 						if (!cpc_supported_by_cpu())
 							goto out_free;
+						ret = -EINVAL;
 					}
 
 					access_width = GET_BIT_WIDTH(gas_t) / 8;
 					addr = ioremap(gas_t->address, access_width);
-					if (!addr)
+					if (!addr) {
+						ret = -ENOMEM;
 						goto out_free;
+					}
 					cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr;
 				}
 			} else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
@@ -929,14 +1001,17 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 				}
 				if (!osc_cpc_flexible_adr_space_confirmed) {
 					pr_debug("Flexible address space capability not supported\n");
+					ret = -EOPNOTSUPP;
 					if (!cpc_supported_by_cpu())
 						goto out_free;
+					ret = -EINVAL;
 				}
 			} else {
 				if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) {
 					/* Support only PCC, SystemMemory, SystemIO, and FFH type regs. */
 					pr_debug("Unsupported register type (%d) in _CPC\n",
 						 gas_t->space_id);
+					ret = -EOPNOTSUPP;
 					goto out_free;
 				}
 			}
@@ -961,15 +1036,35 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 	}
 	per_cpu(cpu_pcc_subspace_idx, pr->id) = pcc_subspace_id;
 
+	/*
+	 * Performance Limited is required by the specification, but tolerate a
+	 * NULL descriptor used by firmware which cannot report limiting events.
+	 * CPPC control does not depend on this status.
+	 */
+	for (i = 0; i < num_ent - 2; i++) {
+		if (i != DESIRED_PERF && i != PERF_LIMITED &&
+		    !IS_OPTIONAL_CPC_REG(i) &&
+		    !cpc_entry_present(&cpc_ptr->cpc_regs[i])) {
+			pr_debug("CPU:%d lacks mandatory _CPC register %u\n",
+				 pr->id, i);
+			ret = -EINVAL;
+			goto out_free;
+		}
+	}
+
 	/*
 	 * In CPPC v1, DESIRED_PERF is mandatory. In CPPC v2, it is optional
 	 * only when AUTO_SEL_ENABLE is supported.
 	 */
-	if (!CPC_SUPPORTED(&cpc_ptr->cpc_regs[DESIRED_PERF]) &&
+	if (!cpc_is_writable(&cpc_ptr->cpc_regs[DESIRED_PERF]) &&
 	    (!osc_sb_cppc2_support_acked ||
-	     !CPC_SUPPORTED(&cpc_ptr->cpc_regs[AUTO_SEL_ENABLE])))
-		pr_warn("Desired perf. register is mandatory if CPPC v2 is not supported "
-			"or autonomous selection is disabled\n");
+	     cpc_ptr->cpc_regs[AUTO_SEL_ENABLE].type != ACPI_TYPE_INTEGER ||
+	     cpc_ptr->cpc_regs[AUTO_SEL_ENABLE].cpc_entry.int_value != 1)) {
+		pr_debug("CPU:%d lacks a writable Desired Performance register\n",
+			 pr->id);
+		ret = -EINVAL;
+		goto out_free;
+	}
 
 	/*
 	 * Initialize the remaining cpc_regs as unsupported.
@@ -1037,6 +1132,8 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 	kfree(cpc_ptr);
 
 out_buf_free:
+	if (cpc_present)
+		pr_err("CPU%d: failed to initialize _CPC: %d\n", pr->id, ret);
 	kfree(output.pointer);
 	return ret;
 }
@@ -1217,11 +1314,18 @@ static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
 	u64 prev_val;
 	void __iomem *vaddr = NULL;
 	int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
-	struct cpc_reg *reg = &reg_res->cpc_entry.reg;
+	struct cpc_reg *reg;
 	struct cpc_desc *cpc_desc;
 	unsigned long flags;
 	bool locked = false;
 
+	if (reg_res->type != ACPI_TYPE_BUFFER)
+		return -EOPNOTSUPP;
+
+	reg = &reg_res->cpc_entry.reg;
+	if (IS_NULL_REG(reg))
+		return -EOPNOTSUPP;
+
 	size = GET_BIT_WIDTH(reg);
 
 	if (IS_ENABLED(CONFIG_HAS_IOPORT) &&
@@ -1364,7 +1468,9 @@ static int cppc_get_reg_val(int cpu, enum cppc_regs reg_idx, u64 *val)
 
 	reg = &cpc_desc->cpc_regs[reg_idx];
 
-	if ((reg->type == ACPI_TYPE_INTEGER && IS_OPTIONAL_CPC_REG(reg_idx) &&
+	/* Desired may be absent for immutable autonomous selection. */
+	if ((reg->type == ACPI_TYPE_INTEGER &&
+	     (IS_OPTIONAL_CPC_REG(reg_idx) || reg_idx == DESIRED_PERF) &&
 	     !reg->cpc_entry.int_value) || (reg->type != ACPI_TYPE_INTEGER &&
 	     IS_NULL_REG(&reg->cpc_entry.reg))) {
 		pr_debug("CPC register is not supported\n");
@@ -1415,7 +1521,7 @@ static int cppc_set_reg_val(int cpu, enum cppc_regs reg_idx, u64 val)
 	reg = &cpc_desc->cpc_regs[reg_idx];
 
 	/* if a register is writeable, it must be a buffer and not null */
-	if ((reg->type != ACPI_TYPE_BUFFER) || IS_NULL_REG(&reg->cpc_entry.reg)) {
+	if (!cpc_is_writable(reg)) {
 		pr_debug("CPC register is not supported\n");
 		return -EOPNOTSUPP;
 	}
@@ -1505,7 +1611,7 @@ int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
 	struct cpc_register_resource *highest_reg, *lowest_reg,
 		*lowest_non_linear_reg, *nominal_reg, *reference_reg,
 		*guaranteed_reg, *low_freq_reg = NULL, *nom_freq_reg = NULL;
-	u64 high, low, guaranteed, nom, ref, min_nonlinear,
+	u64 high, low, guaranteed = 0, nom, ref, min_nonlinear,
 	    low_f = 0, nom_f = 0;
 	int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
 	struct cppc_pcc_data *pcc_ss_data = NULL;
@@ -1588,7 +1694,12 @@ int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
 		goto out_err;
 	perf_caps->lowest_nonlinear_perf = min_nonlinear;
 
-	if (!high || !low || !nom || !ref || !min_nonlinear) {
+	if (!high || !nom || !ref || !min_nonlinear ||
+	    high > U32_MAX || low > U32_MAX || guaranteed > U32_MAX ||
+	    nom > U32_MAX || ref > U32_MAX || min_nonlinear > U32_MAX ||
+	    high < nom || nom < min_nonlinear || min_nonlinear < low ||
+	    (CPC_SUPPORTED(guaranteed_reg) &&
+	     (guaranteed < low || guaranteed > nom))) {
 		ret = -EFAULT;
 		goto out_err;
 	}
@@ -1605,6 +1716,19 @@ int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
 		if (ret)
 			goto out_err;
 	}
+	/*
+	 * Require ordered anchors and a nonzero slope when frequencies differ.
+	 * A zero Lowest Performance needs that affine mapping to produce a
+	 * nonzero physical minimum frequency.
+	 */
+	if (low_f > U32_MAX || nom_f > U32_MAX ||
+	    (!low && (!low_f || !nom_f || low_f == nom_f)) ||
+	    (low_f && nom_f &&
+	     (nom_f < low_f || nom < low ||
+	      (nom_f != low_f && nom == low)))) {
+		ret = -EFAULT;
+		goto out_err;
+	}
 
 	perf_caps->lowest_freq = low_f;
 	perf_caps->nominal_freq = nom_f;
@@ -1779,6 +1903,9 @@ int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable)
 
 	auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
 	epp_set_reg = &cpc_desc->cpc_regs[ENERGY_PERF];
+	if (!enable && auto_sel_reg->type == ACPI_TYPE_INTEGER &&
+	    auto_sel_reg->cpc_entry.int_value == 1)
+		return -EOPNOTSUPP;
 
 	epp_ffh_sysmem = CPC_SUPPORTED(epp_set_reg) &&
 		(CPC_IN_FFH(epp_set_reg) || CPC_IN_SYSTEM_MEMORY(epp_set_reg));
@@ -1791,13 +1918,13 @@ int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable)
 			return -ENODEV;
 		}
 
-		if (CPC_SUPPORTED(auto_sel_reg)) {
+		if (cpc_is_writable(auto_sel_reg)) {
 			ret = cpc_write(cpu, auto_sel_reg, enable);
 			if (ret)
 				return ret;
 		}
 
-		if (CPC_SUPPORTED(epp_set_reg)) {
+		if (cpc_is_writable(epp_set_reg)) {
 			ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf);
 			if (ret)
 				return ret;
@@ -1996,6 +2123,8 @@ int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
 	max_perf_reg = &cpc_desc->cpc_regs[MAX_PERF];
 	energy_perf_reg = &cpc_desc->cpc_regs[ENERGY_PERF];
 	auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
+	perf_ctrls->max_perf_valid = false;
+	perf_ctrls->min_perf_valid = false;
 
 	/* Are any of the regs PCC ?*/
 	if (CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg) ||
@@ -2020,6 +2149,7 @@ int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
 		ret = cpc_read(cpu, max_perf_reg, &max);
 		if (ret)
 			goto out_err;
+		perf_ctrls->max_perf_valid = true;
 	}
 	perf_ctrls->max_perf = max;
 
@@ -2027,6 +2157,7 @@ int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
 		ret = cpc_read(cpu, min_perf_reg, &min);
 		if (ret)
 			goto out_err;
+		perf_ctrls->min_perf_valid = true;
 	}
 	perf_ctrls->min_perf = min;
 
@@ -2113,14 +2244,11 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
 	if (CPC_SUPPORTED(desired_reg))
 		cpc_write(cpu, desired_reg, perf_ctrls->desired_perf);
 
-	/*
-	 * Only write if min_perf and max_perf not zero. Some drivers pass zero
-	 * value to min and max perf, but they don't mean to set the zero value,
-	 * they just don't want to write to those registers.
-	 */
-	if (perf_ctrls->min_perf && CPC_SUPPORTED(min_perf_reg))
+	if (CPC_SUPPORTED(min_perf_reg) &&
+	    (perf_ctrls->min_perf || perf_ctrls->min_perf_valid))
 		cpc_write(cpu, min_perf_reg, perf_ctrls->min_perf);
-	if (perf_ctrls->max_perf && CPC_SUPPORTED(max_perf_reg))
+	if (CPC_SUPPORTED(max_perf_reg) &&
+	    (perf_ctrls->max_perf || perf_ctrls->max_perf_valid))
 		cpc_write(cpu, max_perf_reg, perf_ctrls->max_perf);
 
 	if (regs_in_pcc)
diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
index d4ff8b228f86..63f0ca5f19b3 100644
--- a/drivers/cpufreq/amd-pstate.c
+++ b/drivers/cpufreq/amd-pstate.c
@@ -544,7 +544,13 @@ static int shmem_update_perf(struct cpufreq_policy *policy, u8 min_perf,
 			     u8 des_perf, u8 max_perf, u8 epp, bool fast_switch)
 {
 	struct amd_cpudata *cpudata = policy->driver_data;
-	struct cppc_perf_ctrls perf_ctrls;
+	struct cppc_perf_ctrls perf_ctrls = {
+		.max_perf = max_perf,
+		.min_perf = min_perf,
+		.desired_perf = des_perf,
+		.max_perf_valid = true,
+		.min_perf_valid = true,
+	};
 	u64 value, prev;
 	int ret;
 
@@ -577,10 +583,6 @@ static int shmem_update_perf(struct cpufreq_policy *policy, u8 min_perf,
 	if (value == prev)
 		return 0;
 
-	perf_ctrls.max_perf = max_perf;
-	perf_ctrls.min_perf = min_perf;
-	perf_ctrls.desired_perf = des_perf;
-
 	ret = cppc_set_perf(cpudata->cpu, &perf_ctrls);
 	if (ret)
 		return ret;
diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h
index 94a6277edab2..5dcbe65c5ddc 100644
--- a/include/acpi/cppc_acpi.h
+++ b/include/acpi/cppc_acpi.h
@@ -141,6 +141,8 @@ struct cppc_perf_ctrls {
 	u32 desired_perf;
 	u32 energy_perf;
 	bool auto_sel;
+	bool max_perf_valid;
+	bool min_perf_valid;
 };
 
 struct cppc_perf_fb_ctrs {
-- 
2.34.1

[PATCH v6 03/15] ACPI: CPPC: Propagate performance-control write errors

[Christian Loehle]

cppc_set_perf() can skip malformed controls, discard cpc_write() failures,
and report success without programming the requested performance tuple.

Return every control-write error to the caller and honor the explicit
Minimum and Maximum Performance validity flags, so an explicit zero remains
distinct from a legacy omitted bound. Validate every requested PCC field
before changing either a direct control or the shared payload; after that
check, PCC staging cannot fail partway through a tuple.

Keep the existing shared-lock batching for layouts whose writable
performance controls all use PCC. Multiple Phase-I callers may set the
pending flag to true while holding the shared side of pcc_lock. Mark that
intentional same-value store with WRITE_ONCE(); transitions back to false
remain protected by the exclusive side.

A layout which mixes PCC with directly accessed controls needs stronger
ordering. A fallible direct write cannot safely run alongside another CPU's
staged PCC tuple: if it fails after changing a direct register, neither
submitting nor discarding the shared batch can preserve the other request.
Serialize the complete mixed transaction with the exclusive PCC lock.
Drain an older pending batch before changing a direct control. Check the
preceding PCC command for completion, then program the direct and PCC
portions and submit the new command synchronously. Use the mixed-layout
synchronization even when the current request omits its PCC-backed bounds,
so a direct-only update cannot race a prior PCC command.

Purely direct layouts continue to avoid the PCC lock. Cross-address-space
updates cannot be atomic, but a known write failure no longer submits or
cancels a tuple staged by another caller.

Fixes: 337aadff8e45 ("ACPI: Introduce CPU performance controls using CPPC")
Reported-by: Sashiko <sashiko-bot@kernel.org>
Link: https://sashiko.dev/#/patchset/20260807111303.1062391-1-christian.loehle%40arm.com
Signed-off-by: Christian Loehle <christian.loehle@arm.com>
---
 drivers/acpi/cppc_acpi.c | 264 ++++++++++++++++++++++++++++++---------
 1 file changed, 203 insertions(+), 61 deletions(-)

diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
index 6f3ffa4a1845..925be772041c 100644
--- a/drivers/acpi/cppc_acpi.c
+++ b/drivers/acpi/cppc_acpi.c
@@ -233,6 +233,19 @@ show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time);
 			     (reg)->space_id != ACPI_ADR_SPACE_PLATFORM_COMM) ? \
 			    (8 << ((reg)->access_width - 1)) : (reg)->bit_width)
 
+static bool cpc_pcc_write_supported(const struct cpc_register_resource *reg)
+{
+	switch (GET_BIT_WIDTH(&reg->cpc_entry.reg)) {
+	case 8:
+	case 16:
+	case 32:
+	case 64:
+		return true;
+	default:
+		return false;
+	}
+}
+
 /* Shift and apply the mask for CPC reads/writes */
 #define MASK_VAL_READ(reg, val) (((val) >> (reg)->bit_offset) &				\
 					GENMASK(((reg)->bit_width) - 1, 0))
@@ -373,13 +386,34 @@ static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit)
 	return ret;
 }
 
+static void cppc_complete_pcc_write(struct cppc_pcc_data *pcc_ss_data,
+				    int ret)
+{
+	int i;
+
+	if (unlikely(ret)) {
+		for_each_possible_cpu(i) {
+			struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i);
+
+			if (!desc)
+				continue;
+
+			if (desc->write_cmd_id == pcc_ss_data->pcc_write_cnt)
+				desc->write_cmd_status = ret;
+		}
+	}
+
+	pcc_ss_data->pcc_write_cnt++;
+	wake_up_all(&pcc_ss_data->pcc_write_wait_q);
+}
+
 /*
  * This function transfers the ownership of the PCC to the platform
  * So it must be called while holding write_lock(pcc_lock)
  */
 static int send_pcc_cmd(int pcc_ss_id, u16 cmd)
 {
-	int ret = -EIO, i;
+	int ret = -EIO;
 	struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
 	struct acpi_pcct_shared_memory __iomem *generic_comm_base =
 					pcc_ss_data->pcc_channel->shmem;
@@ -471,21 +505,8 @@ static int send_pcc_cmd(int pcc_ss_id, u16 cmd)
 		mbox_client_txdone(pcc_ss_data->pcc_channel->mchan, ret);
 
 end:
-	if (cmd == CMD_WRITE) {
-		if (unlikely(ret)) {
-			for_each_possible_cpu(i) {
-				struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i);
-
-				if (!desc)
-					continue;
-
-				if (desc->write_cmd_id == pcc_ss_data->pcc_write_cnt)
-					desc->write_cmd_status = ret;
-			}
-		}
-		pcc_ss_data->pcc_write_cnt++;
-		wake_up_all(&pcc_ss_data->pcc_write_wait_q);
-	}
+	if (cmd == CMD_WRITE)
+		cppc_complete_pcc_write(pcc_ss_data, ret);
 
 	return ret;
 }
@@ -2197,7 +2218,9 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
 	struct cpc_register_resource *desired_reg, *min_perf_reg, *max_perf_reg;
 	int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
 	struct cppc_pcc_data *pcc_ss_data = NULL;
-	bool regs_in_pcc;
+	bool desired_update, min_update, max_update;
+	bool desired_pcc, min_pcc, max_pcc, pcc_update;
+	bool pcc_layout, direct_layout, mixed_layout;
 	int ret = 0;
 
 	if (!cpc_desc) {
@@ -2208,51 +2231,168 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
 	desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
 	min_perf_reg = &cpc_desc->cpc_regs[MIN_PERF];
 	max_perf_reg = &cpc_desc->cpc_regs[MAX_PERF];
-	regs_in_pcc = CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) ||
-		      CPC_IN_PCC(max_perf_reg);
+	desired_update = cpc_is_writable(desired_reg);
+	min_update = cpc_is_writable(min_perf_reg) &&
+		     (perf_ctrls->min_perf || perf_ctrls->min_perf_valid);
+	max_update = cpc_is_writable(max_perf_reg) &&
+		     (perf_ctrls->max_perf || perf_ctrls->max_perf_valid);
+	desired_pcc = desired_update && CPC_IN_PCC(desired_reg);
+	min_pcc = min_update && CPC_IN_PCC(min_perf_reg);
+	max_pcc = max_update && CPC_IN_PCC(max_perf_reg);
+	pcc_update = desired_pcc || min_pcc || max_pcc;
+	pcc_layout = (cpc_is_writable(desired_reg) && CPC_IN_PCC(desired_reg)) ||
+		     (cpc_is_writable(min_perf_reg) && CPC_IN_PCC(min_perf_reg)) ||
+		     (cpc_is_writable(max_perf_reg) && CPC_IN_PCC(max_perf_reg));
+	direct_layout = (cpc_is_writable(desired_reg) &&
+			 !CPC_IN_PCC(desired_reg)) ||
+			(cpc_is_writable(min_perf_reg) &&
+			 !CPC_IN_PCC(min_perf_reg)) ||
+			(cpc_is_writable(max_perf_reg) &&
+			 !CPC_IN_PCC(max_perf_reg));
+	mixed_layout = pcc_layout && direct_layout;
+
+	/* Do not modify any control if a requested PCC field cannot be staged. */
+	if ((desired_pcc && !cpc_pcc_write_supported(desired_reg)) ||
+	    (min_pcc && !cpc_pcc_write_supported(min_perf_reg)) ||
+	    (max_pcc && !cpc_pcc_write_supported(max_perf_reg)))
+		return -EFAULT;
 
-	/*
-	 * This is Phase-I where we want to write to CPC registers
-	 * -> We want all CPUs to be able to execute this phase in parallel
-	 *
-	 * Since read_lock can be acquired by multiple CPUs simultaneously we
-	 * achieve that goal here
-	 */
-	if (regs_in_pcc) {
+	if (mixed_layout || pcc_update) {
 		if (pcc_ss_id < 0) {
 			pr_debug("Invalid pcc_ss_id\n");
 			return -ENODEV;
 		}
 		pcc_ss_data = pcc_data[pcc_ss_id];
-		down_read(&pcc_ss_data->pcc_lock); /* BEGIN Phase-I */
+		if (!pcc_ss_data)
+			return -ENODEV;
+	}
+
+	/*
+	 * A mixed layout cannot batch fallible direct writes safely: another
+	 * CPU's staged PCC values may no longer match if a direct write fails.
+	 * Serialize the complete mixed transaction and drain an older batch
+	 * before changing a direct control.
+	 */
+	if (mixed_layout) {
+		down_write(&pcc_ss_data->pcc_lock);
+		if (pcc_ss_data->pending_pcc_write_cmd) {
+			ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
+			if (ret)
+				goto out_mixed_unlock;
+		}
+
 		if (pcc_ss_data->platform_owns_pcc) {
 			ret = check_pcc_chan(pcc_ss_id, false);
-			if (ret) {
-				up_read(&pcc_ss_data->pcc_lock);
+			if (ret)
+				goto out_mixed_unlock;
+		}
+
+		if (desired_update && !desired_pcc) {
+			ret = cpc_write(cpu, desired_reg,
+					perf_ctrls->desired_perf);
+			if (ret)
+				goto out_mixed_unlock;
+		}
+		if (min_update && !min_pcc) {
+			ret = cpc_write(cpu, min_perf_reg,
+					perf_ctrls->min_perf);
+			if (ret)
+				goto out_mixed_unlock;
+		}
+		if (max_update && !max_pcc) {
+			ret = cpc_write(cpu, max_perf_reg,
+					perf_ctrls->max_perf);
+			if (ret)
+				goto out_mixed_unlock;
+		}
+
+		if (desired_pcc) {
+			ret = cpc_write(cpu, desired_reg,
+					perf_ctrls->desired_perf);
+			if (ret)
+				goto out_mixed_unlock;
+		}
+		if (min_pcc) {
+			ret = cpc_write(cpu, min_perf_reg,
+					perf_ctrls->min_perf);
+			if (ret)
+				goto out_mixed_unlock;
+		}
+		if (max_pcc) {
+			ret = cpc_write(cpu, max_perf_reg,
+					perf_ctrls->max_perf);
+			if (ret)
+				goto out_mixed_unlock;
+		}
+
+		if (pcc_update) {
+			WRITE_ONCE(pcc_ss_data->pending_pcc_write_cmd, true);
+			cpc_desc->write_cmd_id = pcc_ss_data->pcc_write_cnt;
+			cpc_desc->write_cmd_status = 0;
+			ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
+		}
+
+out_mixed_unlock:
+		up_write(&pcc_ss_data->pcc_lock);
+		return ret;
+	}
+
+	/* A non-PCC layout has no shared payload to coordinate. */
+	if (!pcc_update) {
+		if (desired_update) {
+			ret = cpc_write(cpu, desired_reg,
+					perf_ctrls->desired_perf);
+			if (ret)
 				return ret;
-			}
 		}
-		/*
-		 * Update the pending_write to make sure a PCC CMD_READ will not
-		 * arrive and steal the channel during the switch to write lock
-		 */
-		pcc_ss_data->pending_pcc_write_cmd = true;
-		cpc_desc->write_cmd_id = pcc_ss_data->pcc_write_cnt;
-		cpc_desc->write_cmd_status = 0;
+		if (min_update) {
+			ret = cpc_write(cpu, min_perf_reg,
+					perf_ctrls->min_perf);
+			if (ret)
+				return ret;
+		}
+		if (max_update)
+			ret = cpc_write(cpu, max_perf_reg,
+					perf_ctrls->max_perf);
+		return ret;
 	}
 
-	if (CPC_SUPPORTED(desired_reg))
-		cpc_write(cpu, desired_reg, perf_ctrls->desired_perf);
+	down_read(&pcc_ss_data->pcc_lock); /* BEGIN Phase-I */
+	if (pcc_ss_data->platform_owns_pcc) {
+		ret = check_pcc_chan(pcc_ss_id, false);
+		if (ret)
+			goto out_pcc_read_unlock;
+	}
 
-	if (CPC_SUPPORTED(min_perf_reg) &&
-	    (perf_ctrls->min_perf || perf_ctrls->min_perf_valid))
-		cpc_write(cpu, min_perf_reg, perf_ctrls->min_perf);
-	if (CPC_SUPPORTED(max_perf_reg) &&
-	    (perf_ctrls->max_perf || perf_ctrls->max_perf_valid))
-		cpc_write(cpu, max_perf_reg, perf_ctrls->max_perf);
+	/*
+	 * This is Phase-I where we want to write to CPC registers
+	 * -> We want all CPUs to be able to execute this phase in parallel
+	 *
+	 * Since read_lock can be acquired by multiple CPUs simultaneously we
+	 * achieve that goal here.
+	 */
+	if (desired_pcc) {
+		ret = cpc_write(cpu, desired_reg, perf_ctrls->desired_perf);
+		if (ret)
+			goto out_pcc_read_unlock;
+	}
 
-	if (regs_in_pcc)
-		up_read(&pcc_ss_data->pcc_lock);	/* END Phase-I */
+	if (min_pcc) {
+		ret = cpc_write(cpu, min_perf_reg, perf_ctrls->min_perf);
+		if (ret)
+			goto out_pcc_read_unlock;
+	}
+	if (max_pcc) {
+		ret = cpc_write(cpu, max_perf_reg, perf_ctrls->max_perf);
+		if (ret)
+			goto out_pcc_read_unlock;
+	}
+
+	/* Block a PCC read until the staged payload has been submitted. */
+	WRITE_ONCE(pcc_ss_data->pending_pcc_write_cmd, true);
+	cpc_desc->write_cmd_id = pcc_ss_data->pcc_write_cnt;
+	cpc_desc->write_cmd_status = 0;
+	up_read(&pcc_ss_data->pcc_lock);	/* END Phase-I */
 	/*
 	 * This is Phase-II where we transfer the ownership of PCC to Platform
 	 *
@@ -2299,20 +2439,22 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
 	 * case during a CMD_READ and if there are pending writes it delivers
 	 * the write command before servicing the read command
 	 */
-	if (regs_in_pcc) {
-		if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */
-			/* Update only if there are pending write commands */
-			if (pcc_ss_data->pending_pcc_write_cmd)
-				send_pcc_cmd(pcc_ss_id, CMD_WRITE);
-			up_write(&pcc_ss_data->pcc_lock);	/* END Phase-II */
-		} else
-			/* Wait until pcc_write_cnt is updated by send_pcc_cmd */
-			wait_event(pcc_ss_data->pcc_write_wait_q,
-				   cpc_desc->write_cmd_id != pcc_ss_data->pcc_write_cnt);
-
-		/* send_pcc_cmd updates the status in case of failure */
-		ret = cpc_desc->write_cmd_status;
+	if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */
+		/* Update only if there are pending write commands */
+		if (pcc_ss_data->pending_pcc_write_cmd)
+			send_pcc_cmd(pcc_ss_id, CMD_WRITE);
+		up_write(&pcc_ss_data->pcc_lock);	/* END Phase-II */
+	} else {
+		/* Wait until pcc_write_cnt is updated by send_pcc_cmd */
+		wait_event(pcc_ss_data->pcc_write_wait_q,
+			   cpc_desc->write_cmd_id != pcc_ss_data->pcc_write_cnt);
 	}
+
+	/* send_pcc_cmd updates the status in case of failure */
+	return cpc_desc->write_cmd_status;
+
+out_pcc_read_unlock:
+	up_read(&pcc_ss_data->pcc_lock);
 	return ret;
 }
 EXPORT_SYMBOL_GPL(cppc_set_perf);
-- 
2.34.1

[PATCH v6 04/15] ACPI: CPPC: Use 64-bit masks for register fields

[Christian Loehle]

MASK_VAL_READ() and MASK_VAL_WRITE() operate on u64 values but construct
their masks with GENMASK(), whose type is unsigned long. On 32-bit kernels
a field wider than 32 bits therefore produces an invalid shift or loses
its upper bits.

The Generic Address Structure permits QWord access units and the CPPC
accessors implement 64-bit MMIO reads and writes. Use GENMASK_ULL() in both
directions so the mask matches the value and supported access width on
every architecture.

Fixes: 60949b7b8054 ("ACPI: CPPC: Fix MASK_VAL() usage")
Reported-by: Sashiko <sashiko-bot@kernel.org>
Link: https://sashiko.dev/#/patchset/20260724134251.1632824-1-christian.loehle%40arm.com
Signed-off-by: Christian Loehle <christian.loehle@arm.com>
---
 drivers/acpi/cppc_acpi.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
index 925be772041c..9ddcce7dc1a9 100644
--- a/drivers/acpi/cppc_acpi.c
+++ b/drivers/acpi/cppc_acpi.c
@@ -248,10 +248,10 @@ static bool cpc_pcc_write_supported(const struct cpc_register_resource *reg)
 
 /* Shift and apply the mask for CPC reads/writes */
 #define MASK_VAL_READ(reg, val) (((val) >> (reg)->bit_offset) &				\
-					GENMASK(((reg)->bit_width) - 1, 0))
+					GENMASK_ULL(((reg)->bit_width) - 1, 0))
 #define MASK_VAL_WRITE(reg, prev_val, val)						\
-	((((val) & GENMASK(((reg)->bit_width) - 1, 0)) << (reg)->bit_offset) |		\
-	((prev_val) & ~(GENMASK(((reg)->bit_width) - 1, 0) << (reg)->bit_offset)))	\
+	((((val) & GENMASK_ULL(((reg)->bit_width) - 1, 0)) << (reg)->bit_offset) |	\
+	((prev_val) & ~(GENMASK_ULL(((reg)->bit_width) - 1, 0) << (reg)->bit_offset))) \
 
 static u64 cpc_sysmem_access_size(const struct cpc_register_resource *reg)
 {
-- 
2.34.1

[PATCH v6 05/15] ACPI: CPPC: Serialize PCC single-register payload updates

[Christian Loehle]

The PCC doorbell protocol requires OSPM to confirm ownership of the shared
subspace before placing a command and its payload there.
cppc_set_reg_val_in_pcc() instead modifies the payload before taking
pcc_lock.

A concurrent command can consequently overwrite or consume the staged
value, and OSPM can write the shared region while the platform still owns
it.

Take the PCC write lock first, wait for the previous command to complete,
and keep the lock held while staging the value and submitting CMD_WRITE.
This follows the ownership sequence in ACPI 6.5 Section 14.5 and the
existing contract documented by send_pcc_cmd().

If ownership acquisition or staging fails, abort any older performance
batch before dropping the exclusive lock. This advances its generation and
wakes cppc_set_perf() callers which otherwise wait indefinitely for a
command this path did not submit.

Fixes: e05c75072c2e ("ACPI: CPPC: Add cppc_set_reg_val()")
Reported-by: Sashiko <sashiko-bot@kernel.org>
Link: https://sashiko.dev/#/patchset/20260724134251.1632824-1-christian.loehle%40arm.com
Link: https://sashiko.dev/#/patchset/20260807111303.1062391-1-christian.loehle%40arm.com
Signed-off-by: Christian Loehle <christian.loehle@arm.com>
---
 drivers/acpi/cppc_acpi.c | 32 +++++++++++++++++++++++++++-----
 1 file changed, 27 insertions(+), 5 deletions(-)

diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
index 9ddcce7dc1a9..085e775b3637 100644
--- a/drivers/acpi/cppc_acpi.c
+++ b/drivers/acpi/cppc_acpi.c
@@ -407,6 +407,17 @@ static void cppc_complete_pcc_write(struct cppc_pcc_data *pcc_ss_data,
 	wake_up_all(&pcc_ss_data->pcc_write_wait_q);
 }
 
+/* The caller must hold pcc_lock for write. */
+static void cppc_abort_pending_pcc_write(struct cppc_pcc_data *pcc_ss_data,
+					 int ret)
+{
+	if (!pcc_ss_data->pending_pcc_write_cmd)
+		return;
+
+	pcc_ss_data->pending_pcc_write_cmd = false;
+	cppc_complete_pcc_write(pcc_ss_data, ret);
+}
+
 /*
  * This function transfers the ownership of the PCC to the platform
  * So it must be called while holding write_lock(pcc_lock)
@@ -1507,7 +1518,7 @@ static int cppc_get_reg_val(int cpu, enum cppc_regs reg_idx, u64 *val)
 static int cppc_set_reg_val_in_pcc(int cpu, struct cpc_register_resource *reg, u64 val)
 {
 	int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
-	struct cppc_pcc_data *pcc_ss_data = NULL;
+	struct cppc_pcc_data *pcc_ss_data;
 	int ret;
 
 	if (pcc_ss_id < 0) {
@@ -1515,15 +1526,26 @@ static int cppc_set_reg_val_in_pcc(int cpu, struct cpc_register_resource *reg, u
 		return -ENODEV;
 	}
 
-	ret = cpc_write(cpu, reg, val);
-	if (ret)
-		return ret;
-
 	pcc_ss_data = pcc_data[pcc_ss_id];
+	if (!pcc_ss_data)
+		return -ENODEV;
 
 	down_write(&pcc_ss_data->pcc_lock);
+
+	ret = check_pcc_chan(pcc_ss_id, false);
+	if (ret)
+		goto out;
+
+	ret = cpc_write(cpu, reg, val);
+	if (ret)
+		goto out;
+
 	/* after writing CPC, transfer the ownership of PCC to platform */
 	ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
+
+out:
+	if (ret)
+		cppc_abort_pending_pcc_write(pcc_ss_data, ret);
 	up_write(&pcc_ss_data->pcc_lock);
 
 	return ret;
-- 
2.34.1

[PATCH v6 06/15] ACPI: CPPC: Serialize PCC EPP payload updates

[Christian Loehle]

cppc_set_epp_perf() stages Autonomous Selection and Energy Performance
Preference in the PCC shared region before taking pcc_lock. The platform
may still own the subspace, or a concurrent command may consume or
overwrite only part of the new payload.

Take the PCC write lock and wait for OSPM ownership before staging either
control. Keep the lock held until the complete payload has been submitted
with CMD_WRITE, so firmware cannot observe a mixed transaction.

For a mixed PCC/non-PCC description, complete every fallible non-PCC write
before staging PCC data. Cross-address-space updates cannot be atomic, but
a non-PCC failure can no longer leave an unsent value in shared memory for
a later PCC command to consume.

Classify every probe-validated writable control as either PCC or non-PCC.
This covers SystemIO along with FFH and SystemMemory and avoids repeating a
flexible-address-space _OSC decision that probe has already made.

If ownership acquisition or PCC staging fails, abort any older pending
performance batch before releasing the exclusive lock so its Phase-II
waiters receive the error instead of sleeping indefinitely.

This follows the PCC ownership sequence in ACPI 6.5 Section 14.5.

Fixes: 7bc1fcd39901 ("ACPI: CPPC: Add AMD pstate energy performance preference cppc control")
Reported-by: Sashiko <sashiko-bot@kernel.org>
Link: https://sashiko.dev/#/patchset/20260724134251.1632824-1-christian.loehle%40arm.com
Link: https://sashiko.dev/#/patchset/20260807111303.1062391-1-christian.loehle%40arm.com
Signed-off-by: Christian Loehle <christian.loehle@arm.com>
---
 drivers/acpi/cppc_acpi.c | 74 ++++++++++++++++++++++++----------------
 1 file changed, 44 insertions(+), 30 deletions(-)

diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
index 085e775b3637..f9866563466b 100644
--- a/drivers/acpi/cppc_acpi.c
+++ b/drivers/acpi/cppc_acpi.c
@@ -1935,8 +1935,10 @@ int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable)
 	struct cpc_register_resource *auto_sel_reg;
 	struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
 	struct cppc_pcc_data *pcc_ss_data = NULL;
-	bool autosel_ffh_sysmem;
-	bool epp_ffh_sysmem;
+	bool auto_sel_pcc;
+	bool auto_sel_non_pcc;
+	bool epp_pcc;
+	bool epp_non_pcc;
 	int ret;
 
 	if (!cpc_desc) {
@@ -1950,52 +1952,64 @@ int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable)
 	    auto_sel_reg->cpc_entry.int_value == 1)
 		return -EOPNOTSUPP;
 
-	epp_ffh_sysmem = CPC_SUPPORTED(epp_set_reg) &&
-		(CPC_IN_FFH(epp_set_reg) || CPC_IN_SYSTEM_MEMORY(epp_set_reg));
-	autosel_ffh_sysmem = CPC_SUPPORTED(auto_sel_reg) &&
-		(CPC_IN_FFH(auto_sel_reg) || CPC_IN_SYSTEM_MEMORY(auto_sel_reg));
+	auto_sel_pcc = cpc_is_writable(auto_sel_reg) &&
+		CPC_IN_PCC(auto_sel_reg);
+	epp_pcc = cpc_is_writable(epp_set_reg) && CPC_IN_PCC(epp_set_reg);
+	auto_sel_non_pcc = cpc_is_writable(auto_sel_reg) && !auto_sel_pcc;
+	epp_non_pcc = cpc_is_writable(epp_set_reg) && !epp_pcc;
 
-	if (CPC_IN_PCC(epp_set_reg) || CPC_IN_PCC(auto_sel_reg)) {
+	/* Complete fallible non-PCC writes before staging PCC data. */
+	if (auto_sel_non_pcc) {
+		ret = cpc_write(cpu, auto_sel_reg, enable);
+		if (ret)
+			return ret;
+	}
+	if (epp_non_pcc) {
+		ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf);
+		if (ret)
+			return ret;
+	}
+
+	if (epp_pcc || auto_sel_pcc) {
 		if (pcc_ss_id < 0) {
 			pr_debug("Invalid pcc_ss_id for CPU:%d\n", cpu);
 			return -ENODEV;
 		}
 
-		if (cpc_is_writable(auto_sel_reg)) {
+		pcc_ss_data = pcc_data[pcc_ss_id];
+		if (!pcc_ss_data)
+			return -ENODEV;
+
+		down_write(&pcc_ss_data->pcc_lock);
+
+		ret = check_pcc_chan(pcc_ss_id, false);
+		if (ret)
+			goto out_unlock;
+
+		if (auto_sel_pcc) {
 			ret = cpc_write(cpu, auto_sel_reg, enable);
 			if (ret)
-				return ret;
+				goto out_unlock;
 		}
 
-		if (cpc_is_writable(epp_set_reg)) {
+		if (epp_pcc) {
 			ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf);
 			if (ret)
-				return ret;
+				goto out_unlock;
 		}
 
-		pcc_ss_data = pcc_data[pcc_ss_id];
-
-		down_write(&pcc_ss_data->pcc_lock);
 		/* after writing CPC, transfer the ownership of PCC to platform */
 		ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
-		up_write(&pcc_ss_data->pcc_lock);
-	} else if (osc_cpc_flexible_adr_space_confirmed &&
-		   (epp_ffh_sysmem || autosel_ffh_sysmem)) {
-		if (autosel_ffh_sysmem) {
-			ret = cpc_write(cpu, auto_sel_reg, enable);
-			if (ret)
-				return ret;
-		}
 
-		if (epp_ffh_sysmem) {
-			ret = cpc_write(cpu, epp_set_reg,
-					perf_ctrls->energy_perf);
-			if (ret)
-				return ret;
-		}
+out_unlock:
+		if (ret)
+			cppc_abort_pending_pcc_write(pcc_ss_data, ret);
+		up_write(&pcc_ss_data->pcc_lock);
+	} else if (epp_non_pcc || auto_sel_non_pcc) {
+		ret = 0;
 	} else {
-		ret = -ENOTSUPP;
-		pr_debug("_CPC in PCC/FFH/SystemMemory are not supported\n");
+		ret = -EOPNOTSUPP;
+		pr_debug("No writable EPP controls for CPU:%d\n", cpu);
 	}
 
 	return ret;
-- 
2.34.1

[PATCH v6 07/15] ACPI: CPPC: Release CPC descriptors through kobject

[Christian Loehle]

The CPC descriptor embeds the kobject used for its sysfs directory, but
it has no release callback and processor exit frees the descriptor
immediately after kobject_put(). It also unmaps register resources and
releases PCC state before sysfs removal has drained active attribute
callbacks.

Provide a release callback which unmaps and frees the descriptor, and use
the same cleanup helper before kobject initialization. Once initialized,
let kobject_put() own descriptor cleanup so its error path cannot free the
object twice.

On processor exit, first unpublish the per-CPU descriptor and remove its
sysfs directory, then release PCC state and drop the kobject reference.
This keeps all resources valid while sysfs callbacks are active and also
works with delayed kobject release.

Fixes: 158c998ea44b ("ACPI / CPPC: add sysfs support to compute delivered performance")
Reported-by: Sashiko <sashiko-bot@kernel.org>
Link: https://sashiko.dev/#/patchset/20260724134251.1632824-1-christian.loehle%40arm.com
Signed-off-by: Christian Loehle <christian.loehle@arm.com>
---
 drivers/acpi/cppc_acpi.c | 49 ++++++++++++++++++++++++----------------
 1 file changed, 29 insertions(+), 20 deletions(-)

diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
index f9866563466b..37ff54a048c9 100644
--- a/drivers/acpi/cppc_acpi.c
+++ b/drivers/acpi/cppc_acpi.c
@@ -350,7 +350,27 @@ static struct attribute *cppc_attrs[] = {
 };
 ATTRIBUTE_GROUPS(cppc);
 
+static void cppc_free_desc(struct cpc_desc *cpc_ptr)
+{
+	unsigned int i;
+
+	for (i = 2; i < cpc_ptr->num_entries; i++) {
+		void __iomem *addr = cpc_ptr->cpc_regs[i - 2].sys_mem_vaddr;
+
+		if (addr)
+			iounmap(addr);
+	}
+
+	kfree(cpc_ptr);
+}
+
+static void cppc_kobj_release(struct kobject *kobj)
+{
+	cppc_free_desc(to_cpc_desc(kobj));
+}
+
 static const struct kobj_type cppc_ktype = {
+	.release = cppc_kobj_release,
 	.sysfs_ops = &kobj_sysfs_ops,
 	.default_groups = cppc_groups,
 };
@@ -1147,21 +1167,14 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 	if (ret) {
 		per_cpu(cpc_desc_ptr, pr->id) = NULL;
 		kobject_put(&cpc_ptr->kobj);
-		goto out_free;
+		goto out_buf_free;
 	}
 
 	kfree(output.pointer);
 	return 0;
 
 out_free:
-	/* Free all the mapped sys mem areas for this CPU */
-	for (i = 2; i < cpc_ptr->num_entries; i++) {
-		void __iomem *addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
-
-		if (addr)
-			iounmap(addr);
-	}
-	kfree(cpc_ptr);
+	cppc_free_desc(cpc_ptr);
 
 out_buf_free:
 	if (cpc_present)
@@ -1180,10 +1193,14 @@ EXPORT_SYMBOL_GPL(acpi_cppc_processor_probe);
 void acpi_cppc_processor_exit(struct acpi_processor *pr)
 {
 	struct cpc_desc *cpc_ptr;
-	unsigned int i;
-	void __iomem *addr;
 	int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, pr->id);
 
+	cpc_ptr = per_cpu(cpc_desc_ptr, pr->id);
+	if (cpc_ptr) {
+		per_cpu(cpc_desc_ptr, pr->id) = NULL;
+		kobject_del(&cpc_ptr->kobj);
+	}
+
 	if (pcc_ss_id >= 0 && pcc_data[pcc_ss_id]) {
 		if (pcc_data[pcc_ss_id]->pcc_channel_acquired) {
 			pcc_data[pcc_ss_id]->refcount--;
@@ -1194,20 +1211,12 @@ void acpi_cppc_processor_exit(struct acpi_processor *pr)
 			}
 		}
 	}
+	per_cpu(cpu_pcc_subspace_idx, pr->id) = -1;
 
-	cpc_ptr = per_cpu(cpc_desc_ptr, pr->id);
 	if (!cpc_ptr)
 		return;
 
-	/* Free all the mapped sys mem areas for this CPU */
-	for (i = 2; i < cpc_ptr->num_entries; i++) {
-		addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
-		if (addr)
-			iounmap(addr);
-	}
-
 	kobject_put(&cpc_ptr->kobj);
-	kfree(cpc_ptr);
 }
 EXPORT_SYMBOL_GPL(acpi_cppc_processor_exit);
 
-- 
2.34.1

[PATCH v6 08/15] ACPI: CPPC: Release PCC data after probe failures

[Christian Loehle]

pcc_data_alloc() takes a per-processor reference while parsing the first
PCC register. Every later probe failure currently frees the CPC descriptor
without dropping that reference. Depending on where probe fails, this
leaks an unacquired PCC object, an acquired mailbox channel, or an extra
reference to a shared channel.

Factor the teardown into pcc_data_put() so it handles both acquired and
unacquired state, and invoke it on every failure after allocation.

Allocation, reference updates, channel setup, and teardown of a shared
subspace are also unsynchronized. Concurrent processor probe and removal
can lose a reference update, free a live object, or request and initialize
the same mailbox channel twice. Protect that lifecycle with a mutex and
publish pcc_channel_acquired only after its lock and wait queue have been
initialized.

Do not store the temporary pcc_data_alloc() result in the eventual probe
return value. A successful allocation must not make a later parsing failure
run cleanup and then return success.

A later processor-start step can fail after CPPC probe has published its
descriptor. Reuse that descriptor when processor start is retried instead
of resetting its PCC index and reparsing _CPC. This prevents the live
descriptor from becoming detached from its PCC reference.

The per-CPU PCC subspace index is zero-initialized. If probe returns before
assigning it, a later processor exit can consequently drop the reference
for subspace 0 even though this CPU never acquired one. Initialize the
index to -1 before any probe return and only release it from exit after a
CPC descriptor has been published.

Fixes: 85b1407bf6d2 ("ACPI / CPPC: Make CPPC ACPI driver aware of PCC subspace IDs")
Signed-off-by: Christian Loehle <christian.loehle@arm.com>
---
 drivers/acpi/cppc_acpi.c | 153 ++++++++++++++++++++++++++-------------
 1 file changed, 101 insertions(+), 52 deletions(-)

diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
index 37ff54a048c9..e8ffd5b7094d 100644
--- a/drivers/acpi/cppc_acpi.c
+++ b/drivers/acpi/cppc_acpi.c
@@ -36,6 +36,7 @@
 #include <linux/delay.h>
 #include <linux/iopoll.h>
 #include <linux/ktime.h>
+#include <linux/mutex.h>
 #include <linux/rwsem.h>
 #include <linux/wait.h>
 #include <linux/topology.h>
@@ -81,6 +82,7 @@ struct cppc_pcc_data {
 
 /* Array to represent the PCC channel per subspace ID */
 static struct cppc_pcc_data *pcc_data[MAX_PCC_SUBSPACES];
+static DEFINE_MUTEX(pcc_data_lock);
 /* The cpu_pcc_subspace_idx contains per CPU subspace ID */
 static DEFINE_PER_CPU(int, cpu_pcc_subspace_idx);
 
@@ -735,35 +737,51 @@ EXPORT_SYMBOL_GPL(acpi_get_psd_map);
 
 static int register_pcc_channel(int pcc_ss_idx)
 {
+	struct cppc_pcc_data *data;
 	struct pcc_mbox_chan *pcc_chan;
 	u64 usecs_lat;
+	int ret = 0;
 
-	if (pcc_ss_idx >= 0) {
-		pcc_chan = pcc_mbox_request_channel(&cppc_mbox_cl, pcc_ss_idx);
-
-		if (IS_ERR(pcc_chan)) {
-			pr_err("Failed to find PCC channel for subspace %d\n",
-			       pcc_ss_idx);
-			return -ENODEV;
-		}
+	if (pcc_ss_idx < 0 || pcc_ss_idx >= MAX_PCC_SUBSPACES)
+		return -EINVAL;
 
-		pcc_data[pcc_ss_idx]->pcc_channel = pcc_chan;
-		/*
-		 * cppc_ss->latency is just a Nominal value. In reality
-		 * the remote processor could be much slower to reply.
-		 * So add an arbitrary amount of wait on top of Nominal.
-		 */
-		usecs_lat = NUM_RETRIES * pcc_chan->latency;
-		pcc_data[pcc_ss_idx]->deadline_us = usecs_lat;
-		pcc_data[pcc_ss_idx]->pcc_mrtt = pcc_chan->min_turnaround_time;
-		pcc_data[pcc_ss_idx]->pcc_mpar = pcc_chan->max_access_rate;
-		pcc_data[pcc_ss_idx]->pcc_nominal = pcc_chan->latency;
+	mutex_lock(&pcc_data_lock);
+	data = pcc_data[pcc_ss_idx];
+	if (!data) {
+		ret = -ENODEV;
+		goto out_unlock;
+	}
+	if (data->pcc_channel_acquired)
+		goto out_unlock;
 
-		/* Set flag so that we don't come here for each CPU. */
-		pcc_data[pcc_ss_idx]->pcc_channel_acquired = true;
+	pcc_chan = pcc_mbox_request_channel(&cppc_mbox_cl, pcc_ss_idx);
+	if (IS_ERR(pcc_chan)) {
+		pr_err("Failed to find PCC channel for subspace %d\n",
+		       pcc_ss_idx);
+		ret = -ENODEV;
+		goto out_unlock;
 	}
 
-	return 0;
+	data->pcc_channel = pcc_chan;
+	/*
+	 * cppc_ss->latency is just a Nominal value. In reality
+	 * the remote processor could be much slower to reply.
+	 * So add an arbitrary amount of wait on top of Nominal.
+	 */
+	usecs_lat = NUM_RETRIES * pcc_chan->latency;
+	data->deadline_us = usecs_lat;
+	data->pcc_mrtt = pcc_chan->min_turnaround_time;
+	data->pcc_mpar = pcc_chan->max_access_rate;
+	data->pcc_nominal = pcc_chan->latency;
+	init_rwsem(&data->pcc_lock);
+	init_waitqueue_head(&data->pcc_write_wait_q);
+
+	/* Set flag so that we don't come here for each CPU. */
+	data->pcc_channel_acquired = true;
+
+out_unlock:
+	mutex_unlock(&pcc_data_lock);
+	return ret;
 }
 
 /**
@@ -805,19 +823,49 @@ bool __weak cpc_supported_by_cpu(void)
  */
 static int pcc_data_alloc(int pcc_ss_id)
 {
+	struct cppc_pcc_data *data;
+	int ret = 0;
+
 	if (pcc_ss_id < 0 || pcc_ss_id >= MAX_PCC_SUBSPACES)
 		return -EINVAL;
 
-	if (pcc_data[pcc_ss_id]) {
-		pcc_data[pcc_ss_id]->refcount++;
-	} else {
-		pcc_data[pcc_ss_id] = kzalloc_obj(struct cppc_pcc_data);
-		if (!pcc_data[pcc_ss_id])
-			return -ENOMEM;
-		pcc_data[pcc_ss_id]->refcount++;
+	mutex_lock(&pcc_data_lock);
+	data = pcc_data[pcc_ss_id];
+	if (!data) {
+		data = kzalloc_obj(struct cppc_pcc_data);
+		if (!data) {
+			ret = -ENOMEM;
+			goto out_unlock;
+		}
+		pcc_data[pcc_ss_id] = data;
 	}
+	data->refcount++;
 
-	return 0;
+out_unlock:
+	mutex_unlock(&pcc_data_lock);
+	return ret;
+}
+
+static void pcc_data_put(int pcc_ss_id)
+{
+	struct cppc_pcc_data *data;
+
+	if (pcc_ss_id < 0 || pcc_ss_id >= MAX_PCC_SUBSPACES)
+		return;
+
+	mutex_lock(&pcc_data_lock);
+	data = pcc_data[pcc_ss_id];
+	if (!data || --data->refcount)
+		goto out_unlock;
+
+	pcc_data[pcc_ss_id] = NULL;
+	if (data->pcc_channel_acquired)
+		pcc_mbox_free_channel(data->pcc_channel);
+
+	kfree(data);
+
+out_unlock:
+	mutex_unlock(&pcc_data_lock);
 }
 
 /*
@@ -865,11 +913,17 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 	acpi_handle handle = pr->handle;
 	unsigned int num_ent, i, cpc_rev;
 	int pcc_subspace_id = -1;
+	bool pcc_data_ref = false;
 	bool cpc_present = false;
 	acpi_status status;
 	int ret = -ENODATA;
 	int err;
 
+	if (per_cpu(cpc_desc_ptr, pr->id))
+		return 0;
+
+	per_cpu(cpu_pcc_subspace_idx, pr->id) = -1;
+
 	if (!osc_sb_cppc2_support_acked) {
 		pr_debug("CPPC v2 _OSC not acked\n");
 		if (!cpc_supported_by_cpu()) {
@@ -1008,6 +1062,7 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 						ret = err;
 						goto out_free;
 					}
+					pcc_data_ref = true;
 				} else if (pcc_subspace_id != gas_t->access_width) {
 					pr_debug("Mismatched PCC ids in _CPC for CPU:%d\n",
 						 pr->id);
@@ -1140,13 +1195,10 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 		goto out_free;
 
 	/* Register PCC channel once for all PCC subspace ID. */
-	if (pcc_subspace_id >= 0 && !pcc_data[pcc_subspace_id]->pcc_channel_acquired) {
+	if (pcc_subspace_id >= 0) {
 		ret = register_pcc_channel(pcc_subspace_id);
 		if (ret)
 			goto out_free;
-
-		init_rwsem(&pcc_data[pcc_subspace_id]->pcc_lock);
-		init_waitqueue_head(&pcc_data[pcc_subspace_id]->pcc_write_wait_q);
 	}
 
 	/* Everything looks okay */
@@ -1167,7 +1219,7 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 	if (ret) {
 		per_cpu(cpc_desc_ptr, pr->id) = NULL;
 		kobject_put(&cpc_ptr->kobj);
-		goto out_buf_free;
+		goto out_pcc_put;
 	}
 
 	kfree(output.pointer);
@@ -1176,6 +1228,11 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 out_free:
 	cppc_free_desc(cpc_ptr);
 
+out_pcc_put:
+	if (pcc_data_ref)
+		pcc_data_put(pcc_subspace_id);
+	per_cpu(cpu_pcc_subspace_idx, pr->id) = -1;
+
 out_buf_free:
 	if (cpc_present)
 		pr_err("CPU%d: failed to initialize _CPC: %d\n", pr->id, ret);
@@ -1193,28 +1250,20 @@ EXPORT_SYMBOL_GPL(acpi_cppc_processor_probe);
 void acpi_cppc_processor_exit(struct acpi_processor *pr)
 {
 	struct cpc_desc *cpc_ptr;
-	int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, pr->id);
+	int pcc_ss_id;
 
 	cpc_ptr = per_cpu(cpc_desc_ptr, pr->id);
-	if (cpc_ptr) {
-		per_cpu(cpc_desc_ptr, pr->id) = NULL;
-		kobject_del(&cpc_ptr->kobj);
+	if (!cpc_ptr) {
+		per_cpu(cpu_pcc_subspace_idx, pr->id) = -1;
+		return;
 	}
 
-	if (pcc_ss_id >= 0 && pcc_data[pcc_ss_id]) {
-		if (pcc_data[pcc_ss_id]->pcc_channel_acquired) {
-			pcc_data[pcc_ss_id]->refcount--;
-			if (!pcc_data[pcc_ss_id]->refcount) {
-				pcc_mbox_free_channel(pcc_data[pcc_ss_id]->pcc_channel);
-				kfree(pcc_data[pcc_ss_id]);
-				pcc_data[pcc_ss_id] = NULL;
-			}
-		}
-	}
-	per_cpu(cpu_pcc_subspace_idx, pr->id) = -1;
+	pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, pr->id);
+	per_cpu(cpc_desc_ptr, pr->id) = NULL;
+	kobject_del(&cpc_ptr->kobj);
 
-	if (!cpc_ptr)
-		return;
+	pcc_data_put(pcc_ss_id);
+	per_cpu(cpu_pcc_subspace_idx, pr->id) = -1;
 
 	kobject_put(&cpc_ptr->kobj);
 }
-- 
2.34.1

[PATCH v6 09/15] ACPI: CPPC: Reject unsafe cross-CPU SystemMemory RMW

[Christian Loehle]

A SystemMemory CPPC field narrower than its access unit needs a
read-modify-write operation. The existing per-CPC-descriptor lock
serializes such fields within one _CPC package, but not access units
described by different processors. Concurrent writers can therefore lose
updates.

The ACPI specification does not make _PSD a physical register-ownership
boundary. It can legally describe shared or packed registers across
processors and performance domains. Supporting every such layout would
require locks keyed by physical access unit.

Retain the deliberately cheaper per-descriptor locking model and enforce
its assumptions at probe instead. Reject overlapping access units from
different descriptors when both contain writable partial fields. Exempt
exact aliases when their complete access is one aligned native transaction.
Such non-identical layouts were never safely writable by Linux, so this
turns possible corruption into a probe error rather than removing support.

Within one descriptor, disjoint partial writable fields remain supported
and share its raw spinlock. Across descriptors, exact writable aliases
remain supported and lockless when the complete access is naturally aligned
and the architecture provides a native access of the declared width. Two
partial aliases update the same logical field, so their requests retain
last-writer-wins semantics. Require alignment even on x86 because an
unaligned instruction may not be one indivisible device transaction. Reject
64-bit writable aliases on 32-bit kernels because generic writeq() may use
two 32-bit stores and is not a portable atomicity guarantee. Read-only
64-bit aliases remain supported on every architecture.

Read-only overlaps also remain supported, as does a partial writable field
sharing an access unit with a read-only field. Reject overlapping logical
fields when both are writable. Reject any other field sharing a full-width
writable access unit. Also reject disjoint partial writers across
descriptors because their locks cannot serialize the shared access unit.

Validate the GAS geometry and require naturally aligned 8-, 16-, 32-, or
64-bit SystemMemory access units on architectures whose MMIO accessors
require it. Preserve unaligned SystemMemory layouts on x86, whose MMIO
accessors support them. Keep an interval tree solely for scalable
probe-time overlap validation; the full-width scheduler path does no lookup
and takes no lock.

Keep validation errors separate from the probe return value. A successful
SystemMemory geometry check must not overwrite the pending negative error,
because a later mapping or address-space failure still needs to make probe
fail.

Fixes: 60949b7b8054 ("ACPI: CPPC: Fix MASK_VAL() usage")
Reported-by: Sashiko <sashiko-bot@kernel.org>
Link: https://sashiko.dev/#/patchset/20260724134251.1632824-1-christian.loehle%40arm.com
Link: https://sashiko.dev/#/patchset/20260807111303.1062391-1-christian-loehle%40arm.com
Signed-off-by: Christian Loehle <christian.loehle@arm.com>
---
 drivers/acpi/cppc_acpi.c | 402 +++++++++++++++++++++++++++++++++++----
 include/acpi/cppc_acpi.h |   5 +-
 2 files changed, 370 insertions(+), 37 deletions(-)

diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
index e8ffd5b7094d..058f4c71d981 100644
--- a/drivers/acpi/cppc_acpi.c
+++ b/drivers/acpi/cppc_acpi.c
@@ -34,9 +34,12 @@
 #define pr_fmt(fmt)	"ACPI CPPC: " fmt
 
 #include <linux/delay.h>
+#include <linux/interval_tree_generic.h>
 #include <linux/iopoll.h>
 #include <linux/ktime.h>
+#include <linux/list.h>
 #include <linux/mutex.h>
+#include <linux/rbtree.h>
 #include <linux/rwsem.h>
 #include <linux/wait.h>
 #include <linux/topology.h>
@@ -95,6 +98,40 @@ static DEFINE_PER_CPU(int, cpu_pcc_subspace_idx);
  */
 static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
 
+struct cpc_sysmem_node {
+	struct rb_node rb;
+	u64 subtree_last;
+	u64 start;
+	u64 last;
+	struct cpc_desc *desc;
+	unsigned int reg_idx;
+	struct list_head aliases;
+	struct list_head alias_node;
+	struct cpc_sysmem_node *alias_of;
+	bool registered;
+};
+
+#define CPC_SYSMEM_START(node) ((node)->start)
+#define CPC_SYSMEM_LAST(node) ((node)->last)
+
+INTERVAL_TREE_DEFINE(struct cpc_sysmem_node, rb, u64, subtree_last,
+		     CPC_SYSMEM_START, CPC_SYSMEM_LAST, static inline,
+		     cpc_sysmem_itree)
+
+static struct rb_root_cached cpc_sysmem_tree = RB_ROOT_CACHED;
+static DEFINE_MUTEX(cpc_sysmem_lock);
+
+static struct cpc_sysmem_node *cpc_sysmem_first(u64 start, u64 last)
+{
+	return cpc_sysmem_itree_iter_first(&cpc_sysmem_tree, start, last);
+}
+
+static struct cpc_sysmem_node *cpc_sysmem_next(struct cpc_sysmem_node *node,
+					       u64 start, u64 last)
+{
+	return cpc_sysmem_itree_iter_next(node, start, last);
+}
+
 /* pcc mapped address + header size + offset within PCC subspace */
 #define GET_PCC_VADDR(offs, pcc_ss_id) (pcc_data[pcc_ss_id]->pcc_channel->shmem + \
 						0x8 + (offs))
@@ -255,15 +292,20 @@ static bool cpc_pcc_write_supported(const struct cpc_register_resource *reg)
 	((((val) & GENMASK_ULL(((reg)->bit_width) - 1, 0)) << (reg)->bit_offset) |	\
 	((prev_val) & ~(GENMASK_ULL(((reg)->bit_width) - 1, 0) << (reg)->bit_offset))) \
 
-static u64 cpc_sysmem_access_size(const struct cpc_register_resource *reg)
+static unsigned int cpc_reg_access_width(const struct cpc_reg *reg)
 {
-	const struct cpc_reg *gas = &reg->cpc_entry.reg;
-	unsigned int width;
-
-	if (gas->access_width > 4)
+	if (reg->access_width > 4)
 		return 0;
 
-	width = GET_BIT_WIDTH(gas);
+	if (reg->access_width)
+		return 8U << (reg->access_width - 1);
+
+	return reg->bit_width;
+}
+
+static u64 cpc_sysmem_access_size(const struct cpc_register_resource *reg)
+{
+	unsigned int width = cpc_reg_access_width(&reg->cpc_entry.reg);
 
 	if (width != 8 && width != 16 && width != 32 && width != 64)
 		return 0;
@@ -271,6 +313,12 @@ static u64 cpc_sysmem_access_size(const struct cpc_register_resource *reg)
 	return width / 8;
 }
 
+static bool cpc_reg_access_aligned(const struct cpc_reg *reg, u64 access_size)
+{
+	/* x86 MMIO and port-I/O accessors support unaligned addresses. */
+	return IS_ENABLED(CONFIG_X86) || IS_ALIGNED(reg->address, access_size);
+}
+
 static bool cpc_sysmem_access_units_overlap(const struct cpc_register_resource *a,
 					    const struct cpc_register_resource *b)
 {
@@ -289,36 +337,307 @@ static bool cpc_sysmem_access_units_overlap(const struct cpc_register_resource *
 	return a_gas->address - b_gas->address < b_size;
 }
 
+static bool cpc_reg_is_writable(unsigned int reg_idx)
+{
+	switch (reg_idx) {
+	case DESIRED_PERF:
+	case MIN_PERF:
+	case MAX_PERF:
+	case PERF_LIMITED:
+	case ENABLE:
+	case AUTO_SEL_ENABLE:
+	case AUTO_ACT_WINDOW:
+	case ENERGY_PERF:
+	case OSPM_NOMINAL_PERF:
+		return true;
+	default:
+		return false;
+	}
+}
+
+static bool cpc_sysmem_reg_needs_rmw(const struct cpc_register_resource *reg)
+{
+	const struct cpc_reg *gas = &reg->cpc_entry.reg;
+	u64 access_size = cpc_sysmem_access_size(reg);
+
+	return gas->bit_offset || gas->bit_width != access_size * 8;
+}
+
+static int cpc_validate_sysmem_reg(const struct cpc_desc *cpc_desc,
+				   const struct cpc_reg *gas,
+				   unsigned int reg_idx)
+{
+	unsigned int access_width = cpc_reg_access_width(gas);
+	u64 access_size;
+
+	if (access_width != 8 && access_width != 16 &&
+	    access_width != 32 && access_width != 64)
+		goto invalid;
+
+	if (!gas->bit_width || gas->bit_width > access_width ||
+	    gas->bit_offset >= access_width ||
+	    gas->bit_width > access_width - gas->bit_offset)
+		goto invalid;
+
+	access_size = access_width / 8;
+	if (!gas->address || gas->address > U64_MAX - (access_size - 1))
+		goto invalid;
+	if (!cpc_reg_access_aligned(gas, access_size))
+		goto invalid;
+
+	return 0;
+
+invalid:
+	pr_debug("CPU:%d invalid SystemMemory GAS for _CPC register %u\n",
+		 cpc_desc->cpu_id, reg_idx);
+	return -EINVAL;
+}
+
 static void cpc_mark_rmw_lock_users(struct cpc_desc *cpc_desc)
 {
-	int i, j;
+	int i;
+
+	for (i = 0; i < cpc_desc->num_entries - 2; i++) {
+		struct cpc_register_resource *reg = &cpc_desc->cpc_regs[i];
+
+		if (CPC_SUPPORTED(reg) && CPC_IN_SYSTEM_MEMORY(reg))
+			reg->cpc_entry.use_rmw_lock =
+				cpc_sysmem_reg_needs_rmw(reg);
+	}
+}
+
+struct cpc_bit_position {
+	u64 byte;
+	u8 bit;
+};
+
+static bool cpc_bit_position_before(const struct cpc_bit_position *a,
+				    const struct cpc_bit_position *b)
+{
+	return a->byte < b->byte || (a->byte == b->byte && a->bit < b->bit);
+}
+
+static bool cpc_sysmem_fields_overlap(const struct cpc_register_resource *a,
+				      const struct cpc_register_resource *b)
+{
+	const struct cpc_reg *a_gas = &a->cpc_entry.reg;
+	const struct cpc_reg *b_gas = &b->cpc_entry.reg;
+	unsigned int a_last_bit = a_gas->bit_offset + a_gas->bit_width - 1;
+	unsigned int b_last_bit = b_gas->bit_offset + b_gas->bit_width - 1;
+	struct cpc_bit_position a_start = {
+		.byte = a_gas->address + a_gas->bit_offset / 8,
+		.bit = a_gas->bit_offset % 8,
+	};
+	struct cpc_bit_position a_end = {
+		.byte = a_gas->address + a_last_bit / 8,
+		.bit = a_last_bit % 8,
+	};
+	struct cpc_bit_position b_start = {
+		.byte = b_gas->address + b_gas->bit_offset / 8,
+		.bit = b_gas->bit_offset % 8,
+	};
+	struct cpc_bit_position b_end = {
+		.byte = b_gas->address + b_last_bit / 8,
+		.bit = b_last_bit % 8,
+	};
+
+	return !cpc_bit_position_before(&a_end, &b_start) &&
+	       !cpc_bit_position_before(&b_end, &a_start);
+}
+
+static bool cpc_same_sysmem_register(unsigned int a_idx,
+				     const struct cpc_register_resource *a,
+				     unsigned int b_idx,
+				     const struct cpc_register_resource *b)
+{
+	const struct cpc_reg *a_gas = &a->cpc_entry.reg;
+	const struct cpc_reg *b_gas = &b->cpc_entry.reg;
+
+	return a_idx == b_idx &&
+	       a_gas->address == b_gas->address &&
+	       a_gas->bit_width == b_gas->bit_width &&
+	       a_gas->bit_offset == b_gas->bit_offset &&
+	       cpc_reg_access_width(a_gas) == cpc_reg_access_width(b_gas);
+}
+
+static int cpc_validate_sysmem_pair(const struct cpc_desc *a_desc,
+				    unsigned int a_idx,
+				    const struct cpc_desc *b_desc,
+				    unsigned int b_idx)
+{
+	const struct cpc_register_resource *a = &a_desc->cpc_regs[a_idx];
+	const struct cpc_register_resource *b = &b_desc->cpc_regs[b_idx];
+	bool a_writable, b_writable;
+
+	if (!CPC_SUPPORTED(a) || !CPC_IN_SYSTEM_MEMORY(a) ||
+	    !CPC_SUPPORTED(b) || !CPC_IN_SYSTEM_MEMORY(b) ||
+	    !cpc_sysmem_access_units_overlap(a, b))
+		return 0;
+
+	a_writable = cpc_reg_is_writable(a_idx);
+	b_writable = cpc_reg_is_writable(b_idx);
+	if (!a_writable && !b_writable)
+		return 0;
+
+	if (cpc_same_sysmem_register(a_idx, a, b_idx, b)) {
+		u64 access_size = cpc_sysmem_access_size(a);
+
+		/*
+		 * Exact partial aliases update the same field and retain
+		 * last-writer-wins semantics when the complete access is one native
+		 * transaction.  A 64-bit MMIO write may be split on 32-bit kernels,
+		 * and an unaligned x86 access is not guaranteed to be one device
+		 * transaction.
+		 */
+		if (!a_writable ||
+		    (IS_ALIGNED(a->cpc_entry.reg.address, access_size) &&
+		     (access_size < sizeof(u64) ||
+		      IS_ENABLED(CONFIG_64BIT))))
+			return 0;
+		goto conflict;
+	}
+
+	/* A full-width writable register owns its complete access unit. */
+	if ((a_writable && !cpc_sysmem_reg_needs_rmw(a)) ||
+	    (b_writable && !cpc_sysmem_reg_needs_rmw(b)) ||
+	    (a_writable && b_writable && cpc_sysmem_fields_overlap(a, b)))
+		goto conflict;
+
+	/* Different descriptors do not share their partial-write locks. */
+	if (a_desc != b_desc && a_writable && b_writable)
+		goto conflict;
+
+	return 0;
+
+conflict:
+	pr_err("CPU%d: SystemMemory _CPC register %u conflicts with CPU%d register %u\n",
+	       a_desc->cpu_id, a_idx, b_desc->cpu_id, b_idx);
+	return -EINVAL;
+}
+
+static void cpc_unregister_sysmem_desc_locked(struct cpc_desc *cpc_desc)
+{
+	unsigned int i;
+
+	if (!cpc_desc->sysmem_nodes)
+		return;
 
 	for (i = 0; i < cpc_desc->num_entries - 2; i++) {
-		struct cpc_register_resource *a = &cpc_desc->cpc_regs[i];
-		struct cpc_reg *gas;
-		u64 access_size;
+		struct cpc_sysmem_node *node = &cpc_desc->sysmem_nodes[i];
+		struct cpc_sysmem_node *alias, *child;
 
-		if (!CPC_SUPPORTED(a) || !CPC_IN_SYSTEM_MEMORY(a))
+		if (node->alias_of) {
+			list_del(&node->alias_node);
+			continue;
+		}
+		if (!node->registered)
 			continue;
 
-		gas = &a->cpc_entry.reg;
-		access_size = cpc_sysmem_access_size(a);
-		if (gas->bit_offset || !access_size ||
-		    gas->bit_width != access_size * 8)
-			a->cpc_entry.use_rmw_lock = true;
+		cpc_sysmem_itree_remove(node, &cpc_sysmem_tree);
+		node->registered = false;
+		if (list_empty(&node->aliases))
+			continue;
 
-		for (j = i + 1; j < cpc_desc->num_entries - 2; j++) {
-			struct cpc_register_resource *b = &cpc_desc->cpc_regs[j];
+		/* Keep one representative for aliases owned by live descriptors. */
+		alias = list_first_entry(&node->aliases,
+					 struct cpc_sysmem_node, alias_node);
+		list_del_init(&alias->alias_node);
+		alias->alias_of = NULL;
+		alias->registered = true;
+		list_splice_init(&node->aliases, &alias->aliases);
+		list_for_each_entry(child, &alias->aliases, alias_node)
+			child->alias_of = alias;
+		cpc_sysmem_itree_insert(alias, &cpc_sysmem_tree);
+	}
 
-			if (!CPC_SUPPORTED(b) || !CPC_IN_SYSTEM_MEMORY(b))
-				continue;
-			if (!cpc_sysmem_access_units_overlap(a, b))
-				continue;
+	kfree(cpc_desc->sysmem_nodes);
+	cpc_desc->sysmem_nodes = NULL;
+}
+
+static int cpc_register_sysmem_desc(struct cpc_desc *cpc_desc)
+{
+	unsigned int nr_regs = cpc_desc->num_entries - 2;
+	unsigned int i;
+	int ret = 0;
+	bool found = false;
+
+	for (i = 0; i < nr_regs; i++) {
+		struct cpc_register_resource *reg = &cpc_desc->cpc_regs[i];
 
-			a->cpc_entry.use_rmw_lock = true;
-			b->cpc_entry.use_rmw_lock = true;
+		if (CPC_SUPPORTED(reg) && CPC_IN_SYSTEM_MEMORY(reg)) {
+			found = true;
+			break;
 		}
 	}
+	if (!found)
+		return 0;
+
+	cpc_desc->sysmem_nodes = kcalloc(nr_regs,
+					 sizeof(*cpc_desc->sysmem_nodes),
+					 GFP_KERNEL);
+	if (!cpc_desc->sysmem_nodes)
+		return -ENOMEM;
+
+	mutex_lock(&cpc_sysmem_lock);
+
+	for (i = 0; i < nr_regs; i++) {
+		struct cpc_register_resource *reg = &cpc_desc->cpc_regs[i];
+		struct cpc_sysmem_node *alias = NULL, *match, *node;
+		u64 size;
+
+		if (!CPC_SUPPORTED(reg) || !CPC_IN_SYSTEM_MEMORY(reg))
+			continue;
+
+		node = &cpc_desc->sysmem_nodes[i];
+		size = cpc_sysmem_access_size(reg);
+		node->start = reg->cpc_entry.reg.address;
+		node->last = node->start + size - 1;
+		node->desc = cpc_desc;
+		node->reg_idx = i;
+		INIT_LIST_HEAD(&node->aliases);
+		INIT_LIST_HEAD(&node->alias_node);
+
+		match = cpc_sysmem_first(node->start, node->last);
+		while (match) {
+			struct cpc_register_resource *match_reg;
+
+			ret = cpc_validate_sysmem_pair(cpc_desc, i, match->desc,
+						       match->reg_idx);
+			if (ret)
+				goto out_unregister;
+			match_reg = &match->desc->cpc_regs[match->reg_idx];
+			if (cpc_same_sysmem_register(i, reg, match->reg_idx, match_reg))
+				alias = match;
+
+			match = cpc_sysmem_next(match, node->start, node->last);
+		}
+		if (alias) {
+			node->alias_of = alias;
+			list_add_tail(&node->alias_node, &alias->aliases);
+			continue;
+		}
+
+		cpc_sysmem_itree_insert(node, &cpc_sysmem_tree);
+		node->registered = true;
+	}
+
+	mutex_unlock(&cpc_sysmem_lock);
+	return 0;
+
+out_unregister:
+	cpc_unregister_sysmem_desc_locked(cpc_desc);
+	mutex_unlock(&cpc_sysmem_lock);
+	return ret;
+}
+
+static void cpc_unregister_sysmem_desc(struct cpc_desc *cpc_desc)
+{
+	if (!cpc_desc->sysmem_nodes)
+		return;
+
+	mutex_lock(&cpc_sysmem_lock);
+	cpc_unregister_sysmem_desc_locked(cpc_desc);
+	mutex_unlock(&cpc_sysmem_lock);
 }
 
 static ssize_t show_feedback_ctrs(struct kobject *kobj,
@@ -356,6 +675,8 @@ static void cppc_free_desc(struct cpc_desc *cpc_ptr)
 {
 	unsigned int i;
 
+	cpc_unregister_sysmem_desc(cpc_ptr);
+
 	for (i = 2; i < cpc_ptr->num_entries; i++) {
 		void __iomem *addr = cpc_ptr->cpc_regs[i - 2].sys_mem_vaddr;
 
@@ -954,6 +1275,7 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 		ret = -ENOMEM;
 		goto out_buf_free;
 	}
+	cpc_ptr->cpu_id = pr->id;
 
 	/* First entry is NumEntries. */
 	cpc_obj = &out_obj->package.elements[0];
@@ -1069,10 +1391,16 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 					goto out_free;
 				}
 			} else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
-				if (gas_t->address) {
+				if (!IS_NULL_REG(gas_t)) {
 					void __iomem *addr;
 					size_t access_width;
 
+					err = cpc_validate_sysmem_reg(cpc_ptr, gas_t, i - 2);
+					if (err) {
+						ret = err;
+						goto out_free;
+					}
+
 					if (!osc_cpc_flexible_adr_space_confirmed) {
 						pr_debug("Flexible address space capability not supported\n");
 						ret = -EOPNOTSUPP;
@@ -1081,13 +1409,14 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 						ret = -EINVAL;
 					}
 
-					access_width = GET_BIT_WIDTH(gas_t) / 8;
+					access_width = cpc_reg_access_width(gas_t);
+					access_width /= 8;
 					addr = ioremap(gas_t->address, access_width);
 					if (!addr) {
 						ret = -ENOMEM;
 						goto out_free;
 					}
-					cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr;
+					cpc_ptr->cpc_regs[i - 2].sys_mem_vaddr = addr;
 				}
 			} else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
 				if (gas_t->access_width < 1 || gas_t->access_width > 3) {
@@ -1123,8 +1452,9 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 				}
 			}
 
-			cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER;
-			memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t));
+			cpc_ptr->cpc_regs[i - 2].type = ACPI_TYPE_BUFFER;
+			memcpy(&cpc_ptr->cpc_regs[i - 2].cpc_entry.reg, gas_t,
+			       sizeof(*gas_t));
 		} else if (cpc_obj->type == ACPI_TYPE_PACKAGE && (i - 2) == RESOURCE_PRIORITY) {
 			/*
 			 * ACPI 6.6, s8.4.6.1.2.7 defines Resource Priority as a
@@ -1184,8 +1514,6 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 	}
 
 
-	/* Store CPU Logical ID */
-	cpc_ptr->cpu_id = pr->id;
 	cpc_mark_rmw_lock_users(cpc_ptr);
 	raw_spin_lock_init(&cpc_ptr->rmw_lock);
 
@@ -1194,6 +1522,10 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 	if (ret)
 		goto out_free;
 
+	ret = cpc_register_sysmem_desc(cpc_ptr);
+	if (ret)
+		goto out_free;
+
 	/* Register PCC channel once for all PCC subspace ID. */
 	if (pcc_subspace_id >= 0) {
 		ret = register_pcc_channel(pcc_subspace_id);
@@ -1218,6 +1550,7 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 			"acpi_cppc");
 	if (ret) {
 		per_cpu(cpc_desc_ptr, pr->id) = NULL;
+		cpc_unregister_sysmem_desc(cpc_ptr);
 		kobject_put(&cpc_ptr->kobj);
 		goto out_pcc_put;
 	}
@@ -1261,6 +1594,7 @@ void acpi_cppc_processor_exit(struct acpi_processor *pr)
 	pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, pr->id);
 	per_cpu(cpc_desc_ptr, pr->id) = NULL;
 	kobject_del(&cpc_ptr->kobj);
+	cpc_unregister_sysmem_desc(cpc_ptr);
 
 	pcc_data_put(pcc_ss_id);
 	per_cpu(cpu_pcc_subspace_idx, pr->id) = -1;
@@ -1448,11 +1782,7 @@ static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
 				val, size);
 
 	if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
-		/*
-		 * The _CPC layout is immutable after probe. The precomputed flag
-		 * retains serialization for partial fields or overlapping access
-		 * units; standalone full-width registers avoid the lock.
-		 */
+		/* Partial fields use their per-CPU descriptor lock. */
 		locked = reg_res->cpc_entry.use_rmw_lock;
 		if (locked) {
 			cpc_desc = per_cpu(cpc_desc_ptr, cpu);
diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h
index 5dcbe65c5ddc..168e3143e6ae 100644
--- a/include/acpi/cppc_acpi.h
+++ b/include/acpi/cppc_acpi.h
@@ -77,6 +77,8 @@ struct cpc_register_resource {
 	} cpc_entry;
 };
 
+struct cpc_sysmem_node;
+
 /* Container to hold the CPC details for each CPU */
 struct cpc_desc {
 	int num_entries;
@@ -84,10 +86,11 @@ struct cpc_desc {
 	int cpu_id;
 	int write_cmd_status;
 	int write_cmd_id;
-	/* Lock used for RMW operations in cpc_write() */
+	/* Serialize partial SystemMemory writes within this descriptor. */
 	raw_spinlock_t rmw_lock;
 	struct cpc_register_resource cpc_regs[MAX_CPC_REG_ENT];
 	struct acpi_psd_package domain_info;
+	struct cpc_sysmem_node *sysmem_nodes;
 	struct kobject kobj;
 };
 
-- 
2.34.1

[PATCH v6 10/15] ACPI: CPPC: Reject direct reads of write-only controls

[Christian Loehle]

Between _CPC revision 3 and revision 4, Desired Performance changed from
Read/Write to Write. Revision 4 also added the write-only OSPM Nominal
Performance control. ACPI 6.6 section 4.6.3 says reads of write-only bit
positions produce undefined results.

The public Desired Performance helper already rejects revision-4 readback,
but the common register accessor still permits either write-only control to
be read. Reject both centrally so new callers cannot consume undefined
values.

A partial SystemMemory field still makes cpc_write() read its complete
access unit to preserve bits outside the field. MASK_VAL_WRITE() replaces
every bit of the field being written, so that field's undefined readback is
not propagated. However, another writer sharing the access unit would
preserve and replay the write-only field when performing its own RMW.
Reject such pairs; a partial write-only field may share its access unit
only with disjoint read-only fields. The descriptor lock serializes
supported RMW, and the preceding validation rejects unsafe cross-descriptor
partial writers.

Keep an invalid but locatable write-only SystemMemory descriptor
represented during overlap validation, but mark it unreadable and
unwritable. Otherwise a neighbouring RMW field could evade validation and
replay undefined readback into the hidden control. Conservatively claim the
larger of the declared access unit and logical field span. Check if the
writer access unit covers the write-only field so harmless asymmetric
geometries are not rejected. Preserve a decoded access-unit claim even when
the malformed Bit Width is zero, and use that claimed range when testing
whether another writer's access overlaps the hidden field.

A retained range-only descriptor cannot issue a transaction over that whole
conservative claim. Keep the full-width ownership rule for accessible
descriptors, but reject a full-width writer against a range-only descriptor
only when its access covers the hidden logical field. Likewise, count only
accessible descriptors as writers in the generic writer-conflict rules;
the dedicated write-only-field check still protects a retained descriptor
from an accessible writer's RMW.

Mark an inaccessible OSPM Nominal Performance control unsupported because
it is optional. Do the same for inaccessible Desired Performance while
parsing, then let the post-parse control check accept it only for immutable
autonomous selection. This preserves the autonomous-only exception without
accepting an unusable Desired control in non-autonomous mode.

Do not advertise fast switching or zero transition latency unless Desired
Performance remains writable. An inaccessible descriptor retained only for
overlap validation still carries its original address-space identity, but
cannot service a performance request.

Fixes: 71e1815113f7 ("ACPI: CPPC: Add support for CPPC v4")
Reported-by: Sashiko <sashiko-bot@kernel.org>
Link: https://sashiko.dev/#/patchset/20260807111303.1062391-1-christian.loehle%40arm.com
Link: https://sashiko.dev/#/patchset/20260808082644.1251332-1-christian.loehle%40arm.com
Signed-off-by: Christian Loehle <christian.loehle@arm.com>
---
 drivers/acpi/cppc_acpi.c | 153 +++++++++++++++++++++++++++++++++++----
 include/acpi/cppc_acpi.h |   2 +
 2 files changed, 141 insertions(+), 14 deletions(-)

diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
index 058f4c71d981..bb83b5c9ab31 100644
--- a/drivers/acpi/cppc_acpi.c
+++ b/drivers/acpi/cppc_acpi.c
@@ -171,7 +171,14 @@ static struct cpc_sysmem_node *cpc_sysmem_next(struct cpc_sysmem_node *node,
 static bool cpc_is_writable(const struct cpc_register_resource *cpc)
 {
 	return cpc->type == ACPI_TYPE_BUFFER &&
-	       !IS_NULL_REG(&cpc->cpc_entry.reg);
+	       !IS_NULL_REG(&cpc->cpc_entry.reg) &&
+	       !cpc->cpc_entry.write_unsupported;
+}
+
+static bool cpc_is_readable(const struct cpc_register_resource *cpc)
+{
+	return cpc->type != ACPI_TYPE_BUFFER ||
+	       !cpc->cpc_entry.read_unsupported;
 }
 
 static bool cpc_entry_present(const struct cpc_register_resource *cpc)
@@ -313,6 +320,22 @@ static u64 cpc_sysmem_access_size(const struct cpc_register_resource *reg)
 	return width / 8;
 }
 
+static u64 cpc_sysmem_field_size(const struct cpc_reg *gas)
+{
+	return DIV_ROUND_UP((u64)gas->bit_offset + gas->bit_width, 8);
+}
+
+static u64 cpc_sysmem_claim_size(const struct cpc_register_resource *reg)
+{
+	const struct cpc_reg *gas = &reg->cpc_entry.reg;
+	u64 access_size = cpc_sysmem_access_size(reg);
+
+	if (!gas->bit_width)
+		return access_size;
+
+	return max(access_size, cpc_sysmem_field_size(gas));
+}
+
 static bool cpc_reg_access_aligned(const struct cpc_reg *reg, u64 access_size)
 {
 	/* x86 MMIO and port-I/O accessors support unaligned addresses. */
@@ -324,8 +347,8 @@ static bool cpc_sysmem_access_units_overlap(const struct cpc_register_resource *
 {
 	const struct cpc_reg *a_gas = &a->cpc_entry.reg;
 	const struct cpc_reg *b_gas = &b->cpc_entry.reg;
-	u64 a_size = cpc_sysmem_access_size(a);
-	u64 b_size = cpc_sysmem_access_size(b);
+	u64 a_size = cpc_sysmem_claim_size(a);
+	u64 b_size = cpc_sysmem_claim_size(b);
 
 	/* Keep the conservative locking path for malformed access widths. */
 	if (!a_size || !b_size)
@@ -355,6 +378,21 @@ static bool cpc_reg_is_writable(unsigned int reg_idx)
 	}
 }
 
+static bool cpc_reg_is_write_only(const struct cpc_desc *cpc_desc,
+				  unsigned int reg_idx)
+{
+	return cpc_desc->version >= CPPC_V4_REV &&
+	       (reg_idx == DESIRED_PERF || reg_idx == OSPM_NOMINAL_PERF);
+}
+
+static void cpc_disable_reg(struct cpc_desc *cpc_desc, unsigned int reg_idx)
+{
+	struct cpc_register_resource *reg = &cpc_desc->cpc_regs[reg_idx];
+
+	reg->type = ACPI_TYPE_INTEGER;
+	reg->cpc_entry.int_value = 0;
+}
+
 static bool cpc_sysmem_reg_needs_rmw(const struct cpc_register_resource *reg)
 {
 	const struct cpc_reg *gas = &reg->cpc_entry.reg;
@@ -363,7 +401,7 @@ static bool cpc_sysmem_reg_needs_rmw(const struct cpc_register_resource *reg)
 	return gas->bit_offset || gas->bit_width != access_size * 8;
 }
 
-static int cpc_validate_sysmem_reg(const struct cpc_desc *cpc_desc,
+static int cpc_validate_sysmem_reg(struct cpc_desc *cpc_desc,
 				   const struct cpc_reg *gas,
 				   unsigned int reg_idx)
 {
@@ -388,6 +426,23 @@ static int cpc_validate_sysmem_reg(const struct cpc_desc *cpc_desc,
 	return 0;
 
 invalid:
+	access_size = 0;
+	if (access_width == 8 || access_width == 16 ||
+	    access_width == 32 || access_width == 64)
+		access_size = access_width / 8;
+	if (gas->bit_width)
+		access_size = max(access_size, cpc_sysmem_field_size(gas));
+	if (cpc_reg_is_write_only(cpc_desc, reg_idx) && gas->address &&
+	    access_size && gas->address <= U64_MAX - (access_size - 1)) {
+		struct cpc_register_resource *reg = &cpc_desc->cpc_regs[reg_idx];
+
+		pr_warn("CPU%d: _CPC v%d register %u is inaccessible; keeping its range reserved\n",
+			cpc_desc->cpu_id, cpc_desc->version, reg_idx);
+		reg->cpc_entry.read_unsupported = true;
+		reg->cpc_entry.write_unsupported = true;
+		return 0;
+	}
+
 	pr_debug("CPU:%d invalid SystemMemory GAS for _CPC register %u\n",
 		 cpc_desc->cpu_id, reg_idx);
 	return -EINVAL;
@@ -445,6 +500,39 @@ static bool cpc_sysmem_fields_overlap(const struct cpc_register_resource *a,
 	       !cpc_bit_position_before(&b_end, &a_start);
 }
 
+static bool cpc_sysmem_access_overlaps_field(const struct cpc_register_resource *access,
+					     const struct cpc_register_resource *field)
+{
+	const struct cpc_reg *access_gas = &access->cpc_entry.reg;
+	const struct cpc_reg *field_gas = &field->cpc_entry.reg;
+	u64 access_last;
+	u64 field_start;
+	u64 field_last;
+
+	if (!field_gas->bit_width)
+		return cpc_sysmem_access_units_overlap(access, field);
+
+	access_last = access_gas->address +
+		      cpc_sysmem_access_size(access) - 1;
+	field_start = field_gas->address + field_gas->bit_offset / 8;
+	field_last = field_gas->address +
+		     (field_gas->bit_offset + field_gas->bit_width - 1) / 8;
+
+	return access_gas->address <= field_last && field_start <= access_last;
+}
+
+static bool cpc_sysmem_full_width_conflicts(const struct cpc_register_resource *writer,
+					    const struct cpc_register_resource *other)
+{
+	/*
+	 * An accessible descriptor may issue a transaction over its complete
+	 * access unit.  A retained range-only descriptor cannot; protect only
+	 * its logical field from the full-width writer.
+	 */
+	return cpc_is_readable(other) || cpc_is_writable(other) ||
+	       cpc_sysmem_access_overlaps_field(writer, other);
+}
+
 static bool cpc_same_sysmem_register(unsigned int a_idx,
 				     const struct cpc_register_resource *a,
 				     unsigned int b_idx,
@@ -474,8 +562,8 @@ static int cpc_validate_sysmem_pair(const struct cpc_desc *a_desc,
 	    !cpc_sysmem_access_units_overlap(a, b))
 		return 0;
 
-	a_writable = cpc_reg_is_writable(a_idx);
-	b_writable = cpc_reg_is_writable(b_idx);
+	a_writable = cpc_reg_is_writable(a_idx) && cpc_is_writable(a);
+	b_writable = cpc_reg_is_writable(b_idx) && cpc_is_writable(b);
 	if (!a_writable && !b_writable)
 		return 0;
 
@@ -498,8 +586,10 @@ static int cpc_validate_sysmem_pair(const struct cpc_desc *a_desc,
 	}
 
 	/* A full-width writable register owns its complete access unit. */
-	if ((a_writable && !cpc_sysmem_reg_needs_rmw(a)) ||
-	    (b_writable && !cpc_sysmem_reg_needs_rmw(b)) ||
+	if ((a_writable && !cpc_sysmem_reg_needs_rmw(a) &&
+	     cpc_sysmem_full_width_conflicts(a, b)) ||
+	    (b_writable && !cpc_sysmem_reg_needs_rmw(b) &&
+	     cpc_sysmem_full_width_conflicts(b, a)) ||
 	    (a_writable && b_writable && cpc_sysmem_fields_overlap(a, b)))
 		goto conflict;
 
@@ -507,6 +597,18 @@ static int cpc_validate_sysmem_pair(const struct cpc_desc *a_desc,
 	if (a_desc != b_desc && a_writable && b_writable)
 		goto conflict;
 
+	/*
+	 * RMW of either writer preserves the other field.  If that field is
+	 * write-only, its readback is undefined and cannot safely be replayed.
+	 */
+	if ((cpc_reg_is_write_only(a_desc, a_idx) && b_writable &&
+	     cpc_sysmem_reg_needs_rmw(b) &&
+	     cpc_sysmem_access_overlaps_field(b, a)) ||
+	    (cpc_reg_is_write_only(b_desc, b_idx) && a_writable &&
+	     cpc_sysmem_reg_needs_rmw(a) &&
+	     cpc_sysmem_access_overlaps_field(a, b)))
+		goto conflict;
+
 	return 0;
 
 conflict:
@@ -589,7 +691,7 @@ static int cpc_register_sysmem_desc(struct cpc_desc *cpc_desc)
 			continue;
 
 		node = &cpc_desc->sysmem_nodes[i];
-		size = cpc_sysmem_access_size(reg);
+		size = cpc_sysmem_claim_size(reg);
 		node->start = reg->cpc_entry.reg.address;
 		node->last = node->start + size - 1;
 		node->desc = cpc_desc;
@@ -970,7 +1072,7 @@ bool cppc_allow_fast_switch(const struct cpumask *cpus)
 		min_reg = &cpc_ptr->cpc_regs[MIN_PERF];
 		max_reg = &cpc_ptr->cpc_regs[MAX_PERF];
 
-		if (!CPC_SUPPORTED(desired_reg) ||
+		if (!cpc_is_writable(desired_reg) ||
 		    (!CPC_IN_SYSTEM_MEMORY(desired_reg) &&
 		     !CPC_IN_SYSTEM_IO(desired_reg)) ||
 		    (CPC_SUPPORTED(min_reg) &&
@@ -1370,6 +1472,10 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 				goto out_free;
 			}
 
+			cpc_ptr->cpc_regs[i - 2].type = ACPI_TYPE_BUFFER;
+			memcpy(&cpc_ptr->cpc_regs[i - 2].cpc_entry.reg, gas_t,
+			       sizeof(*gas_t));
+
 			/*
 			 * The PCC Subspace index is encoded inside
 			 * the CPC table entries. The same PCC index
@@ -1396,10 +1502,24 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 					size_t access_width;
 
 					err = cpc_validate_sysmem_reg(cpc_ptr, gas_t, i - 2);
+					if (err && (i - 2 == DESIRED_PERF ||
+						    i - 2 == OSPM_NOMINAL_PERF)) {
+						const char *name = i - 2 == DESIRED_PERF ?
+								   "Desired Performance" :
+								   "OSPM Nominal Performance";
+
+						pr_warn("CPU%d: disabling inaccessible %s register\n",
+							pr->id, name);
+						cpc_disable_reg(cpc_ptr, i - 2);
+						continue;
+					}
 					if (err) {
 						ret = err;
 						goto out_free;
 					}
+					if (!cpc_is_readable(&cpc_ptr->cpc_regs[i - 2]) &&
+					    !cpc_is_writable(&cpc_ptr->cpc_regs[i - 2]))
+						continue;
 
 					if (!osc_cpc_flexible_adr_space_confirmed) {
 						pr_debug("Flexible address space capability not supported\n");
@@ -1451,10 +1571,6 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 					goto out_free;
 				}
 			}
-
-			cpc_ptr->cpc_regs[i - 2].type = ACPI_TYPE_BUFFER;
-			memcpy(&cpc_ptr->cpc_regs[i - 2].cpc_entry.reg, gas_t,
-			       sizeof(*gas_t));
 		} else if (cpc_obj->type == ACPI_TYPE_PACKAGE && (i - 2) == RESOURCE_PRIORITY) {
 			/*
 			 * ACPI 6.6, s8.4.6.1.2.7 defines Resource Priority as a
@@ -1794,6 +1910,10 @@ static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
 		}
 
 		if (reg->bit_offset || reg->bit_width != size) {
+			/*
+			 * MASK_VAL_WRITE() discards the field's old bits, so undefined
+			 * readback from a write-only field is not propagated.
+			 */
 			switch (size) {
 			case 8:
 				prev_val = readb_relaxed(vaddr);
@@ -1885,6 +2005,8 @@ static int cppc_get_reg_val(int cpu, enum cppc_regs reg_idx, u64 *val)
 		pr_debug("No CPC descriptor for CPU:%d\n", cpu);
 		return -ENODEV;
 	}
+	if (cpc_reg_is_write_only(cpc_desc, reg_idx))
+		return -EOPNOTSUPP;
 
 	reg = &cpc_desc->cpc_regs[reg_idx];
 
@@ -2975,6 +3097,9 @@ int cppc_get_transition_latency(int cpu_num)
 		return -ENODATA;
 
 	desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
+	if (!cpc_is_writable(desired_reg))
+		return -ENODATA;
+
 	if (CPC_IN_SYSTEM_MEMORY(desired_reg) || CPC_IN_SYSTEM_IO(desired_reg))
 		return 0;
 
diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h
index 168e3143e6ae..4e5f59bc95f8 100644
--- a/include/acpi/cppc_acpi.h
+++ b/include/acpi/cppc_acpi.h
@@ -72,6 +72,8 @@ struct cpc_register_resource {
 		struct {
 			struct cpc_reg reg;
 			bool use_rmw_lock;
+			bool read_unsupported;
+			bool write_unsupported;
 		};
 		u64 int_value;
 	} cpc_entry;
-- 
2.34.1

[PATCH v6 11/15] ACPI: CPPC: Validate and access PCC register layouts

[Christian Loehle]

PCC GAS Access Size identifies the subspace, so the accessors use Bit Width
as the field size. Their typed readw/readl/readq operations require natural
alignment and support only 8, 16, 32, or 64 bits. This rejects valid
firmware: ACPI 6.6 shows a mandatory 32-bit Delivered Performance Counter
at unaligned offset 0x116, while read-only fields may use byte-multiple
widths such as 24 bits.

Support zero-offset, byte-multiple fields up to 64 bits with byte-oriented
I/O and explicit little-endian encoding. A short per-subspace raw spinlock
serializes aliased payload copies performed concurrently under the shared
side of pcc_lock. Read-only fields may retain byte widths through 64 bits.
Keep writable fields restricted to the previously supported 8-, 16-, 32-,
and 64-bit geometries until cross-processor overlap validation is installed
later in the series. Most CPPC controls are limited to 32 bits, so reject a
64-bit encoding for them. Retain 64-bit Performance Limited, CPPC Enable,
and Autonomous Selection Enable fields, whose specified sizes have only
lower bounds. Fields with a nonzero bit offset or non-byte width still need
unsupported RMW semantics and are rejected or disabled.

Order completion status before consuming returned payload bytes, and
publish every byte-oriented payload store before another CPU can ring the
doorbell. This preserves the PCC status/payload ordering despite relaxed
MMIO and the short payload lock.

Defer the unsupported-field decision until the entire package is known. A
provided but inaccessible CPPC Enable control fails probe because OSPM must
write it before using CPPC. An inaccessible Desired control can be ignored
only for immutable autonomous operation. If both Minimum and Maximum
controls are inaccessible, disable the pair coherently; a one-sided
inaccessible bound fails probe. The post-sanitization check enforces the
specification requirement that both controls exist or neither does. Other
inaccessible optional controls are marked absent; mandatory controls fail.

Keep the eventual probe result negative while temporary validation helpers
succeed. This prevents a later malformed entry, unsupported address space,
or mapping failure from freeing the descriptor and nevertheless returning
success.

Apply the same control-specific policy to unsupported SystemMemory
geometry. Once the PCC channel is available, verify every retained field
fits after the eight-byte header and within shared memory, and reject
overlapping logical ranges when either is writable.

This deliberately does not implement bit-level PCC RMW. In particular, the
one-bit CPPC Enable field in the specification example now produces an
explicit probe failure instead of being silently treated as absent.

Fixes: 85b1407bf6d2 ("ACPI / CPPC: Make CPPC ACPI driver aware of PCC subspace IDs")
Signed-off-by: Christian Loehle <christian.loehle@arm.com>
---
 drivers/acpi/cppc_acpi.c | 320 +++++++++++++++++++++++++++++++++------
 1 file changed, 275 insertions(+), 45 deletions(-)

diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
index bb83b5c9ab31..d81ac477d184 100644
--- a/drivers/acpi/cppc_acpi.c
+++ b/drivers/acpi/cppc_acpi.c
@@ -74,6 +74,8 @@ struct cppc_pcc_data {
 	 *	Take write_lock for all purposes which gives exclusive access
 	 */
 	struct rw_semaphore pcc_lock;
+	/* Serialize byte-oriented accesses to aliased PCC payload fields. */
+	raw_spinlock_t payload_lock;
 
 	/* Wait queue for CPUs whose requests were batched */
 	wait_queue_head_t pcc_write_wait_q;
@@ -132,9 +134,11 @@ static struct cpc_sysmem_node *cpc_sysmem_next(struct cpc_sysmem_node *node,
 	return cpc_sysmem_itree_iter_next(node, start, last);
 }
 
+#define CPC_PCC_HEADER_SIZE	0x8
+
 /* pcc mapped address + header size + offset within PCC subspace */
 #define GET_PCC_VADDR(offs, pcc_ss_id) (pcc_data[pcc_ss_id]->pcc_channel->shmem + \
-						0x8 + (offs))
+						CPC_PCC_HEADER_SIZE + (offs))
 
 /* Check if a CPC register is in PCC */
 #define CPC_IN_PCC(cpc) ((cpc)->type == ACPI_TYPE_BUFFER &&		\
@@ -448,6 +452,184 @@ static int cpc_validate_sysmem_reg(struct cpc_desc *cpc_desc,
 	return -EINVAL;
 }
 
+static bool cpc_immutable_autonomous(const struct cpc_desc *cpc_desc)
+{
+	const struct cpc_register_resource *reg;
+
+	reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
+	return osc_sb_cppc2_support_acked && reg->type == ACPI_TYPE_INTEGER &&
+	       reg->cpc_entry.int_value == 1;
+}
+
+static int cpc_resolve_unsupported(struct cpc_desc *cpc_desc,
+				   u32 unsupported)
+{
+	unsigned int i;
+	u32 bounds = BIT(MIN_PERF) | BIT(MAX_PERF);
+	bool min_unusable, max_unusable;
+
+	if (unsupported & bounds) {
+		min_unusable = (unsupported & BIT(MIN_PERF)) ||
+			       !cpc_is_writable(&cpc_desc->cpc_regs[MIN_PERF]);
+		max_unusable = (unsupported & BIT(MAX_PERF)) ||
+			       !cpc_is_writable(&cpc_desc->cpc_regs[MAX_PERF]);
+		if (min_unusable && max_unusable) {
+			pr_warn("CPU%d: ignoring inaccessible Minimum and Maximum Performance registers\n",
+				cpc_desc->cpu_id);
+			cpc_disable_reg(cpc_desc, MIN_PERF);
+			cpc_disable_reg(cpc_desc, MAX_PERF);
+			unsupported &= ~bounds;
+		}
+	}
+
+	for (i = 0; i < cpc_desc->num_entries - 2; i++) {
+		if (!(unsupported & BIT(i)))
+			continue;
+
+		if (i == DESIRED_PERF && cpc_immutable_autonomous(cpc_desc)) {
+			pr_warn("CPU%d: ignoring inaccessible Desired Performance register in autonomous mode\n",
+				cpc_desc->cpu_id);
+			cpc_disable_reg(cpc_desc, i);
+			continue;
+		}
+
+		/* A present Enable control must be usable to enter CPPC mode. */
+		if (i == ENABLE || i == MIN_PERF || i == MAX_PERF ||
+		    !IS_OPTIONAL_CPC_REG(i)) {
+			pr_err("CPU%d: cannot access _CPC register %u\n",
+			       cpc_desc->cpu_id, i);
+			return -EINVAL;
+		}
+
+		pr_warn("CPU%d: ignoring inaccessible optional _CPC register %u\n",
+			cpc_desc->cpu_id, i);
+		cpc_disable_reg(cpc_desc, i);
+	}
+
+	return 0;
+}
+
+static int cpc_validate_required_controls(struct cpc_desc *cpc_desc)
+{
+	bool have_min, have_max;
+	unsigned int i;
+
+	/*
+	 * Performance Limited is required by the specification, but tolerate a
+	 * NULL descriptor used by firmware which cannot report limiting events.
+	 * CPPC control does not depend on this status.
+	 */
+	for (i = 0; i < cpc_desc->num_entries - 2; i++) {
+		if (i != DESIRED_PERF && i != PERF_LIMITED &&
+		    !IS_OPTIONAL_CPC_REG(i) &&
+		    !cpc_entry_present(&cpc_desc->cpc_regs[i])) {
+			pr_debug("CPU:%d lacks mandatory _CPC register %u\n",
+				 cpc_desc->cpu_id, i);
+			return -EINVAL;
+		}
+	}
+
+	/* Desired may be absent only for immutable autonomous operation. */
+	if (!cpc_is_writable(&cpc_desc->cpc_regs[DESIRED_PERF]) &&
+	    !cpc_immutable_autonomous(cpc_desc)) {
+		pr_debug("CPU:%d lacks a writable Desired Performance register\n",
+			 cpc_desc->cpu_id);
+		return -EINVAL;
+	}
+
+	have_min = cpc_is_writable(&cpc_desc->cpc_regs[MIN_PERF]);
+	have_max = cpc_is_writable(&cpc_desc->cpc_regs[MAX_PERF]);
+	if (have_min != have_max) {
+		pr_err("CPU%d: _CPC must provide both Minimum and Maximum Performance or neither\n",
+		       cpc_desc->cpu_id);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static void cpc_validate_pcc_bounds(struct cpc_desc *cpc_desc,
+				    struct cppc_pcc_data *data,
+				    u32 *unsupported)
+{
+	u64 shmem_size = data->pcc_channel->shmem_size;
+	unsigned int i;
+
+	for (i = 0; i < cpc_desc->num_entries - 2; i++) {
+		struct cpc_register_resource *reg = &cpc_desc->cpc_regs[i];
+		struct cpc_reg *gas;
+		u64 access_size;
+
+		if ((*unsupported & BIT(i)) || !CPC_SUPPORTED(reg) ||
+		    !CPC_IN_PCC(reg))
+			continue;
+
+		gas = &reg->cpc_entry.reg;
+		access_size = gas->bit_width / 8;
+		if (shmem_size >= CPC_PCC_HEADER_SIZE &&
+		    gas->address <= shmem_size - CPC_PCC_HEADER_SIZE &&
+		    access_size <= shmem_size - CPC_PCC_HEADER_SIZE - gas->address)
+			continue;
+
+		pr_debug("CPU%d: _CPC register %u exceeds the PCC shared region\n",
+			 cpc_desc->cpu_id, i);
+		*unsupported |= BIT(i);
+	}
+}
+
+static u64 cpc_non_mmio_access_size(const struct cpc_register_resource *reg)
+{
+	const struct cpc_reg *gas = &reg->cpc_entry.reg;
+
+	if (gas->space_id == ACPI_ADR_SPACE_PLATFORM_COMM)
+		return gas->bit_width / 8;
+
+	return cpc_reg_access_width(gas) / 8;
+}
+
+static int cpc_validate_non_mmio_overlaps(struct cpc_desc *cpc_desc,
+					  u8 space_id, const char *name)
+{
+	unsigned int i, j;
+
+	for (i = 0; i < cpc_desc->num_entries - 2; i++) {
+		struct cpc_register_resource *a = &cpc_desc->cpc_regs[i];
+		const struct cpc_reg *a_gas;
+		u64 a_size;
+
+		if (!CPC_SUPPORTED(a) || a->type != ACPI_TYPE_BUFFER ||
+		    a->cpc_entry.reg.space_id != space_id)
+			continue;
+
+		a_gas = &a->cpc_entry.reg;
+		a_size = cpc_non_mmio_access_size(a);
+		for (j = i + 1; j < cpc_desc->num_entries - 2; j++) {
+			struct cpc_register_resource *b = &cpc_desc->cpc_regs[j];
+			const struct cpc_reg *b_gas;
+			u64 b_size;
+
+			if (!CPC_SUPPORTED(b) || b->type != ACPI_TYPE_BUFFER ||
+			    b->cpc_entry.reg.space_id != space_id)
+				continue;
+
+			b_gas = &b->cpc_entry.reg;
+			b_size = cpc_non_mmio_access_size(b);
+			if (!cpc_reg_is_writable(i) && !cpc_reg_is_writable(j))
+				continue;
+			if (a_gas->address < b_gas->address ?
+			    b_gas->address - a_gas->address >= a_size :
+			    a_gas->address - b_gas->address >= b_size)
+				continue;
+
+			pr_err("CPU%d: overlapping writable %s _CPC registers %u and %u\n",
+			       cpc_desc->cpu_id, name, i, j);
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
 static void cpc_mark_rmw_lock_users(struct cpc_desc *cpc_desc)
 {
 	int i;
@@ -819,6 +1001,8 @@ static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit)
 					pcc_ss_data->deadline_us);
 
 	if (likely(!ret)) {
+		/* Order completion status before reading the returned payload. */
+		rmb();
 		pcc_ss_data->platform_owns_pcc = false;
 		if (chk_err_bit && (status & PCC_ERROR_MASK))
 			ret = -EIO;
@@ -1260,6 +1444,7 @@ static int pcc_data_alloc(int pcc_ss_id)
 			ret = -ENOMEM;
 			goto out_unlock;
 		}
+		raw_spin_lock_init(&data->payload_lock);
 		pcc_data[pcc_ss_id] = data;
 	}
 	data->refcount++;
@@ -1335,11 +1520,12 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 	struct device *cpu_dev;
 	acpi_handle handle = pr->handle;
 	unsigned int num_ent, i, cpc_rev;
+	u32 unsupported_regs = 0;
 	int pcc_subspace_id = -1;
 	bool pcc_data_ref = false;
 	bool cpc_present = false;
 	acpi_status status;
-	int ret = -ENODATA;
+	int ret = -EINVAL;
 	int err;
 
 	if (per_cpu(cpc_desc_ptr, pr->id))
@@ -1483,6 +1669,24 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 			 * so extract it only once.
 			 */
 			if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
+				/* These registers have no specified 32-bit upper bound. */
+				bool wide_write = i - 2 == PERF_LIMITED ||
+						  i - 2 == ENABLE ||
+						  i - 2 == AUTO_SEL_ENABLE;
+				bool write_width_supported = gas_t->bit_width == 8 ||
+						     gas_t->bit_width == 16 ||
+						     gas_t->bit_width == 32 ||
+						     gas_t->bit_width == 64;
+
+				if (!gas_t->bit_width || gas_t->bit_width > 64 ||
+				    gas_t->bit_offset || gas_t->bit_width % 8 ||
+				    (cpc_reg_is_writable(i - 2) &&
+				     (!write_width_supported ||
+				      (!wide_write && gas_t->bit_width > 32)))) {
+					unsupported_regs |= BIT(i - 2);
+					continue;
+				}
+
 				if (pcc_subspace_id < 0) {
 					pcc_subspace_id = gas_t->access_width;
 					err = pcc_data_alloc(pcc_subspace_id);
@@ -1494,6 +1698,7 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 				} else if (pcc_subspace_id != gas_t->access_width) {
 					pr_debug("Mismatched PCC ids in _CPC for CPU:%d\n",
 						 pr->id);
+					ret = -EINVAL;
 					goto out_free;
 				}
 			} else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
@@ -1501,21 +1706,11 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 					void __iomem *addr;
 					size_t access_width;
 
-					err = cpc_validate_sysmem_reg(cpc_ptr, gas_t, i - 2);
-					if (err && (i - 2 == DESIRED_PERF ||
-						    i - 2 == OSPM_NOMINAL_PERF)) {
-						const char *name = i - 2 == DESIRED_PERF ?
-								   "Desired Performance" :
-								   "OSPM Nominal Performance";
-
-						pr_warn("CPU%d: disabling inaccessible %s register\n",
-							pr->id, name);
-						cpc_disable_reg(cpc_ptr, i - 2);
-						continue;
-					}
+					err = cpc_validate_sysmem_reg(cpc_ptr, gas_t,
+								      i - 2);
 					if (err) {
-						ret = err;
-						goto out_free;
+						unsupported_regs |= BIT(i - 2);
+						continue;
 					}
 					if (!cpc_is_readable(&cpc_ptr->cpc_regs[i - 2]) &&
 					    !cpc_is_writable(&cpc_ptr->cpc_regs[i - 2]))
@@ -1589,35 +1784,14 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 	}
 	per_cpu(cpu_pcc_subspace_idx, pr->id) = pcc_subspace_id;
 
-	/*
-	 * Performance Limited is required by the specification, but tolerate a
-	 * NULL descriptor used by firmware which cannot report limiting events.
-	 * CPPC control does not depend on this status.
-	 */
-	for (i = 0; i < num_ent - 2; i++) {
-		if (i != DESIRED_PERF && i != PERF_LIMITED &&
-		    !IS_OPTIONAL_CPC_REG(i) &&
-		    !cpc_entry_present(&cpc_ptr->cpc_regs[i])) {
-			pr_debug("CPU:%d lacks mandatory _CPC register %u\n",
-				 pr->id, i);
-			ret = -EINVAL;
-			goto out_free;
-		}
-	}
+	ret = cpc_resolve_unsupported(cpc_ptr, unsupported_regs);
+	if (ret)
+		goto out_free;
+	unsupported_regs = 0;
 
-	/*
-	 * In CPPC v1, DESIRED_PERF is mandatory. In CPPC v2, it is optional
-	 * only when AUTO_SEL_ENABLE is supported.
-	 */
-	if (!cpc_is_writable(&cpc_ptr->cpc_regs[DESIRED_PERF]) &&
-	    (!osc_sb_cppc2_support_acked ||
-	     cpc_ptr->cpc_regs[AUTO_SEL_ENABLE].type != ACPI_TYPE_INTEGER ||
-	     cpc_ptr->cpc_regs[AUTO_SEL_ENABLE].cpc_entry.int_value != 1)) {
-		pr_debug("CPU:%d lacks a writable Desired Performance register\n",
-			 pr->id);
-		ret = -EINVAL;
+	ret = cpc_validate_required_controls(cpc_ptr);
+	if (ret)
 		goto out_free;
-	}
 
 	/*
 	 * Initialize the remaining cpc_regs as unsupported.
@@ -1648,6 +1822,24 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 		if (ret)
 			goto out_free;
 	}
+	if (pcc_subspace_id >= 0) {
+		cpc_validate_pcc_bounds(cpc_ptr, pcc_data[pcc_subspace_id],
+					&unsupported_regs);
+
+		ret = cpc_resolve_unsupported(cpc_ptr, unsupported_regs);
+		if (ret)
+			goto out_free;
+	}
+
+	ret = cpc_validate_non_mmio_overlaps(cpc_ptr,
+					     ACPI_ADR_SPACE_PLATFORM_COMM,
+					     "PCC");
+	if (ret)
+		goto out_free;
+
+	ret = cpc_validate_required_controls(cpc_ptr);
+	if (ret)
+		goto out_free;
 
 	/* Everything looks okay */
 	pr_debug("Parsed CPC struct for CPU: %d\n", pr->id);
@@ -1774,6 +1966,9 @@ int __weak cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)
 static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
 {
 	void __iomem *vaddr = NULL;
+	unsigned long flags;
+	u8 buf[sizeof(*val)];
+	unsigned int i;
 	int size;
 	int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
 	struct cpc_reg *reg = &reg_res->cpc_entry.reg;
@@ -1801,13 +1996,29 @@ static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
 
 		*val = val_u32;
 		return 0;
-	} else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) {
+	} else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
+		if (pcc_ss_id < 0 || !pcc_data[pcc_ss_id])
+			return -ENODEV;
+
 		/*
 		 * For registers in PCC space, the register size is determined
 		 * by the bit width field; the access size is used to indicate
 		 * the PCC subspace id.
 		 */
 		vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
+		size = reg->bit_width / 8;
+		if (!size || size > sizeof(buf) || reg->bit_width % 8)
+			return -EFAULT;
+
+		raw_spin_lock_irqsave(&pcc_data[pcc_ss_id]->payload_lock, flags);
+		memcpy_fromio(buf, vaddr, size);
+		raw_spin_unlock_irqrestore(&pcc_data[pcc_ss_id]->payload_lock,
+					   flags);
+
+		*val = 0;
+		for (i = 0; i < size; i++)
+			*val |= (u64)buf[i] << (i * 8);
+		return 0;
 	}
 	else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
 		vaddr = reg_res->sys_mem_vaddr;
@@ -1857,6 +2068,8 @@ static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
 	struct cpc_reg *reg;
 	struct cpc_desc *cpc_desc;
 	unsigned long flags;
+	u8 buf[sizeof(val)];
+	unsigned int i;
 	bool locked = false;
 
 	if (reg_res->type != ACPI_TYPE_BUFFER)
@@ -1881,13 +2094,30 @@ static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
 		}
 
 		return 0;
-	} else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) {
+	} else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
+		if (pcc_ss_id < 0 || !pcc_data[pcc_ss_id])
+			return -ENODEV;
+
 		/*
 		 * For registers in PCC space, the register size is determined
 		 * by the bit width field; the access size is used to indicate
 		 * the PCC subspace id.
 		 */
 		vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
+		size = reg->bit_width / 8;
+		if (!size || size > sizeof(buf) || reg->bit_width % 8)
+			return -EFAULT;
+
+		for (i = 0; i < size; i++)
+			buf[i] = val >> (i * 8);
+
+		raw_spin_lock_irqsave(&pcc_data[pcc_ss_id]->payload_lock, flags);
+		memcpy_toio(vaddr, buf, size);
+		/* Publish every payload byte before another CPU can ring the doorbell. */
+		wmb();
+		raw_spin_unlock_irqrestore(&pcc_data[pcc_ss_id]->payload_lock,
+					   flags);
+		return 0;
 	}
 	else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
 		vaddr = reg_res->sys_mem_vaddr;
-- 
2.34.1

[PATCH v6 12/15] ACPI: CPPC: Validate SystemIO register layouts

[Christian Loehle]

cpc_read() and cpc_write() access SystemIO registers using the complete GAS
access width. cpc_read() does not extract a partial field, while the writer
does not preserve bits outside one. A partial register can therefore return
the wrong value or clobber adjacent fields on write.

Retain valid read-only fields in 8-, 16-, and 32-bit access units. Extract
them after reading the complete port. Continue to require writable controls
to cover the complete access unit at Bit Offset zero. A partial write would
require a serialized RMW. Keep accepting Access Size zero when Bit Width
supplies one of the supported sizes. Require natural alignment on
architectures which implement port I/O through MMIO and may fault on
unaligned Device-memory accesses. Preserve port layouts on x86; its native
port-I/O instructions support them.

When CONFIG_HAS_IOPORT is disabled, report unavailable port-I/O support and
mark SystemIO layouts inaccessible during probe. Also return -EOPNOTSUPP
explicitly in cpc_read() and cpc_write() so a SystemIO entry can never fall
through and treat its port number as a physical-memory address.

Resolve inaccessible entries using the control-specific policy established
for PCC: optional fields can be disabled, while mandatory or semantically
required controls fail probe. Reject overlapping logical port ranges when
either entry is writable; read-only overlaps remain allowed.

Partial writable forms are permitted by ACPI, but never worked with the
existing whole-width Linux writer. Implementing them would require
field-aware I/O and appropriate RMW serialization.

Fixes: a2c8f92bea5f ("ACPI: CPPC: Implement support for SystemIO registers")
Signed-off-by: Christian Loehle <christian.loehle@arm.com>
---
 drivers/acpi/cppc_acpi.c | 68 ++++++++++++++++++++++++++++------------
 1 file changed, 48 insertions(+), 20 deletions(-)

diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
index d81ac477d184..beeae0a983b8 100644
--- a/drivers/acpi/cppc_acpi.c
+++ b/drivers/acpi/cppc_acpi.c
@@ -237,7 +237,6 @@ static bool cpc_integer_entry_valid(unsigned int reg_idx, u64 value)
  */
 #define NUM_RETRIES 500ULL
 
-#define OVER_16BTS_MASK ~0xFFFFULL
 #define CPC_GENERIC_REGISTER_DESCRIPTOR 0x82
 #define CPC_GENERIC_REGISTER_LENGTH (sizeof(struct cpc_reg) - 3)
 
@@ -1734,21 +1733,41 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 					cpc_ptr->cpc_regs[i - 2].sys_mem_vaddr = addr;
 				}
 			} else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
-				if (gas_t->access_width < 1 || gas_t->access_width > 3) {
-					/*
-					 * 1 = 8-bit, 2 = 16-bit, and 3 = 32-bit.
-					 * SystemIO doesn't implement 64-bit
-					 * registers.
-					 */
-					pr_debug("Invalid access width %d for SystemIO register in _CPC\n",
-						 gas_t->access_width);
-					goto out_free;
+				u64 access_size;
+				const char *reason = "uses unsupported SystemIO geometry";
+				unsigned int access_width;
+				bool unsupported;
+
+				access_width = cpc_reg_access_width(gas_t);
+				unsupported = !IS_ENABLED(CONFIG_HAS_IOPORT);
+				if (unsupported)
+					reason = "requires unavailable SystemIO support";
+				else
+					unsupported = access_width != 8 &&
+					      access_width != 16 &&
+					      access_width != 32;
+				if (!unsupported) {
+					access_size = access_width / 8;
+					unsupported = !gas_t->bit_width ||
+						gas_t->bit_width > access_width ||
+						gas_t->bit_offset >= access_width ||
+						gas_t->bit_width > access_width -
+									   gas_t->bit_offset;
 				}
-				if (gas_t->address & OVER_16BTS_MASK) {
-					/* SystemIO registers use 16-bit integer addresses */
-					pr_debug("Invalid IO port %llu for SystemIO register in _CPC\n",
-						 gas_t->address);
-					goto out_free;
+				if (!unsupported) {
+					unsupported = (cpc_reg_is_writable(i - 2) &&
+						(gas_t->bit_offset ||
+						 gas_t->bit_width != access_width)) ||
+						!cpc_reg_access_aligned(gas_t,
+									access_size) ||
+						gas_t->address >
+						U16_MAX - (access_size - 1);
+				}
+				if (unsupported) {
+					pr_debug("CPU%d: _CPC register %u %s\n",
+						 pr->id, i - 2, reason);
+					unsupported_regs |= BIT(i - 2);
+					continue;
 				}
 				if (!osc_cpc_flexible_adr_space_confirmed) {
 					pr_debug("Flexible address space capability not supported\n");
@@ -1836,6 +1855,11 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 					     "PCC");
 	if (ret)
 		goto out_free;
+	ret = cpc_validate_non_mmio_overlaps(cpc_ptr,
+					     ACPI_ADR_SPACE_SYSTEM_IO,
+					     "SystemIO");
+	if (ret)
+		goto out_free;
 
 	ret = cpc_validate_required_controls(cpc_ptr);
 	if (ret)
@@ -1981,11 +2005,13 @@ static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
 	*val = 0;
 	size = GET_BIT_WIDTH(reg);
 
-	if (IS_ENABLED(CONFIG_HAS_IOPORT) &&
-	    reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
+	if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
 		u32 val_u32;
 		acpi_status status;
 
+		if (!IS_ENABLED(CONFIG_HAS_IOPORT))
+			return -EOPNOTSUPP;
+
 		status = acpi_os_read_port((acpi_io_address)reg->address,
 					   &val_u32, size);
 		if (ACPI_FAILURE(status)) {
@@ -1994,7 +2020,7 @@ static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
 			return -EFAULT;
 		}
 
-		*val = val_u32;
+		*val = MASK_VAL_READ(reg, val_u32);
 		return 0;
 	} else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
 		if (pcc_ss_id < 0 || !pcc_data[pcc_ss_id])
@@ -2081,10 +2107,12 @@ static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
 
 	size = GET_BIT_WIDTH(reg);
 
-	if (IS_ENABLED(CONFIG_HAS_IOPORT) &&
-	    reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
+	if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
 		acpi_status status;
 
+		if (!IS_ENABLED(CONFIG_HAS_IOPORT))
+			return -EOPNOTSUPP;
+
 		status = acpi_os_write_port((acpi_io_address)reg->address,
 					    (u32)val, size);
 		if (ACPI_FAILURE(status)) {
-- 
2.34.1

[PATCH v6 13/15] ACPI: CPPC: Validate PCC overlaps across processors

[Christian Loehle]

PCC shared-memory offsets are physical within a subspace, but the existing
overlap check stops at one _CPC package. Two processors can therefore pass
probe with writable ranges which overlap in the same PCC subspace.

This is unsafe in the performance path, where CPUs may stage requests
concurrently while holding the shared side of pcc_lock. Partially
overlapping stores can construct a payload which belongs to neither request
before a doorbell submits it.

Index retained PCC byte ranges by subspace and physical interval. Permit
read-only overlap and exact aliases of the same logical CPPC entry. The
per-subspace payload lock serializes exact writable aliases, including
multi-byte fields copied with byte-oriented I/O. Reject every other overlap
involving a writable entry.

With that cross-processor protection in place, enable zero-offset,
byte-multiple writable PCC fields. Ordinary performance controls remain at
most 32 bits, while Performance Limited, CPPC Enable, and Autonomous
Selection Enable may use byte-multiple fields through 64 bits.

The interval tree keeps registration proportional to real overlaps rather
than to the number of processors. Remove entries when processor teardown
unpublishes its CPC descriptor, including every probe-failure path after
registration.

Fixes: 85b1407bf6d2 ("ACPI / CPPC: Make CPPC ACPI driver aware of PCC subspace IDs")
Signed-off-by: Christian Loehle <christian.loehle@arm.com>
---
 drivers/acpi/cppc_acpi.c | 193 ++++++++++++++++++++++++++++++++++++---
 include/acpi/cppc_acpi.h |   2 +
 2 files changed, 180 insertions(+), 15 deletions(-)

diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
index beeae0a983b8..cc749a487373 100644
--- a/drivers/acpi/cppc_acpi.c
+++ b/drivers/acpi/cppc_acpi.c
@@ -113,6 +113,18 @@ struct cpc_sysmem_node {
 	bool registered;
 };
 
+struct cpc_non_mmio_node {
+	struct rb_node rb;
+	u64 subtree_last;
+	u64 start;
+	u64 last;
+	struct cpc_desc *desc;
+	unsigned int reg_idx;
+	u8 space_id;
+	u8 pcc_ss_id;
+	bool registered;
+};
+
 #define CPC_SYSMEM_START(node) ((node)->start)
 #define CPC_SYSMEM_LAST(node) ((node)->last)
 
@@ -123,6 +135,16 @@ INTERVAL_TREE_DEFINE(struct cpc_sysmem_node, rb, u64, subtree_last,
 static struct rb_root_cached cpc_sysmem_tree = RB_ROOT_CACHED;
 static DEFINE_MUTEX(cpc_sysmem_lock);
 
+#define CPC_NON_MMIO_START(node) ((node)->start)
+#define CPC_NON_MMIO_LAST(node) ((node)->last)
+
+INTERVAL_TREE_DEFINE(struct cpc_non_mmio_node, rb, u64, subtree_last,
+		     CPC_NON_MMIO_START, CPC_NON_MMIO_LAST, static inline,
+		     cpc_non_mmio_itree)
+
+static struct rb_root_cached cpc_pcc_trees[MAX_PCC_SUBSPACES];
+static DEFINE_MUTEX(cpc_non_mmio_lock);
+
 static struct cpc_sysmem_node *cpc_sysmem_first(u64 start, u64 last)
 {
 	return cpc_sysmem_itree_iter_first(&cpc_sysmem_tree, start, last);
@@ -284,15 +306,9 @@ show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time);
 
 static bool cpc_pcc_write_supported(const struct cpc_register_resource *reg)
 {
-	switch (GET_BIT_WIDTH(&reg->cpc_entry.reg)) {
-	case 8:
-	case 16:
-	case 32:
-	case 64:
-		return true;
-	default:
-		return false;
-	}
+	unsigned int width = reg->cpc_entry.reg.bit_width;
+
+	return width && width <= 32 && !(width % 8);
 }
 
 /* Shift and apply the mask for CPC reads/writes */
@@ -629,6 +645,150 @@ static int cpc_validate_non_mmio_overlaps(struct cpc_desc *cpc_desc,
 	return 0;
 }
 
+static struct rb_root_cached *cpc_non_mmio_tree(u8 space_id, u8 pcc_ss_id)
+{
+	if (space_id == ACPI_ADR_SPACE_PLATFORM_COMM)
+		return &cpc_pcc_trees[pcc_ss_id];
+	return NULL;
+}
+
+static int cpc_validate_non_mmio_pair(const struct cpc_non_mmio_node *a,
+				      const struct cpc_non_mmio_node *b)
+{
+	bool a_writable = cpc_reg_is_writable(a->reg_idx);
+	bool b_writable = cpc_reg_is_writable(b->reg_idx);
+	const char *name;
+
+	if (!a_writable && !b_writable)
+		return 0;
+
+	if (a->reg_idx == b->reg_idx && a->start == b->start &&
+	    a->last == b->last)
+		return 0;
+
+	name = "PCC";
+	pr_err("CPU%d: %s _CPC register %u conflicts with CPU%d register %u\n",
+	       a->desc->cpu_id, name, a->reg_idx, b->desc->cpu_id,
+	       b->reg_idx);
+	return -EINVAL;
+}
+
+static void cpc_unregister_non_mmio_desc_locked(struct cpc_desc *cpc_desc)
+{
+	unsigned int i;
+
+	if (!cpc_desc->non_mmio_nodes)
+		return;
+
+	for (i = 0; i < cpc_desc->num_entries - 2; i++) {
+		struct cpc_non_mmio_node *node = &cpc_desc->non_mmio_nodes[i];
+		struct rb_root_cached *tree;
+
+		if (!node->registered)
+			continue;
+
+		tree = cpc_non_mmio_tree(node->space_id, node->pcc_ss_id);
+		cpc_non_mmio_itree_remove(node, tree);
+	}
+
+	kfree(cpc_desc->non_mmio_nodes);
+	cpc_desc->non_mmio_nodes = NULL;
+}
+
+static int cpc_register_non_mmio_desc(struct cpc_desc *cpc_desc,
+				      int pcc_ss_id)
+{
+	unsigned int nr_regs = cpc_desc->num_entries - 2;
+	unsigned int i;
+	int ret = 0;
+	bool found = false;
+
+	for (i = 0; i < nr_regs; i++) {
+		struct cpc_register_resource *reg = &cpc_desc->cpc_regs[i];
+		u8 space_id;
+
+		if (!CPC_SUPPORTED(reg) || reg->type != ACPI_TYPE_BUFFER)
+			continue;
+		space_id = reg->cpc_entry.reg.space_id;
+		if (space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
+			found = true;
+			break;
+		}
+	}
+	if (!found)
+		return 0;
+
+	cpc_desc->non_mmio_nodes = kcalloc(nr_regs,
+					   sizeof(*cpc_desc->non_mmio_nodes),
+					   GFP_KERNEL);
+	if (!cpc_desc->non_mmio_nodes)
+		return -ENOMEM;
+
+	mutex_lock(&cpc_non_mmio_lock);
+
+	for (i = 0; i < nr_regs; i++) {
+		struct cpc_register_resource *reg = &cpc_desc->cpc_regs[i];
+		struct cpc_non_mmio_node *match, *node;
+		struct rb_root_cached *tree;
+		u8 space_id;
+		u64 size;
+
+		if (!CPC_SUPPORTED(reg) || reg->type != ACPI_TYPE_BUFFER)
+			continue;
+
+		space_id = reg->cpc_entry.reg.space_id;
+		if (space_id != ACPI_ADR_SPACE_PLATFORM_COMM)
+			continue;
+
+		if (pcc_ss_id < 0) {
+			ret = -EINVAL;
+			goto out_unregister;
+		}
+
+		node = &cpc_desc->non_mmio_nodes[i];
+		size = cpc_non_mmio_access_size(reg);
+		node->start = reg->cpc_entry.reg.address;
+		node->last = node->start + size - 1;
+		node->desc = cpc_desc;
+		node->reg_idx = i;
+		node->space_id = space_id;
+		node->pcc_ss_id = pcc_ss_id;
+		tree = cpc_non_mmio_tree(space_id, node->pcc_ss_id);
+
+		match = cpc_non_mmio_itree_iter_first(tree, node->start,
+						      node->last);
+		while (match) {
+			ret = cpc_validate_non_mmio_pair(node, match);
+			if (ret)
+				goto out_unregister;
+
+			match = cpc_non_mmio_itree_iter_next(match, node->start,
+							     node->last);
+		}
+
+		cpc_non_mmio_itree_insert(node, tree);
+		node->registered = true;
+	}
+
+	mutex_unlock(&cpc_non_mmio_lock);
+	return 0;
+
+out_unregister:
+	cpc_unregister_non_mmio_desc_locked(cpc_desc);
+	mutex_unlock(&cpc_non_mmio_lock);
+	return ret;
+}
+
+static void cpc_unregister_non_mmio_desc(struct cpc_desc *cpc_desc)
+{
+	if (!cpc_desc->non_mmio_nodes)
+		return;
+
+	mutex_lock(&cpc_non_mmio_lock);
+	cpc_unregister_non_mmio_desc_locked(cpc_desc);
+	mutex_unlock(&cpc_non_mmio_lock);
+}
+
 static void cpc_mark_rmw_lock_users(struct cpc_desc *cpc_desc)
 {
 	int i;
@@ -958,6 +1118,7 @@ static void cppc_free_desc(struct cpc_desc *cpc_ptr)
 {
 	unsigned int i;
 
+	cpc_unregister_non_mmio_desc(cpc_ptr);
 	cpc_unregister_sysmem_desc(cpc_ptr);
 
 	for (i = 2; i < cpc_ptr->num_entries; i++) {
@@ -1672,16 +1833,12 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 				bool wide_write = i - 2 == PERF_LIMITED ||
 						  i - 2 == ENABLE ||
 						  i - 2 == AUTO_SEL_ENABLE;
-				bool write_width_supported = gas_t->bit_width == 8 ||
-						     gas_t->bit_width == 16 ||
-						     gas_t->bit_width == 32 ||
-						     gas_t->bit_width == 64;
 
 				if (!gas_t->bit_width || gas_t->bit_width > 64 ||
 				    gas_t->bit_offset || gas_t->bit_width % 8 ||
 				    (cpc_reg_is_writable(i - 2) &&
-				     (!write_width_supported ||
-				      (!wide_write && gas_t->bit_width > 32)))) {
+				     !wide_write &&
+				     gas_t->bit_width > 32)) {
 					unsupported_regs |= BIT(i - 2);
 					continue;
 				}
@@ -1865,6 +2022,10 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 	if (ret)
 		goto out_free;
 
+	ret = cpc_register_non_mmio_desc(cpc_ptr, pcc_subspace_id);
+	if (ret)
+		goto out_free;
+
 	/* Everything looks okay */
 	pr_debug("Parsed CPC struct for CPU: %d\n", pr->id);
 
@@ -1882,6 +2043,7 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 			"acpi_cppc");
 	if (ret) {
 		per_cpu(cpc_desc_ptr, pr->id) = NULL;
+		cpc_unregister_non_mmio_desc(cpc_ptr);
 		cpc_unregister_sysmem_desc(cpc_ptr);
 		kobject_put(&cpc_ptr->kobj);
 		goto out_pcc_put;
@@ -1926,6 +2088,7 @@ void acpi_cppc_processor_exit(struct acpi_processor *pr)
 	pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, pr->id);
 	per_cpu(cpc_desc_ptr, pr->id) = NULL;
 	kobject_del(&cpc_ptr->kobj);
+	cpc_unregister_non_mmio_desc(cpc_ptr);
 	cpc_unregister_sysmem_desc(cpc_ptr);
 
 	pcc_data_put(pcc_ss_id);
diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h
index 4e5f59bc95f8..be22504eddce 100644
--- a/include/acpi/cppc_acpi.h
+++ b/include/acpi/cppc_acpi.h
@@ -80,6 +80,7 @@ struct cpc_register_resource {
 };
 
 struct cpc_sysmem_node;
+struct cpc_non_mmio_node;
 
 /* Container to hold the CPC details for each CPU */
 struct cpc_desc {
@@ -93,6 +94,7 @@ struct cpc_desc {
 	struct cpc_register_resource cpc_regs[MAX_CPC_REG_ENT];
 	struct acpi_psd_package domain_info;
 	struct cpc_sysmem_node *sysmem_nodes;
+	struct cpc_non_mmio_node *non_mmio_nodes;
 	struct kobject kobj;
 };
 
-- 
2.34.1

[PATCH v6 14/15] ACPI: CPPC: Validate SystemIO overlaps across processors

[Christian Loehle]

System I/O port space is global, but the overlap check only compares
registers within one _CPC package.  Whole-width accesses from different
processors can therefore target partially overlapping port ranges and
clobber each other.

Extend the physical interval registry to SystemIO.  Permit read-only
overlap and exact full-width aliases of the same logical CPPC entry.
Reject every other cross-processor overlap involving a writable entry.

Fixes: a2c8f92bea5f ("ACPI: CPPC: Implement support for SystemIO registers")
Signed-off-by: Christian Loehle <christian.loehle@arm.com>
---
 drivers/acpi/cppc_acpi.c | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
index cc749a487373..25bccd4cfb34 100644
--- a/drivers/acpi/cppc_acpi.c
+++ b/drivers/acpi/cppc_acpi.c
@@ -143,6 +143,7 @@ INTERVAL_TREE_DEFINE(struct cpc_non_mmio_node, rb, u64, subtree_last,
 		     cpc_non_mmio_itree)
 
 static struct rb_root_cached cpc_pcc_trees[MAX_PCC_SUBSPACES];
+static struct rb_root_cached cpc_sysio_tree = RB_ROOT_CACHED;
 static DEFINE_MUTEX(cpc_non_mmio_lock);
 
 static struct cpc_sysmem_node *cpc_sysmem_first(u64 start, u64 last)
@@ -649,6 +650,8 @@ static struct rb_root_cached *cpc_non_mmio_tree(u8 space_id, u8 pcc_ss_id)
 {
 	if (space_id == ACPI_ADR_SPACE_PLATFORM_COMM)
 		return &cpc_pcc_trees[pcc_ss_id];
+	if (space_id == ACPI_ADR_SPACE_SYSTEM_IO)
+		return &cpc_sysio_tree;
 	return NULL;
 }
 
@@ -666,7 +669,8 @@ static int cpc_validate_non_mmio_pair(const struct cpc_non_mmio_node *a,
 	    a->last == b->last)
 		return 0;
 
-	name = "PCC";
+	name = a->space_id == ACPI_ADR_SPACE_PLATFORM_COMM ?
+	       "PCC" : "SystemIO";
 	pr_err("CPU%d: %s _CPC register %u conflicts with CPU%d register %u\n",
 	       a->desc->cpu_id, name, a->reg_idx, b->desc->cpu_id,
 	       b->reg_idx);
@@ -710,7 +714,8 @@ static int cpc_register_non_mmio_desc(struct cpc_desc *cpc_desc,
 		if (!CPC_SUPPORTED(reg) || reg->type != ACPI_TYPE_BUFFER)
 			continue;
 		space_id = reg->cpc_entry.reg.space_id;
-		if (space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
+		if (space_id == ACPI_ADR_SPACE_PLATFORM_COMM ||
+		    space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
 			found = true;
 			break;
 		}
@@ -737,10 +742,11 @@ static int cpc_register_non_mmio_desc(struct cpc_desc *cpc_desc,
 			continue;
 
 		space_id = reg->cpc_entry.reg.space_id;
-		if (space_id != ACPI_ADR_SPACE_PLATFORM_COMM)
+		if (space_id != ACPI_ADR_SPACE_PLATFORM_COMM &&
+		    space_id != ACPI_ADR_SPACE_SYSTEM_IO)
 			continue;
 
-		if (pcc_ss_id < 0) {
+		if (space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id < 0) {
 			ret = -EINVAL;
 			goto out_unregister;
 		}
@@ -752,7 +758,8 @@ static int cpc_register_non_mmio_desc(struct cpc_desc *cpc_desc,
 		node->desc = cpc_desc;
 		node->reg_idx = i;
 		node->space_id = space_id;
-		node->pcc_ss_id = pcc_ss_id;
+		node->pcc_ss_id = space_id == ACPI_ADR_SPACE_PLATFORM_COMM ?
+				      pcc_ss_id : 0;
 		tree = cpc_non_mmio_tree(space_id, node->pcc_ss_id);
 
 		match = cpc_non_mmio_itree_iter_first(tree, node->start,
-- 
2.34.1

[PATCH v6 15/15] ACPI: CPPC: Clear Performance Limited without a stale read

[Christian Loehle]

The Performance Limited status bits are sticky and write-zero-to-clear.
ACPI 6.6 Section 8.4.6.1.3.2 also requires both entities to use interlocked
accesses.

cppc_set_perf_limited() currently reads the register, computes a new value,
and writes it in a separate transaction. If the platform reports another
excursion between those transactions, the stale write can clear that new
event.

Write zero to the requested bits and one to the other defined status bits
directly. Keep reserved bits zero as required for hardware status registers
by ACPI 6.6 Section 4.6.1. This removes the stale read window.

A partial SystemMemory field would still make the generic writer perform a
read-modify-write to preserve the containing access unit. The
per-descriptor spinlock cannot interlock that RMW with platform updates, so
reject clears of such a field. Keep the descriptor mapped and readable,
because reading the containing access unit once and extracting the field
does not require RMW.

Classify a field as a writer during overlap validation only when its _CPC
semantics permit writes and its validated resource remains writable. This
allows partial Performance Limited fields whose clear path was disabled to
share an access unit with other read-only fields, while still rejecting an
actual writer in that access unit.

Also reject another writable SystemMemory field sharing Performance
Limited's access unit. Its RMW could similarly replay stale status bits,
and an OSPM lock cannot serialize against the platform.

Also reject 64-bit SystemMemory descriptions on 32-bit kernels, where
generic readq()/writeq() may be split into two 32-bit operations and cannot
provide the required portable interlocked access. A naturally aligned
full-width QWord remains supported on 64-bit kernels, where the
architecture provides a native 64-bit MMIO accessor.

Retain any inaccessible Performance Limited descriptor whose conservative
physical range is still locatable, while marking both reads and writes
unsupported. This includes a QWord on a 32-bit kernel. Skip its mapping and
the flexible-address-space capability gate, because Linux will issue no
access, without hiding the asynchronous status range from
neighbouring-writer validation. Both the interval registry and pairwise
overlap test use the larger of the access unit and logical field span, so a
malformed field extending beyond its nominal access unit remains covered.

Performance Limited status is not required for CPPC control. If firmware
describes it without even a locatable physical range, disable that status
register instead of rejecting the processor's otherwise usable _CPC
package. Report reads as unsupported rather than returning a synthetic
zero, and emit a single warning for each nonfatal fallback.

Fixes: 13c45a26635f ("ACPI: CPPC: add APIs and sysfs interface for perf_limited")
Reported-by: Sashiko <sashiko-bot@kernel.org>
Link: https://sashiko.dev/#/patchset/20260807111303.1062391-1-christian.loehle%40arm.com
Signed-off-by: Christian Loehle <christian.loehle@arm.com>
---
 drivers/acpi/cppc_acpi.c | 76 +++++++++++++++++++++++++++++-----------
 1 file changed, 56 insertions(+), 20 deletions(-)

diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
index 25bccd4cfb34..a07440ed7f80 100644
--- a/drivers/acpi/cppc_acpi.c
+++ b/drivers/acpi/cppc_acpi.c
@@ -443,6 +443,22 @@ static int cpc_validate_sysmem_reg(struct cpc_desc *cpc_desc,
 	if (!cpc_reg_access_aligned(gas, access_size))
 		goto invalid;
 
+	if (reg_idx == PERF_LIMITED) {
+		if (access_width == 64 && !IS_ENABLED(CONFIG_64BIT)) {
+			pr_warn("CPU%d: Performance Limited register cannot be accessed atomically; keeping its range reserved\n",
+				cpc_desc->cpu_id);
+			cpc_desc->cpc_regs[reg_idx].cpc_entry.read_unsupported = true;
+			cpc_desc->cpc_regs[reg_idx].cpc_entry.write_unsupported = true;
+			return 0;
+		}
+
+		if (gas->bit_offset || gas->bit_width != access_width) {
+			pr_warn("CPU%d: Performance Limited register cannot be cleared safely; keeping it readable\n",
+				cpc_desc->cpu_id);
+			cpc_desc->cpc_regs[reg_idx].cpc_entry.write_unsupported = true;
+		}
+	}
+
 	return 0;
 
 invalid:
@@ -452,8 +468,9 @@ static int cpc_validate_sysmem_reg(struct cpc_desc *cpc_desc,
 		access_size = access_width / 8;
 	if (gas->bit_width)
 		access_size = max(access_size, cpc_sysmem_field_size(gas));
-	if (cpc_reg_is_write_only(cpc_desc, reg_idx) && gas->address &&
-	    access_size && gas->address <= U64_MAX - (access_size - 1)) {
+	if ((cpc_reg_is_write_only(cpc_desc, reg_idx) ||
+	     reg_idx == PERF_LIMITED) && gas->address && access_size &&
+	    gas->address <= U64_MAX - (access_size - 1)) {
 		struct cpc_register_resource *reg = &cpc_desc->cpc_regs[reg_idx];
 
 		pr_warn("CPU%d: _CPC v%d register %u is inaccessible; keeping its range reserved\n",
@@ -502,6 +519,14 @@ static int cpc_resolve_unsupported(struct cpc_desc *cpc_desc,
 		if (!(unsupported & BIT(i)))
 			continue;
 
+		/* CPPC control does not depend on Performance Limited status. */
+		if (i == PERF_LIMITED) {
+			pr_warn("CPU%d: ignoring inaccessible Performance Limited register\n",
+				cpc_desc->cpu_id);
+			cpc_disable_reg(cpc_desc, i);
+			continue;
+		}
+
 		if (i == DESIRED_PERF && cpc_immutable_autonomous(cpc_desc)) {
 			pr_warn("CPU%d: ignoring inaccessible Desired Performance register in autonomous mode\n",
 				cpc_desc->cpu_id);
@@ -803,7 +828,8 @@ static void cpc_mark_rmw_lock_users(struct cpc_desc *cpc_desc)
 	for (i = 0; i < cpc_desc->num_entries - 2; i++) {
 		struct cpc_register_resource *reg = &cpc_desc->cpc_regs[i];
 
-		if (CPC_SUPPORTED(reg) && CPC_IN_SYSTEM_MEMORY(reg))
+		if (CPC_SUPPORTED(reg) && CPC_IN_SYSTEM_MEMORY(reg) &&
+		    cpc_is_writable(reg))
 			reg->cpc_entry.use_rmw_lock =
 				cpc_sysmem_reg_needs_rmw(reg);
 	}
@@ -905,6 +931,7 @@ static int cpc_validate_sysmem_pair(const struct cpc_desc *a_desc,
 	const struct cpc_register_resource *b = &b_desc->cpc_regs[b_idx];
 	bool a_writable, b_writable;
 
+	/* The overlap helper includes each descriptor's conservative claim. */
 	if (!CPC_SUPPORTED(a) || !CPC_IN_SYSTEM_MEMORY(a) ||
 	    !CPC_SUPPORTED(b) || !CPC_IN_SYSTEM_MEMORY(b) ||
 	    !cpc_sysmem_access_units_overlap(a, b))
@@ -933,6 +960,15 @@ static int cpc_validate_sysmem_pair(const struct cpc_desc *a_desc,
 		goto conflict;
 	}
 
+	/*
+	 * The platform may set Performance Limited asynchronously.  A write to
+	 * another field in the same access unit could write back stale status
+	 * bits, which an OSPM lock cannot prevent.
+	 */
+	if ((a_idx == PERF_LIMITED && b_writable) ||
+	    (b_idx == PERF_LIMITED && a_writable))
+		goto conflict;
+
 	/* A full-width writable register owns its complete access unit. */
 	if ((a_writable && !cpc_sysmem_reg_needs_rmw(a) &&
 	     cpc_sysmem_full_width_conflicts(a, b)) ||
@@ -2167,6 +2203,9 @@ static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
 	int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
 	struct cpc_reg *reg = &reg_res->cpc_entry.reg;
 
+	if (!cpc_is_readable(reg_res))
+		return -EOPNOTSUPP;
+
 	if (reg_res->type == ACPI_TYPE_INTEGER) {
 		*val = reg_res->cpc_entry.int_value;
 		return 0;
@@ -2268,13 +2307,10 @@ static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
 	unsigned int i;
 	bool locked = false;
 
-	if (reg_res->type != ACPI_TYPE_BUFFER)
+	if (!cpc_is_writable(reg_res))
 		return -EOPNOTSUPP;
 
 	reg = &reg_res->cpc_entry.reg;
-	if (IS_NULL_REG(reg))
-		return -EOPNOTSUPP;
-
 	size = GET_BIT_WIDTH(reg);
 
 	if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
@@ -2438,9 +2474,13 @@ static int cppc_get_reg_val(int cpu, enum cppc_regs reg_idx, u64 *val)
 
 	reg = &cpc_desc->cpc_regs[reg_idx];
 
-	/* Desired may be absent for immutable autonomous selection. */
+	/*
+	 * Desired and Performance Limited may be disabled despite not being
+	 * generally optional.
+	 */
 	if ((reg->type == ACPI_TYPE_INTEGER &&
-	     (IS_OPTIONAL_CPC_REG(reg_idx) || reg_idx == DESIRED_PERF) &&
+	     (IS_OPTIONAL_CPC_REG(reg_idx) || reg_idx == DESIRED_PERF ||
+	      reg_idx == PERF_LIMITED) &&
 	     !reg->cpc_entry.int_value) || (reg->type != ACPI_TYPE_INTEGER &&
 	     IS_NULL_REG(&reg->cpc_entry.reg))) {
 		pr_debug("CPC register is not supported\n");
@@ -3468,9 +3508,6 @@ EXPORT_SYMBOL_GPL(cppc_get_perf_limited);
  */
 int cppc_set_perf_limited(int cpu, u64 bits_to_clear)
 {
-	u64 current_val, new_val;
-	int ret;
-
 	/* Only bits 0 and 1 are valid */
 	if (bits_to_clear & ~CPPC_PERF_LIMITED_MASK)
 		return -EINVAL;
@@ -3478,14 +3515,13 @@ int cppc_set_perf_limited(int cpu, u64 bits_to_clear)
 	if (!bits_to_clear)
 		return 0;
 
-	ret = cppc_get_perf_limited(cpu, &current_val);
-	if (ret)
-		return ret;
-
-	/* Clear the specified bits */
-	new_val = current_val & ~bits_to_clear;
-
-	return cppc_set_reg_val(cpu, PERF_LIMITED, new_val);
+	/*
+	 * Performance Limited is write-zero-to-clear.  Write one to the other
+	 * defined sticky bits so a concurrently reported event is not cleared
+	 * using a value obtained by an earlier, separate read transaction.
+	 */
+	return cppc_set_reg_val(cpu, PERF_LIMITED,
+				CPPC_PERF_LIMITED_MASK & ~bits_to_clear);
 }
 EXPORT_SYMBOL_GPL(cppc_set_perf_limited);
 
-- 
2.34.1

Re: [PATCH v6 02/15] ACPI: CPPC: Validate _CPC entry and control semantics

[Christian Loehle]

On 8/30/26 12:56, Christian Loehle wrote:
> Writable _CPC controls are Register descriptors encoded as Buffer objects.
> Integer entries represent fixed values or unsupported optional registers;
> Autonomous Selection Integer 1 is the special immutable form which enables
> operation without Desired Performance.
> 
> The parser accepts arbitrary object types and cpc_write() assumes that its
> argument contains a GAS. Malformed firmware can therefore make it interpret
> an Integer union member as a register.
> 
> Validate the portion of each encoding consumed by the driver: bound Integer
> DWORD forms to 32 bits, and require Buffer entries to start with a complete
> Generic Register descriptor with the expected header. Continue tolerating
> Integer 0 for an absent optional register and retain type checks in
> cpc_write() as defense in depth. Reject an attempt to disable immutable
> Autonomous Selection instead of silently applying only the EPP part of the
> request.
> 
> Capability registers are read into u64 temporaries but exposed through u32
> fields. Reject values above U32_MAX instead of allowing them to be
> truncated. In particular, a truncated Highest Performance value can become
> a zero divisor in the performance-to-frequency conversion. Enforce the
> required ordering from Highest through Nominal, Lowest Nonlinear, and
> Lowest Performance, and constrain a present Guaranteed Performance to the
> inclusive Lowest-to-Nominal range. Also reject reversed frequency anchors
> and unequal frequency anchors with identical performance anchors. Those
> invalid tuples otherwise make affine-conversion differences wrap or divide
> by zero.
> 
> Check mandatory object presence separately from the Integer-zero convention
> for absent optional fields. ACPI does not reserve zero in the abstract
> Lowest Performance scale, so accept a present Lowest Performance DWORD of
> zero when distinct frequency anchors provide a usable nonzero physical
> minimum. Retain the old rejection when that mapping is unavailable and the
> fallback conversion would expose a 0 kHz cpufreq endpoint.
> 
> Minimum Performance also defines zero as a real no-limit value, but the
> exported cppc_set_perf() interface historically used zero to omit a bound.
> Add explicit validity flags so callers can request zero without changing
> that legacy convention. Populate the flags when reading the controls and
> mark the bounds supplied by amd-pstate explicitly.
> 
> Performance Limited is listed as a required Buffer, but the interface does
> not depend on it to control performance and the specification permits a
> platform with no limiting indication to always report zero. Preserve
> the compatibility with firmware that represents that case using a NULL
> register descriptor instead of disabling CPPC entirely.
> 
> Emit an error when a present _CPC package fails parsing or initialization
> so such firmware and resource failures no longer silently suppress cpufreq.
> Initialize malformed-package failures to -EINVAL and preserve specific
> allocation, mapping, and unsupported-access errors in that diagnostic.
> 
> Fixes: 337aadff8e45 ("ACPI: Introduce CPU performance controls using CPPC")
> Reported-by: Sashiko <sashiko-bot@kernel.org>
> Link: https://sashiko.dev/#/patchset/20260724134251.1632824-1-christian.loehle%40arm.com
> Signed-off-by: Christian Loehle <christian.loehle@arm.com>
> ---
>  drivers/acpi/cppc_acpi.c     | 172 ++++++++++++++++++++++++++++++-----
>  drivers/cpufreq/amd-pstate.c |  12 ++-
>  include/acpi/cppc_acpi.h     |   2 +
>  3 files changed, 159 insertions(+), 27 deletions(-)
> 
> diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
> index 3b8cdf88e31d..6f3ffa4a1845 100644
> --- a/drivers/acpi/cppc_acpi.c
> +++ b/drivers/acpi/cppc_acpi.c
> @@ -129,6 +129,21 @@ static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
>  				!!(cpc)->cpc_entry.int_value :		\
>  				!IS_NULL_REG(&(cpc)->cpc_entry.reg))
>  
> +static bool cpc_is_writable(const struct cpc_register_resource *cpc)
> +{
> +	return cpc->type == ACPI_TYPE_BUFFER &&
> +	       !IS_NULL_REG(&cpc->cpc_entry.reg);
> +}
> +
> +static bool cpc_entry_present(const struct cpc_register_resource *cpc)
> +{
> +	if (cpc->type == ACPI_TYPE_INTEGER)
> +		return true;
> +
> +	return cpc->type == ACPI_TYPE_BUFFER &&
> +	       !IS_NULL_REG(&cpc->cpc_entry.reg);
> +}
> +
>  /*
>   * Each bit indicates the optionality of the register in per-cpu
>   * cpc_regs[] with the corresponding index. 0 means mandatory and 1
> @@ -142,6 +157,29 @@ static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
>   */
>  #define IS_OPTIONAL_CPC_REG(reg_idx) (REG_OPTIONAL & (1U << (reg_idx)))
>  
> +static bool cpc_integer_entry_valid(unsigned int reg_idx, u64 value)
> +{
> +	switch (reg_idx) {
> +	case HIGHEST_PERF:
> +	case NOMINAL_PERF:
> +	case LOW_NON_LINEAR_PERF:
> +	case LOWEST_PERF:
> +	case CTR_WRAP_TIME:
> +	case REFERENCE_PERF:
> +	case LOWEST_FREQ:
> +	case NOMINAL_FREQ:
> +		return value <= U32_MAX;


Sashiko:
"Does this incorrectly restrict the counter wraparound time to 32 bits?
The ACPI specification allows firmware to provide a 64-bit QWord integer
for the Counter Wraparound Time. The cppc_perf_fb_ctrs structure already
models this as a 64-bit value internally
If firmware provides a valid 64-bit integer exceeding U32_MAX for this
register, cpc_integer_entry_valid() will return false and completely abort
CPPC initialization for the CPU. Can we remove this restriction for
CTR_WRAP_TIME?"
This is true. ACPI spec 6.6 and 6.5 (Table 8.23) describe it as 
Integer (DWORD) or Buffer
The 64-bit internal representation is only for the case of firmware
providing it as Buffer.

> +	case AUTO_SEL_ENABLE:
> +		return value <= 1;
> +	case DESIRED_PERF:
> +		/* Validated against Autonomous Selection after parsing. */
> +		return value == 0;
> +	default:
> +		/* Tolerate the customary Integer 0 for an absent option. */
> +		return value == 0 && IS_OPTIONAL_CPC_REG(reg_idx);
> +	}
> +}
> +
Sashiko:
"Does this incorrectly restrict the counter wraparound time to 32 bits?
The ACPI specification allows firmware to provide a 64-bit QWord integer
for the Counter Wraparound Time. The cppc_perf_fb_ctrs structure already
models this as a 64-bit value internally.
If firmware provides a valid 64-bit integer exceeding U32_MAX for this
register, cpc_integer_entry_valid() will return false and completely abort
CPPC initialization for the CPU. Can we remove this restriction for
CTR_WRAP_TIME?"
GUARANTEED_PERF and TIME_WINDOW: both are Buffer-only Register descriptors.
Nonzero Integer encodings are invalid and Integer 0 is tolerated because
the previous parser allowed it too. I don't know of any platform describing
this myself.

>  /*
>   * Arbitrary Retries in case the remote processor is slow to respond
>   * to PCC commands. Keeping it high enough to cover emulators where
> @@ -150,6 +188,8 @@ static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
>  #define NUM_RETRIES 500ULL
>  
>  #define OVER_16BTS_MASK ~0xFFFFULL
> +#define CPC_GENERIC_REGISTER_DESCRIPTOR 0x82
> +#define CPC_GENERIC_REGISTER_LENGTH (sizeof(struct cpc_reg) - 3)
>  
>  #define define_one_cppc_ro(_name)		\
>  static struct kobj_attribute _name =		\
> @@ -773,8 +813,10 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
>  	acpi_handle handle = pr->handle;
>  	unsigned int num_ent, i, cpc_rev;
>  	int pcc_subspace_id = -1;
> +	bool cpc_present = false;
>  	acpi_status status;
>  	int ret = -ENODATA;
> +	int err;
>  
>  	if (!osc_sb_cppc2_support_acked) {
>  		pr_debug("CPPC v2 _OSC not acked\n");
> @@ -791,6 +833,8 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
>  		ret = -ENODEV;
>  		goto out_buf_free;
>  	}
> +	cpc_present = true;
> +	ret = -EINVAL;
>  
>  	out_obj = (union acpi_object *) output.pointer;
>  	if (out_obj->package.count < 2) {
> @@ -871,11 +915,32 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
>  		cpc_obj = &out_obj->package.elements[i];
>  
>  		if (cpc_obj->type == ACPI_TYPE_INTEGER)	{
> -			cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER;
> -			cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value;
> +			if (!cpc_integer_entry_valid(i - 2,
> +						     cpc_obj->integer.value)) {
> +				pr_debug("Invalid Integer _CPC register %u for CPU:%d\n",
> +					 i - 2, pr->id);
> +				ret = -EINVAL;
> +				goto out_free;
> +			}
> +			cpc_ptr->cpc_regs[i - 2].type = ACPI_TYPE_INTEGER;
> +			cpc_ptr->cpc_regs[i - 2].cpc_entry.int_value = cpc_obj->integer.value;
>  		} else if (cpc_obj->type == ACPI_TYPE_BUFFER) {
> +			if (cpc_obj->buffer.length < sizeof(*gas_t)) {
> +				pr_debug("Invalid register descriptor for CPU:%d\n",
> +					 pr->id);
> +				ret = -EINVAL;
> +				goto out_free;
> +			}
> +
>  			gas_t = (struct cpc_reg *)
>  				cpc_obj->buffer.pointer;
> +			if (gas_t->descriptor != CPC_GENERIC_REGISTER_DESCRIPTOR ||
> +			    gas_t->length != CPC_GENERIC_REGISTER_LENGTH) {
> +				pr_debug("Invalid register resource for CPU:%d\n",
> +					 pr->id);
> +				ret = -EINVAL;
> +				goto out_free;
> +			}
>  
>  			/*
>  			 * The PCC Subspace index is encoded inside
> @@ -886,8 +951,11 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
>  			if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
>  				if (pcc_subspace_id < 0) {
>  					pcc_subspace_id = gas_t->access_width;
> -					if (pcc_data_alloc(pcc_subspace_id))
> +					err = pcc_data_alloc(pcc_subspace_id);
> +					if (err) {
> +						ret = err;
>  						goto out_free;
> +					}
>  				} else if (pcc_subspace_id != gas_t->access_width) {
>  					pr_debug("Mismatched PCC ids in _CPC for CPU:%d\n",
>  						 pr->id);
> @@ -900,14 +968,18 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
>  
>  					if (!osc_cpc_flexible_adr_space_confirmed) {
>  						pr_debug("Flexible address space capability not supported\n");
> +						ret = -EOPNOTSUPP;
>  						if (!cpc_supported_by_cpu())
>  							goto out_free;
> +						ret = -EINVAL;
>  					}
>  
>  					access_width = GET_BIT_WIDTH(gas_t) / 8;
>  					addr = ioremap(gas_t->address, access_width);
> -					if (!addr)
> +					if (!addr) {
> +						ret = -ENOMEM;
>  						goto out_free;
> +					}
>  					cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr;
>  				}
>  			} else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
> @@ -929,14 +1001,17 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
>  				}
>  				if (!osc_cpc_flexible_adr_space_confirmed) {
>  					pr_debug("Flexible address space capability not supported\n");
> +					ret = -EOPNOTSUPP;
>  					if (!cpc_supported_by_cpu())
>  						goto out_free;
> +					ret = -EINVAL;
>  				}
>  			} else {
>  				if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) {
>  					/* Support only PCC, SystemMemory, SystemIO, and FFH type regs. */
>  					pr_debug("Unsupported register type (%d) in _CPC\n",
>  						 gas_t->space_id);
> +					ret = -EOPNOTSUPP;
>  					goto out_free;
>  				}
>  			}
> @@ -961,15 +1036,35 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
>  	}
>  	per_cpu(cpu_pcc_subspace_idx, pr->id) = pcc_subspace_id;
>  
> +	/*
> +	 * Performance Limited is required by the specification, but tolerate a
> +	 * NULL descriptor used by firmware which cannot report limiting events.
> +	 * CPPC control does not depend on this status.
> +	 */
> +	for (i = 0; i < num_ent - 2; i++) {
> +		if (i != DESIRED_PERF && i != PERF_LIMITED &&
> +		    !IS_OPTIONAL_CPC_REG(i) &&
> +		    !cpc_entry_present(&cpc_ptr->cpc_regs[i])) {
> +			pr_debug("CPU:%d lacks mandatory _CPC register %u\n",
> +				 pr->id, i);
> +			ret = -EINVAL;
> +			goto out_free;
> +		}
> +	}
> +
>  	/*
>  	 * In CPPC v1, DESIRED_PERF is mandatory. In CPPC v2, it is optional
>  	 * only when AUTO_SEL_ENABLE is supported.
>  	 */
> -	if (!CPC_SUPPORTED(&cpc_ptr->cpc_regs[DESIRED_PERF]) &&
> +	if (!cpc_is_writable(&cpc_ptr->cpc_regs[DESIRED_PERF]) &&
>  	    (!osc_sb_cppc2_support_acked ||
> -	     !CPC_SUPPORTED(&cpc_ptr->cpc_regs[AUTO_SEL_ENABLE])))
> -		pr_warn("Desired perf. register is mandatory if CPPC v2 is not supported "
> -			"or autonomous selection is disabled\n");
> +	     cpc_ptr->cpc_regs[AUTO_SEL_ENABLE].type != ACPI_TYPE_INTEGER ||
> +	     cpc_ptr->cpc_regs[AUTO_SEL_ENABLE].cpc_entry.int_value != 1)) {
> +		pr_debug("CPU:%d lacks a writable Desired Performance register\n",
> +			 pr->id);
> +		ret = -EINVAL;
> +		goto out_free;
> +	}
>  
>  	/*
>  	 * Initialize the remaining cpc_regs as unsupported.
> @@ -1037,6 +1132,8 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
>  	kfree(cpc_ptr);
>  
>  out_buf_free:
> +	if (cpc_present)
> +		pr_err("CPU%d: failed to initialize _CPC: %d\n", pr->id, ret);
>  	kfree(output.pointer);
>  	return ret;
>  }
> @@ -1217,11 +1314,18 @@ static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
>  	u64 prev_val;
>  	void __iomem *vaddr = NULL;
>  	int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
> -	struct cpc_reg *reg = &reg_res->cpc_entry.reg;
> +	struct cpc_reg *reg;
>  	struct cpc_desc *cpc_desc;
>  	unsigned long flags;
>  	bool locked = false;
>  
> +	if (reg_res->type != ACPI_TYPE_BUFFER)
> +		return -EOPNOTSUPP;
> +
> +	reg = &reg_res->cpc_entry.reg;
> +	if (IS_NULL_REG(reg))
> +		return -EOPNOTSUPP;
> +
>  	size = GET_BIT_WIDTH(reg);
>  
>  	if (IS_ENABLED(CONFIG_HAS_IOPORT) &&
> @@ -1364,7 +1468,9 @@ static int cppc_get_reg_val(int cpu, enum cppc_regs reg_idx, u64 *val)
>  
>  	reg = &cpc_desc->cpc_regs[reg_idx];
>  
> -	if ((reg->type == ACPI_TYPE_INTEGER && IS_OPTIONAL_CPC_REG(reg_idx) &&
> +	/* Desired may be absent for immutable autonomous selection. */
> +	if ((reg->type == ACPI_TYPE_INTEGER &&
> +	     (IS_OPTIONAL_CPC_REG(reg_idx) || reg_idx == DESIRED_PERF) &&
>  	     !reg->cpc_entry.int_value) || (reg->type != ACPI_TYPE_INTEGER &&
>  	     IS_NULL_REG(&reg->cpc_entry.reg))) {
>  		pr_debug("CPC register is not supported\n");
> @@ -1415,7 +1521,7 @@ static int cppc_set_reg_val(int cpu, enum cppc_regs reg_idx, u64 val)
>  	reg = &cpc_desc->cpc_regs[reg_idx];
>  
>  	/* if a register is writeable, it must be a buffer and not null */
> -	if ((reg->type != ACPI_TYPE_BUFFER) || IS_NULL_REG(&reg->cpc_entry.reg)) {
> +	if (!cpc_is_writable(reg)) {
>  		pr_debug("CPC register is not supported\n");
>  		return -EOPNOTSUPP;
>  	}
> @@ -1505,7 +1611,7 @@ int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
>  	struct cpc_register_resource *highest_reg, *lowest_reg,
>  		*lowest_non_linear_reg, *nominal_reg, *reference_reg,
>  		*guaranteed_reg, *low_freq_reg = NULL, *nom_freq_reg = NULL;
> -	u64 high, low, guaranteed, nom, ref, min_nonlinear,
> +	u64 high, low, guaranteed = 0, nom, ref, min_nonlinear,
>  	    low_f = 0, nom_f = 0;
>  	int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
>  	struct cppc_pcc_data *pcc_ss_data = NULL;
> @@ -1588,7 +1694,12 @@ int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
>  		goto out_err;
>  	perf_caps->lowest_nonlinear_perf = min_nonlinear;
>  
> -	if (!high || !low || !nom || !ref || !min_nonlinear) {
> +	if (!high || !nom || !ref || !min_nonlinear ||
> +	    high > U32_MAX || low > U32_MAX || guaranteed > U32_MAX ||
> +	    nom > U32_MAX || ref > U32_MAX || min_nonlinear > U32_MAX ||
> +	    high < nom || nom < min_nonlinear || min_nonlinear < low ||
> +	    (CPC_SUPPORTED(guaranteed_reg) &&
> +	     (guaranteed < low || guaranteed > nom))) {
>  		ret = -EFAULT;
>  		goto out_err;
>  	}
> @@ -1605,6 +1716,19 @@ int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
>  		if (ret)
>  			goto out_err;
>  	}
> +	/*
> +	 * Require ordered anchors and a nonzero slope when frequencies differ.
> +	 * A zero Lowest Performance needs that affine mapping to produce a
> +	 * nonzero physical minimum frequency.
> +	 */
> +	if (low_f > U32_MAX || nom_f > U32_MAX ||
> +	    (!low && (!low_f || !nom_f || low_f == nom_f)) ||
> +	    (low_f && nom_f &&
> +	     (nom_f < low_f || nom < low ||
> +	      (nom_f != low_f && nom == low)))) {
> +		ret = -EFAULT;
> +		goto out_err;
> +	}
>  
>  	perf_caps->lowest_freq = low_f;
>  	perf_caps->nominal_freq = nom_f;
> @@ -1779,6 +1903,9 @@ int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable)
>  
>  	auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
>  	epp_set_reg = &cpc_desc->cpc_regs[ENERGY_PERF];
> +	if (!enable && auto_sel_reg->type == ACPI_TYPE_INTEGER &&
> +	    auto_sel_reg->cpc_entry.int_value == 1)
> +		return -EOPNOTSUPP;
>  
>  	epp_ffh_sysmem = CPC_SUPPORTED(epp_set_reg) &&
>  		(CPC_IN_FFH(epp_set_reg) || CPC_IN_SYSTEM_MEMORY(epp_set_reg));
> @@ -1791,13 +1918,13 @@ int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable)
>  			return -ENODEV;
>  		}
>  
> -		if (CPC_SUPPORTED(auto_sel_reg)) {
> +		if (cpc_is_writable(auto_sel_reg)) {
>  			ret = cpc_write(cpu, auto_sel_reg, enable);
>  			if (ret)
>  				return ret;
>  		}
>  
> -		if (CPC_SUPPORTED(epp_set_reg)) {
> +		if (cpc_is_writable(epp_set_reg)) {
>  			ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf);
>  			if (ret)
>  				return ret;
> @@ -1996,6 +2123,8 @@ int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
>  	max_perf_reg = &cpc_desc->cpc_regs[MAX_PERF];
>  	energy_perf_reg = &cpc_desc->cpc_regs[ENERGY_PERF];
>  	auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
> +	perf_ctrls->max_perf_valid = false;
> +	perf_ctrls->min_perf_valid = false;
>  
>  	/* Are any of the regs PCC ?*/
>  	if (CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg) ||
> @@ -2020,6 +2149,7 @@ int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
>  		ret = cpc_read(cpu, max_perf_reg, &max);
>  		if (ret)
>  			goto out_err;
> +		perf_ctrls->max_perf_valid = true;
>  	}
>  	perf_ctrls->max_perf = max;
>  
> @@ -2027,6 +2157,7 @@ int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
>  		ret = cpc_read(cpu, min_perf_reg, &min);
>  		if (ret)
>  			goto out_err;
> +		perf_ctrls->min_perf_valid = true;
>  	}
>  	perf_ctrls->min_perf = min;
>  
> @@ -2113,14 +2244,11 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
>  	if (CPC_SUPPORTED(desired_reg))
>  		cpc_write(cpu, desired_reg, perf_ctrls->desired_perf);
>  
> -	/*
> -	 * Only write if min_perf and max_perf not zero. Some drivers pass zero
> -	 * value to min and max perf, but they don't mean to set the zero value,
> -	 * they just don't want to write to those registers.
> -	 */
> -	if (perf_ctrls->min_perf && CPC_SUPPORTED(min_perf_reg))
> +	if (CPC_SUPPORTED(min_perf_reg) &&
> +	    (perf_ctrls->min_perf || perf_ctrls->min_perf_valid))
>  		cpc_write(cpu, min_perf_reg, perf_ctrls->min_perf);
> -	if (perf_ctrls->max_perf && CPC_SUPPORTED(max_perf_reg))
> +	if (CPC_SUPPORTED(max_perf_reg) &&
> +	    (perf_ctrls->max_perf || perf_ctrls->max_perf_valid))
>  		cpc_write(cpu, max_perf_reg, perf_ctrls->max_perf);
>  
>  	if (regs_in_pcc)
> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
> index d4ff8b228f86..63f0ca5f19b3 100644
> --- a/drivers/cpufreq/amd-pstate.c
> +++ b/drivers/cpufreq/amd-pstate.c
> @@ -544,7 +544,13 @@ static int shmem_update_perf(struct cpufreq_policy *policy, u8 min_perf,
>  			     u8 des_perf, u8 max_perf, u8 epp, bool fast_switch)
>  {
>  	struct amd_cpudata *cpudata = policy->driver_data;
> -	struct cppc_perf_ctrls perf_ctrls;
> +	struct cppc_perf_ctrls perf_ctrls = {
> +		.max_perf = max_perf,
> +		.min_perf = min_perf,
> +		.desired_perf = des_perf,
> +		.max_perf_valid = true,
> +		.min_perf_valid = true,
> +	};
>  	u64 value, prev;
>  	int ret;
>  
> @@ -577,10 +583,6 @@ static int shmem_update_perf(struct cpufreq_policy *policy, u8 min_perf,
>  	if (value == prev)
>  		return 0;
>  
> -	perf_ctrls.max_perf = max_perf;
> -	perf_ctrls.min_perf = min_perf;
> -	perf_ctrls.desired_perf = des_perf;
> -
>  	ret = cppc_set_perf(cpudata->cpu, &perf_ctrls);
>  	if (ret)
>  		return ret;
> diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h
> index 94a6277edab2..5dcbe65c5ddc 100644
> --- a/include/acpi/cppc_acpi.h
> +++ b/include/acpi/cppc_acpi.h
> @@ -141,6 +141,8 @@ struct cppc_perf_ctrls {
>  	u32 desired_perf;
>  	u32 energy_perf;
>  	bool auto_sel;
> +	bool max_perf_valid;
> +	bool min_perf_valid;
>  };
>  
>  struct cppc_perf_fb_ctrs {

Re: [PATCH v6 0/15] ACPI: CPPC: Fix register access and lifetime bugs

[Christian Loehle]

On 8/30/26 12:56, Christian Loehle wrote:
> This series fixes correctness and robustness issues found while reviewing
> the CPPC control path. They affect malformed _CPC handling, error
> propagation, PCC ownership and cleanup, CPC object lifetime, register field
> access, cross-processor aliases, and Performance Limited clearing.
> 
> Series structure
> ================
> 
> Patches 1-8 are deliberately small, independently useful fixes. They
> validate the _CPC encoding consumed by cppc-acpi, propagate control-write
> errors, serialize PCC payload updates, correct 64-bit field masks, and fix
> descriptor and PCC lifetime handling.
> 
> Patches 9-15 are the register-layout hardening portion. Geometry validation
> is more substantial because safe RMW and alias handling depend on the
> physical access unit, not merely on a logical _CPC entry or _PSD domain.
> These patches normalize and validate each supported address space before
> building probe-only physical interval registries. Keeping this work in the
> same posting gives the complete safety boundary and a single base for
> review, while each transport and bug retains its own Fixes provenance.
> Feel free to treat the two parts as independent series, I didn't split it
> because they're all technically fixes and to get Sashiko review for the
> whole lot.
> 
> No interval lookup is added to the scheduler hot path. Full-width
> SystemMemory writes remain lockless. RMW locking remains necessary only for
> a partial field, where we must preserve the other bits in its access
> unit. The existing per-descriptor raw lock continues to cover disjoint
> partial fields within one _CPC package; probe rejects cross-descriptor
> layouts that it cannot protect.
> 
> Parsing and control semantics
> =============================
> 
> The parser now validates the package header before indexing it, bounds the
> BYTE and DWORD Integer forms before conversion, and validates the Generic
> Register descriptor consumed by cppc-acpi. NumEntries may not exceed the
> AML package count, but additional trailing package elements are ignored
> because doing so is safe and preserves compatibility with padded firmware.
> The parser likewise tolerates trailing ResourceTemplate data instead of
> imposing a new EndTag compatibility requirement.
> 
> Capability values read from registers must also fit the u32 fields exposed
> to CPPC callers. Reject wider values instead of truncating them, which could
> otherwise turn Highest Performance into a zero divisor.
> 
> Writable controls must be Buffer-encoded registers. Minimum and Maximum
> Performance are checked as the pair required by ACPI 6.6 Sections
> 8.4.6.1.2.1 and 8.4.6.1.2.2. Object presence is kept separate from the
> Integer-zero convention for absent optional fields, so Lowest Performance
> may retain the valid abstract value zero.
> 
> Performance Limited is one deliberate compatibility exception. ACPI lists
> it as required, but permits a platform with no limiting indication to
> always return zero, and deployed firmware represents that case with a NULL
> descriptor. CPPC control does not depend on this status register, so we
> continue to accept that encoding. A present _CPC package which otherwise
> fails parsing or initialization now emits an error instead of silently
> preventing cpufreq registration.
> 
> Compound performance and EPP updates propagate errors and perform every
> fallible non-PCC write before modifying the PCC payload. Updates across
> address spaces cannot be atomic, but a known non-PCC failure can no longer
> commit only the PCC portion or leave an unsent value for a later command.
> All requested PCC fields are validated before the first payload store, so
> a malformed later field cannot leave an earlier value for a subsequent
> doorbell to commit. Writable Minimum and Maximum Performance controls are
> programmed even when their requested value is zero, because zero can be a
> valid abstract performance level rather than an omitted update.
> 
> SystemMemory locking and support boundary
> =========================================
> 
> A partial SystemMemory field requires RMW to preserve the rest of its
> access unit. Commit 60949b7b8054 ("ACPI: CPPC: Fix MASK_VAL() usage") used
> a per-_CPC lock and noted that a global lock would be needed if physical
> registers were shared between packages.
> 
> ACPI does not make _PSD a physical-register ownership boundary. Rather than
> put a global raw lock or lookup into the scheduler path, this series makes
> the cheaper per-descriptor model's assumptions enforceable at probe.
> 
> Supported SystemMemory layouts are:
> 
>   - naturally aligned 8-, 16-, 32-, and 64-bit access units;
>   - lockless full-width controls;
>   - read-only aliases;
>   - exact writable aliases, including partial aliases of the same logical
>     field, when the complete access is one aligned native transaction;
>   - disjoint partial writers within one descriptor, serialized by its
>     rmw_lock, when neither must preserve another write-only field; and
>   - a partial writer sharing an access unit with a disjoint read-only
>     field, except Performance Limited.
> 
> Probe rejects overlapping logical fields involving a writer, another field
> inside a full-width writable access unit, non-identical cross-descriptor
> partial writers, writers sharing Performance Limited's access unit, writers
> which would preserve a write-only neighbour, unaligned accesses, and exact
> writable 64-bit aliases on 32-bit kernels. These layouts were not safely
> supported by the old per-descriptor lock or generic writeq(); rejecting them
> turns possible corruption into a visible probe failure rather than removing
> working support.
> 
> PCC access and locking
> ======================
> 
> The PCC protocol requires OSPM to acquire the subspace before changing its
> command or payload. Single-register and EPP updates now hold pcc_lock
> across ownership acquisition, payload staging, and command submission.
> Concurrent Phase-I callers intentionally store the same true value to the
> pending-command flag under the shared side of pcc_lock, so that store uses
> WRITE_ONCE(); transitions back to false remain exclusively locked.
> 
> ACPI 6.6's implementation example places a mandatory 32-bit Delivered
> Performance Counter at unaligned PCC offset 0x116. Performance controls may
> also use byte-multiple widths such as 24 bits. PCC therefore uses
> byte-oriented I/O with explicit little-endian encoding for zero-offset,
> byte-multiple fields from 8 through 64 bits. A short per-subspace payload
> lock protects concurrent aliased copies made under the shared side of
> pcc_lock; it does not replace the protocol ownership lock.
> 
> Bit-level PCC fields require RMW and remain unsupported. An unsupported
> optional field is marked absent, but a present inaccessible CPPC Enable
> fails probe because OSPM must write it before using CPPC. Thus the
> ACPI-legal one-bit CPPC Enable used by the specification example is a
> documented kernel limitation. The old accessor could not program it
> correctly either, so an explicit error is safer than silently proceeding
> without enabling CPPC.
> 
> Every retained PCC field is bounds checked against the shared-memory
> region. A subspace-keyed interval registry permits read-only overlap and
> exact same-control aliases while rejecting every other writable overlap
> across processors. A lifecycle mutex serializes allocation, reference
> updates, first channel setup, and teardown of each shared PCC object.
> 
> SystemIO support boundary
> =========================
> 
> SystemIO supports Bit Offset zero, naturally aligned, full 8-, 16-, or
> 32-bit accesses ending at or below port 0xffff, including legacy Access
> Size zero when Bit Width supplies the size. Partial fields never worked
> because the driver neither shifted them nor preserved adjacent bits, so
> they now fail visibly instead of being misprogrammed.
> 
> On kernels without CONFIG_HAS_IOPORT, SystemIO entries are rejected or
> disabled according to the affected control's semantics. Runtime accessors
> also return -EOPNOTSUPP rather than treating an I/O port as a
> physical-memory address. A global port interval registry rejects
> cross-processor writable overlap.
> 
> Write-only and Performance Limited controls
> ===========================================
> 
> Between _CPC revisions 3 and 4, Desired Performance changed from
> Read/Write to Write, and revision 4 added write-only OSPM Nominal
> Performance. ACPI 6.6 Section 4.6.3 says reads from write-only positions
> are undefined. Explicit reads of both controls are rejected. Partial
> SystemMemory fields remain writable because RMW replaces every bit of the
> field and therefore does not propagate its undefined readback, provided no
> other writer shares the access unit and would preserve that field.
> 
> Performance Limited is sticky, write-zero-to-clear, and requires
> interlocked accesses under ACPI 6.6 Section 8.4.6.1.3.2. The old separate
> read and write could clear a new event reported between transactions. The
> clear path now writes zero only to requested status bits and one to the
> other defined bits. Partial SystemMemory forms remain readable but cannot
> be cleared because a spinlock cannot interlock an enclosing RMW with
> platform updates. Probe also rejects another writable field sharing its
> access unit. QWord forms cannot be used on 32-bit kernels, where the MMIO
> accessor may be split into two 32-bit operations; naturally aligned,
> full-width QWords remain supported on 64-bit kernels. Since CPPC control
> does not depend on Performance Limited status, an unreadable description
> marks status access unsupported instead of rejecting the processor's
> otherwise usable _CPC. Its physical range remains visible to overlap
> validation so another writer cannot evade the status-register conflict.
> 
> Lifetime and cleanup
> ====================
> 
> CPC descriptors are released through their kobject callback, keeping their
> storage and mappings alive for outstanding sysfs references. Every PCC
> allocation, reference, and acquired channel is unwound on probe failure,
> and the per-CPU PCC index is initialized before every early return. PCC
> allocation uses a separate temporary result, so its success cannot turn a
> later parse failure into a successful probe return. Shared PCC allocation,
> reference updates, channel initialization, and teardown are serialized. A
> repeated processor start reuses an already published descriptor instead of
> resetting its PCC index and leaking or detaching the existing state.
> 
> Changes since v5
> ================
> 
>   - Kept Lowest Performance zero valid while starting the arm64 artificial
>     energy model at its first positive capacity step, and made every
>     present _CPC initialization failure emit the common CPU/errno
>     diagnostic.
>   - Checked completion of a preceding PCC command before writing the direct
>     half of a mixed-address-space performance request.
>   - Coalesced exact SystemMemory aliases behind one interval-tree node and
>     promoted a live alias on teardown, avoiding quadratic probe work on
>     large systems. Also skipped registry allocations for descriptors with
>     no entries in the corresponding address space.
>   - Stopped treating unused Performance Reduction Tolerance and Time Window
>     entries as writers, and retained disjoint fields when a narrower
>     full-width write cannot touch the overlapping read-only access unit.
>   - Preserved inaccessible write-only controls in physical overlap
>     validation, and tested whether the other writer's access unit actually
>     covers the write-only field before rejecting an asymmetric layout.
>   - Restricted writable PCC controls to their DWORD width, coherently
>     disabled an inaccessible Minimum/Maximum pair, and ordered PCC payload
>     bytes against completion and doorbell accesses.
>   - Classified a SystemMemory field as writable during overlap validation
>     only when both its _CPC semantics and validated access permit writes.
>     This keeps partial Performance Limited status fields shareable after
>     their unsafe clear path has been disabled, while still rejecting an
>     actual writer sharing the status access unit.
>   - Preserved an inaccessible 64-bit Performance Limited physical range on
>     32-bit kernels while marking reads and writes unsupported, so a
>     neighbouring writer remains detectable without mapping a split access.
> 
> Changes since v4
> ================
> 
>   - Validated all requested PCC control widths before the first payload
>     store, preventing a later malformed field from leaving an earlier
>     staged value for a subsequent doorbell to commit.
>   - Marked the intentional concurrent same-value pending-command store with
>     WRITE_ONCE().
>   - Serialized shared PCC allocation, reference updates, channel setup, and
>     teardown, and published channel readiness only after initializing its
>     lock and wait queue.
>   - Rejected another writable field sharing a SystemMemory access unit with
>     a write-only field, because its RMW would preserve and replay undefined
>     readback.
>   - Rejected capability values which do not fit the u32 interface instead
>     of allowing truncation and a possible zero divisor.
>   - Programmed writable Minimum and Maximum Performance controls when the
>     requested value is zero, which is valid when Lowest Performance is zero.
>   - Reused an existing CPC descriptor on a repeated processor start instead
>     of resetting its PCC index before a retry could fail.
> 
> Changes since v3
> ================
> 
>   - Allowed partial SystemMemory Desired and OSPM Nominal controls when RMW
>     discards their undefined readback, supporting NVIDIA's separate 9-bit
>     controls in _CPC revision 4.
>   - Reported an unavailable Desired Performance control as unsupported from
>     the common getter instead of returning a synthetic zero.
>   - Required natural alignment for SystemIO access units, preventing faults
>     on architectures which implement port I/O through Device-memory MMIO.
>   - Kept partial Performance Limited fields readable but not clearable,
>     rejected another writer sharing their access unit, reported fully
>     inaccessible forms as unsupported instead of returning a synthetic
>     zero, and consolidated each nonfatal fallback into a single warning.
> 
> Changes since v2
> ================
> 
>   - Relaxed the exact NumEntries/package-count match to tolerate safe
>     trailing package elements while still rejecting any count that could
>     cause an out-of-bounds walk.
>   - Made patch 10 independently preserve immutable-autonomous setups whose
>     inaccessible Desired Performance register requires RMW, rather than
>     relying on patch 11 to restore that exception.
> 
> Sashiko v2 review not addressed
> ===============================
> 
>   - Kept Guaranteed Performance Buffer-only. The suggestion was to accept a
>     nonzero Integer, but ACPI 6.6 Table 8.23 permits only a Buffer for this
>     entry.
> 
> Sashiko v4/v5 review requiring no code change
> =============================================
> 
>   - Kept nonzero Integers restricted to entries whose object type includes
>     Integer in ACPI 6.6 Table 8.23. Guaranteed Performance and Energy
>     Performance Preference are Buffer-only registers.
>   - Kept Desired Performance optional only when OSPM advertises CPPC2 and
>     Autonomous Selection Enable is encoded as Integer 1. ACPI 6.6 Section
>     8.4.6.1.2.3 explicitly requires that immutable encoding; a writable
>     Buffer does not qualify.
> 
> Deferred follow-up work
> =======================
> 
> Sashiko also identified a broader pre-existing lifetime question which this
> series does not attempt to solve. In-kernel accessors read the per-CPU
> cpc_desc_ptr without acquiring a reference, while processor teardown can
> unpublish and eventually release the descriptor and its PCC data. The
> kobject change here fixes the concrete sysfs lifetime bug, but a NULL
> pcc_data check would not protect a caller which already holds a stale
> pointer. Closing this properly requires defining the kernel accessor
> lifetime contract and then using CPU-hotplug serialization / safe
> referencing across all callers, therefore will be handled by a follow-up.
> 
> ACPI-legal bit-level PCC and SystemIO fields also remain unsupported. In
> particular, the ACPI example's one-bit PCC CPPC Enable register cannot be
> implemented by the old whole-value accessors. Supporting these
> descriptions requires transport-specific field extraction and an RMW
> operation which obeys PCC ownership or safely preserves adjacent SystemIO
> bits, just accepting the descriptors would silently program the wrong
> value. Therefore continue to disable optional inaccessible fields where
> safe and reject a present inaccessible CPPC Enable control.
> Full support, if even needed, belongs in a separate follow-up.
> 
> The review additionally suggested validating the complete AML
> ResourceTemplate, including its EndTag. We currently validate the Register
> descriptor we consume and tolerate trailing firmware data. I don't really
> see the point of ever doing this, but definitely not in this series,
> where I'm trying to guarantee that no reasonably working platform is
> regressing.
> 
> Patches 1, 2, 4-7, and 9 address findings reported by Sashiko while
> reviewing:
> 
>   https://sashiko.dev/#/patchset/20260724134251.1632824-1-christian.loehle%40arm.com
> 
> Patches 3, 5, 6, 9, 10, and 15 address findings from the follow-up review:
> 
>   https://sashiko.dev/#/patchset/20260807111303.1062391-1-christian.loehle%40arm.com
> 
> Patches 1 and 10 address findings from the v2 review:
> 
>   https://sashiko.dev/#/patchset/20260808082644.1251332-1-christian.loehle%40arm.com
> 
> Christian Loehle (15):
>   ACPI: CPPC: Validate the _CPC package header
>   ACPI: CPPC: Validate _CPC entry and control semantics
>   ACPI: CPPC: Propagate performance-control write errors
>   ACPI: CPPC: Use 64-bit masks for register fields
>   ACPI: CPPC: Serialize PCC single-register payload updates
>   ACPI: CPPC: Serialize PCC EPP payload updates
>   ACPI: CPPC: Release CPC descriptors through kobject
>   ACPI: CPPC: Release PCC data after probe failures
>   ACPI: CPPC: Reject unsafe cross-CPU SystemMemory RMW
>   ACPI: CPPC: Reject direct reads of write-only controls
>   ACPI: CPPC: Validate and access PCC register layouts
>   ACPI: CPPC: Validate SystemIO register layouts
>   ACPI: CPPC: Validate PCC overlaps across processors
>   ACPI: CPPC: Validate SystemIO overlaps across processors
>   ACPI: CPPC: Clear Performance Limited without a stale read
> 
>  drivers/acpi/cppc_acpi.c     | 1807 ++++++++++++++++++++++++++++++++++++------
>  drivers/cpufreq/amd-pstate.c |   12 +-
>  include/acpi/cppc_acpi.h     |   11 +-
>  3 files changed, 1569 insertions(+), 261 deletions(-)
> 
> base-commit: 08dbfad3f5040f5bdb6c529da20d6d4e81fefd72
> --
> 2.34.1

+CC AMD maintainers

Re: [PATCH v6 0/15] ACPI: CPPC: Fix register access and lifetime bugs

[Mario Limonciello]

On 9/1/26 01:24, Christian Loehle wrote:
> On 8/30/26 12:56, Christian Loehle wrote:
>> This series fixes correctness and robustness issues found while reviewing
>> the CPPC control path. They affect malformed _CPC handling, error
>> propagation, PCC ownership and cleanup, CPC object lifetime, register field
>> access, cross-processor aliases, and Performance Limited clearing.
>>
>> Series structure
>> ================
>>
>> Patches 1-8 are deliberately small, independently useful fixes. They
>> validate the _CPC encoding consumed by cppc-acpi, propagate control-write
>> errors, serialize PCC payload updates, correct 64-bit field masks, and fix
>> descriptor and PCC lifetime handling.
>>
>> Patches 9-15 are the register-layout hardening portion. Geometry validation
>> is more substantial because safe RMW and alias handling depend on the
>> physical access unit, not merely on a logical _CPC entry or _PSD domain.
>> These patches normalize and validate each supported address space before
>> building probe-only physical interval registries. Keeping this work in the
>> same posting gives the complete safety boundary and a single base for
>> review, while each transport and bug retains its own Fixes provenance.
>> Feel free to treat the two parts as independent series, I didn't split it
>> because they're all technically fixes and to get Sashiko review for the
>> whole lot.
>>
>> No interval lookup is added to the scheduler hot path. Full-width
>> SystemMemory writes remain lockless. RMW locking remains necessary only for
>> a partial field, where we must preserve the other bits in its access
>> unit. The existing per-descriptor raw lock continues to cover disjoint
>> partial fields within one _CPC package; probe rejects cross-descriptor
>> layouts that it cannot protect.
>>
>> Parsing and control semantics
>> =============================
>>
>> The parser now validates the package header before indexing it, bounds the
>> BYTE and DWORD Integer forms before conversion, and validates the Generic
>> Register descriptor consumed by cppc-acpi. NumEntries may not exceed the
>> AML package count, but additional trailing package elements are ignored
>> because doing so is safe and preserves compatibility with padded firmware.
>> The parser likewise tolerates trailing ResourceTemplate data instead of
>> imposing a new EndTag compatibility requirement.
>>
>> Capability values read from registers must also fit the u32 fields exposed
>> to CPPC callers. Reject wider values instead of truncating them, which could
>> otherwise turn Highest Performance into a zero divisor.
>>
>> Writable controls must be Buffer-encoded registers. Minimum and Maximum
>> Performance are checked as the pair required by ACPI 6.6 Sections
>> 8.4.6.1.2.1 and 8.4.6.1.2.2. Object presence is kept separate from the
>> Integer-zero convention for absent optional fields, so Lowest Performance
>> may retain the valid abstract value zero.
>>
>> Performance Limited is one deliberate compatibility exception. ACPI lists
>> it as required, but permits a platform with no limiting indication to
>> always return zero, and deployed firmware represents that case with a NULL
>> descriptor. CPPC control does not depend on this status register, so we
>> continue to accept that encoding. A present _CPC package which otherwise
>> fails parsing or initialization now emits an error instead of silently
>> preventing cpufreq registration.
>>
>> Compound performance and EPP updates propagate errors and perform every
>> fallible non-PCC write before modifying the PCC payload. Updates across
>> address spaces cannot be atomic, but a known non-PCC failure can no longer
>> commit only the PCC portion or leave an unsent value for a later command.
>> All requested PCC fields are validated before the first payload store, so
>> a malformed later field cannot leave an earlier value for a subsequent
>> doorbell to commit. Writable Minimum and Maximum Performance controls are
>> programmed even when their requested value is zero, because zero can be a
>> valid abstract performance level rather than an omitted update.
>>
>> SystemMemory locking and support boundary
>> =========================================
>>
>> A partial SystemMemory field requires RMW to preserve the rest of its
>> access unit. Commit 60949b7b8054 ("ACPI: CPPC: Fix MASK_VAL() usage") used
>> a per-_CPC lock and noted that a global lock would be needed if physical
>> registers were shared between packages.
>>
>> ACPI does not make _PSD a physical-register ownership boundary. Rather than
>> put a global raw lock or lookup into the scheduler path, this series makes
>> the cheaper per-descriptor model's assumptions enforceable at probe.
>>
>> Supported SystemMemory layouts are:
>>
>>    - naturally aligned 8-, 16-, 32-, and 64-bit access units;
>>    - lockless full-width controls;
>>    - read-only aliases;
>>    - exact writable aliases, including partial aliases of the same logical
>>      field, when the complete access is one aligned native transaction;
>>    - disjoint partial writers within one descriptor, serialized by its
>>      rmw_lock, when neither must preserve another write-only field; and
>>    - a partial writer sharing an access unit with a disjoint read-only
>>      field, except Performance Limited.
>>
>> Probe rejects overlapping logical fields involving a writer, another field
>> inside a full-width writable access unit, non-identical cross-descriptor
>> partial writers, writers sharing Performance Limited's access unit, writers
>> which would preserve a write-only neighbour, unaligned accesses, and exact
>> writable 64-bit aliases on 32-bit kernels. These layouts were not safely
>> supported by the old per-descriptor lock or generic writeq(); rejecting them
>> turns possible corruption into a visible probe failure rather than removing
>> working support.
>>
>> PCC access and locking
>> ======================
>>
>> The PCC protocol requires OSPM to acquire the subspace before changing its
>> command or payload. Single-register and EPP updates now hold pcc_lock
>> across ownership acquisition, payload staging, and command submission.
>> Concurrent Phase-I callers intentionally store the same true value to the
>> pending-command flag under the shared side of pcc_lock, so that store uses
>> WRITE_ONCE(); transitions back to false remain exclusively locked.
>>
>> ACPI 6.6's implementation example places a mandatory 32-bit Delivered
>> Performance Counter at unaligned PCC offset 0x116. Performance controls may
>> also use byte-multiple widths such as 24 bits. PCC therefore uses
>> byte-oriented I/O with explicit little-endian encoding for zero-offset,
>> byte-multiple fields from 8 through 64 bits. A short per-subspace payload
>> lock protects concurrent aliased copies made under the shared side of
>> pcc_lock; it does not replace the protocol ownership lock.
>>
>> Bit-level PCC fields require RMW and remain unsupported. An unsupported
>> optional field is marked absent, but a present inaccessible CPPC Enable
>> fails probe because OSPM must write it before using CPPC. Thus the
>> ACPI-legal one-bit CPPC Enable used by the specification example is a
>> documented kernel limitation. The old accessor could not program it
>> correctly either, so an explicit error is safer than silently proceeding
>> without enabling CPPC.
>>
>> Every retained PCC field is bounds checked against the shared-memory
>> region. A subspace-keyed interval registry permits read-only overlap and
>> exact same-control aliases while rejecting every other writable overlap
>> across processors. A lifecycle mutex serializes allocation, reference
>> updates, first channel setup, and teardown of each shared PCC object.
>>
>> SystemIO support boundary
>> =========================
>>
>> SystemIO supports Bit Offset zero, naturally aligned, full 8-, 16-, or
>> 32-bit accesses ending at or below port 0xffff, including legacy Access
>> Size zero when Bit Width supplies the size. Partial fields never worked
>> because the driver neither shifted them nor preserved adjacent bits, so
>> they now fail visibly instead of being misprogrammed.
>>
>> On kernels without CONFIG_HAS_IOPORT, SystemIO entries are rejected or
>> disabled according to the affected control's semantics. Runtime accessors
>> also return -EOPNOTSUPP rather than treating an I/O port as a
>> physical-memory address. A global port interval registry rejects
>> cross-processor writable overlap.
>>
>> Write-only and Performance Limited controls
>> ===========================================
>>
>> Between _CPC revisions 3 and 4, Desired Performance changed from
>> Read/Write to Write, and revision 4 added write-only OSPM Nominal
>> Performance. ACPI 6.6 Section 4.6.3 says reads from write-only positions
>> are undefined. Explicit reads of both controls are rejected. Partial
>> SystemMemory fields remain writable because RMW replaces every bit of the
>> field and therefore does not propagate its undefined readback, provided no
>> other writer shares the access unit and would preserve that field.
>>
>> Performance Limited is sticky, write-zero-to-clear, and requires
>> interlocked accesses under ACPI 6.6 Section 8.4.6.1.3.2. The old separate
>> read and write could clear a new event reported between transactions. The
>> clear path now writes zero only to requested status bits and one to the
>> other defined bits. Partial SystemMemory forms remain readable but cannot
>> be cleared because a spinlock cannot interlock an enclosing RMW with
>> platform updates. Probe also rejects another writable field sharing its
>> access unit. QWord forms cannot be used on 32-bit kernels, where the MMIO
>> accessor may be split into two 32-bit operations; naturally aligned,
>> full-width QWords remain supported on 64-bit kernels. Since CPPC control
>> does not depend on Performance Limited status, an unreadable description
>> marks status access unsupported instead of rejecting the processor's
>> otherwise usable _CPC. Its physical range remains visible to overlap
>> validation so another writer cannot evade the status-register conflict.
>>
>> Lifetime and cleanup
>> ====================
>>
>> CPC descriptors are released through their kobject callback, keeping their
>> storage and mappings alive for outstanding sysfs references. Every PCC
>> allocation, reference, and acquired channel is unwound on probe failure,
>> and the per-CPU PCC index is initialized before every early return. PCC
>> allocation uses a separate temporary result, so its success cannot turn a
>> later parse failure into a successful probe return. Shared PCC allocation,
>> reference updates, channel initialization, and teardown are serialized. A
>> repeated processor start reuses an already published descriptor instead of
>> resetting its PCC index and leaking or detaching the existing state.
>>
>> Changes since v5
>> ================
>>
>>    - Kept Lowest Performance zero valid while starting the arm64 artificial
>>      energy model at its first positive capacity step, and made every
>>      present _CPC initialization failure emit the common CPU/errno
>>      diagnostic.
>>    - Checked completion of a preceding PCC command before writing the direct
>>      half of a mixed-address-space performance request.
>>    - Coalesced exact SystemMemory aliases behind one interval-tree node and
>>      promoted a live alias on teardown, avoiding quadratic probe work on
>>      large systems. Also skipped registry allocations for descriptors with
>>      no entries in the corresponding address space.
>>    - Stopped treating unused Performance Reduction Tolerance and Time Window
>>      entries as writers, and retained disjoint fields when a narrower
>>      full-width write cannot touch the overlapping read-only access unit.
>>    - Preserved inaccessible write-only controls in physical overlap
>>      validation, and tested whether the other writer's access unit actually
>>      covers the write-only field before rejecting an asymmetric layout.
>>    - Restricted writable PCC controls to their DWORD width, coherently
>>      disabled an inaccessible Minimum/Maximum pair, and ordered PCC payload
>>      bytes against completion and doorbell accesses.
>>    - Classified a SystemMemory field as writable during overlap validation
>>      only when both its _CPC semantics and validated access permit writes.
>>      This keeps partial Performance Limited status fields shareable after
>>      their unsafe clear path has been disabled, while still rejecting an
>>      actual writer sharing the status access unit.
>>    - Preserved an inaccessible 64-bit Performance Limited physical range on
>>      32-bit kernels while marking reads and writes unsupported, so a
>>      neighbouring writer remains detectable without mapping a split access.
>>
>> Changes since v4
>> ================
>>
>>    - Validated all requested PCC control widths before the first payload
>>      store, preventing a later malformed field from leaving an earlier
>>      staged value for a subsequent doorbell to commit.
>>    - Marked the intentional concurrent same-value pending-command store with
>>      WRITE_ONCE().
>>    - Serialized shared PCC allocation, reference updates, channel setup, and
>>      teardown, and published channel readiness only after initializing its
>>      lock and wait queue.
>>    - Rejected another writable field sharing a SystemMemory access unit with
>>      a write-only field, because its RMW would preserve and replay undefined
>>      readback.
>>    - Rejected capability values which do not fit the u32 interface instead
>>      of allowing truncation and a possible zero divisor.
>>    - Programmed writable Minimum and Maximum Performance controls when the
>>      requested value is zero, which is valid when Lowest Performance is zero.
>>    - Reused an existing CPC descriptor on a repeated processor start instead
>>      of resetting its PCC index before a retry could fail.
>>
>> Changes since v3
>> ================
>>
>>    - Allowed partial SystemMemory Desired and OSPM Nominal controls when RMW
>>      discards their undefined readback, supporting NVIDIA's separate 9-bit
>>      controls in _CPC revision 4.
>>    - Reported an unavailable Desired Performance control as unsupported from
>>      the common getter instead of returning a synthetic zero.
>>    - Required natural alignment for SystemIO access units, preventing faults
>>      on architectures which implement port I/O through Device-memory MMIO.
>>    - Kept partial Performance Limited fields readable but not clearable,
>>      rejected another writer sharing their access unit, reported fully
>>      inaccessible forms as unsupported instead of returning a synthetic
>>      zero, and consolidated each nonfatal fallback into a single warning.
>>
>> Changes since v2
>> ================
>>
>>    - Relaxed the exact NumEntries/package-count match to tolerate safe
>>      trailing package elements while still rejecting any count that could
>>      cause an out-of-bounds walk.
>>    - Made patch 10 independently preserve immutable-autonomous setups whose
>>      inaccessible Desired Performance register requires RMW, rather than
>>      relying on patch 11 to restore that exception.
>>
>> Sashiko v2 review not addressed
>> ===============================
>>
>>    - Kept Guaranteed Performance Buffer-only. The suggestion was to accept a
>>      nonzero Integer, but ACPI 6.6 Table 8.23 permits only a Buffer for this
>>      entry.
>>
>> Sashiko v4/v5 review requiring no code change
>> =============================================
>>
>>    - Kept nonzero Integers restricted to entries whose object type includes
>>      Integer in ACPI 6.6 Table 8.23. Guaranteed Performance and Energy
>>      Performance Preference are Buffer-only registers.
>>    - Kept Desired Performance optional only when OSPM advertises CPPC2 and
>>      Autonomous Selection Enable is encoded as Integer 1. ACPI 6.6 Section
>>      8.4.6.1.2.3 explicitly requires that immutable encoding; a writable
>>      Buffer does not qualify.
>>
>> Deferred follow-up work
>> =======================
>>
>> Sashiko also identified a broader pre-existing lifetime question which this
>> series does not attempt to solve. In-kernel accessors read the per-CPU
>> cpc_desc_ptr without acquiring a reference, while processor teardown can
>> unpublish and eventually release the descriptor and its PCC data. The
>> kobject change here fixes the concrete sysfs lifetime bug, but a NULL
>> pcc_data check would not protect a caller which already holds a stale
>> pointer. Closing this properly requires defining the kernel accessor
>> lifetime contract and then using CPU-hotplug serialization / safe
>> referencing across all callers, therefore will be handled by a follow-up.
>>
>> ACPI-legal bit-level PCC and SystemIO fields also remain unsupported. In
>> particular, the ACPI example's one-bit PCC CPPC Enable register cannot be
>> implemented by the old whole-value accessors. Supporting these
>> descriptions requires transport-specific field extraction and an RMW
>> operation which obeys PCC ownership or safely preserves adjacent SystemIO
>> bits, just accepting the descriptors would silently program the wrong
>> value. Therefore continue to disable optional inaccessible fields where
>> safe and reject a present inaccessible CPPC Enable control.
>> Full support, if even needed, belongs in a separate follow-up.
>>
>> The review additionally suggested validating the complete AML
>> ResourceTemplate, including its EndTag. We currently validate the Register
>> descriptor we consume and tolerate trailing firmware data. I don't really
>> see the point of ever doing this, but definitely not in this series,
>> where I'm trying to guarantee that no reasonably working platform is
>> regressing.
>>
>> Patches 1, 2, 4-7, and 9 address findings reported by Sashiko while
>> reviewing:
>>
>>    https://sashiko.dev/#/patchset/20260724134251.1632824-1-christian.loehle%40arm.com
>>
>> Patches 3, 5, 6, 9, 10, and 15 address findings from the follow-up review:
>>
>>    https://sashiko.dev/#/patchset/20260807111303.1062391-1-christian.loehle%40arm.com
>>
>> Patches 1 and 10 address findings from the v2 review:
>>
>>    https://sashiko.dev/#/patchset/20260808082644.1251332-1-christian.loehle%40arm.com
>>
>> Christian Loehle (15):
>>    ACPI: CPPC: Validate the _CPC package header
>>    ACPI: CPPC: Validate _CPC entry and control semantics
>>    ACPI: CPPC: Propagate performance-control write errors
>>    ACPI: CPPC: Use 64-bit masks for register fields
>>    ACPI: CPPC: Serialize PCC single-register payload updates
>>    ACPI: CPPC: Serialize PCC EPP payload updates
>>    ACPI: CPPC: Release CPC descriptors through kobject
>>    ACPI: CPPC: Release PCC data after probe failures
>>    ACPI: CPPC: Reject unsafe cross-CPU SystemMemory RMW
>>    ACPI: CPPC: Reject direct reads of write-only controls
>>    ACPI: CPPC: Validate and access PCC register layouts
>>    ACPI: CPPC: Validate SystemIO register layouts
>>    ACPI: CPPC: Validate PCC overlaps across processors
>>    ACPI: CPPC: Validate SystemIO overlaps across processors
>>    ACPI: CPPC: Clear Performance Limited without a stale read
>>
>>   drivers/acpi/cppc_acpi.c     | 1807 ++++++++++++++++++++++++++++++++++++------
>>   drivers/cpufreq/amd-pstate.c |   12 +-
>>   include/acpi/cppc_acpi.h     |   11 +-
>>   3 files changed, 1569 insertions(+), 261 deletions(-)
>>
>> base-commit: 08dbfad3f5040f5bdb6c529da20d6d4e81fefd72
>> --
>> 2.34.1
> 
> +CC AMD maintainers

I've tested this series on top of 7.3-rc1 on a handful of Zen5 and Zen6 
client hardware.

It works correctly on Zen5 with this series as is.
With my CPPC patches on top of it for Zen6 it works correctly.

Tested-by: Mario Limonciello (AMD) <superm1@kernel.org>

Re: [PATCH v6 02/15] ACPI: CPPC: Validate _CPC entry and control semantics

[Rafael J. Wysocki (Intel)]

On Sun, Aug 30, 2026 at 3:32 PM Christian Loehle
<christian.loehle@arm.com> wrote:
>
> On 8/30/26 12:56, Christian Loehle wrote:
> > Writable _CPC controls are Register descriptors encoded as Buffer objects.
> > Integer entries represent fixed values or unsupported optional registers;
> > Autonomous Selection Integer 1 is the special immutable form which enables
> > operation without Desired Performance.
> >
> > The parser accepts arbitrary object types and cpc_write() assumes that its
> > argument contains a GAS. Malformed firmware can therefore make it interpret
> > an Integer union member as a register.
> >
> > Validate the portion of each encoding consumed by the driver: bound Integer
> > DWORD forms to 32 bits, and require Buffer entries to start with a complete
> > Generic Register descriptor with the expected header. Continue tolerating
> > Integer 0 for an absent optional register and retain type checks in
> > cpc_write() as defense in depth. Reject an attempt to disable immutable
> > Autonomous Selection instead of silently applying only the EPP part of the
> > request.
> >
> > Capability registers are read into u64 temporaries but exposed through u32
> > fields. Reject values above U32_MAX instead of allowing them to be
> > truncated. In particular, a truncated Highest Performance value can become
> > a zero divisor in the performance-to-frequency conversion. Enforce the
> > required ordering from Highest through Nominal, Lowest Nonlinear, and
> > Lowest Performance, and constrain a present Guaranteed Performance to the
> > inclusive Lowest-to-Nominal range. Also reject reversed frequency anchors
> > and unequal frequency anchors with identical performance anchors. Those
> > invalid tuples otherwise make affine-conversion differences wrap or divide
> > by zero.
> >
> > Check mandatory object presence separately from the Integer-zero convention
> > for absent optional fields. ACPI does not reserve zero in the abstract
> > Lowest Performance scale, so accept a present Lowest Performance DWORD of
> > zero when distinct frequency anchors provide a usable nonzero physical
> > minimum. Retain the old rejection when that mapping is unavailable and the
> > fallback conversion would expose a 0 kHz cpufreq endpoint.
> >
> > Minimum Performance also defines zero as a real no-limit value, but the
> > exported cppc_set_perf() interface historically used zero to omit a bound.
> > Add explicit validity flags so callers can request zero without changing
> > that legacy convention. Populate the flags when reading the controls and
> > mark the bounds supplied by amd-pstate explicitly.
> >
> > Performance Limited is listed as a required Buffer, but the interface does
> > not depend on it to control performance and the specification permits a
> > platform with no limiting indication to always report zero. Preserve
> > the compatibility with firmware that represents that case using a NULL
> > register descriptor instead of disabling CPPC entirely.
> >
> > Emit an error when a present _CPC package fails parsing or initialization
> > so such firmware and resource failures no longer silently suppress cpufreq.
> > Initialize malformed-package failures to -EINVAL and preserve specific
> > allocation, mapping, and unsupported-access errors in that diagnostic.
> >
> > Fixes: 337aadff8e45 ("ACPI: Introduce CPU performance controls using CPPC")
> > Reported-by: Sashiko <sashiko-bot@kernel.org>
> > Link: https://sashiko.dev/#/patchset/20260724134251.1632824-1-christian.loehle%40arm.com
> > Signed-off-by: Christian Loehle <christian.loehle@arm.com>
> > ---
> >  drivers/acpi/cppc_acpi.c     | 172 ++++++++++++++++++++++++++++++-----
> >  drivers/cpufreq/amd-pstate.c |  12 ++-
> >  include/acpi/cppc_acpi.h     |   2 +
> >  3 files changed, 159 insertions(+), 27 deletions(-)
> >
> > diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
> > index 3b8cdf88e31d..6f3ffa4a1845 100644
> > --- a/drivers/acpi/cppc_acpi.c
> > +++ b/drivers/acpi/cppc_acpi.c
> > @@ -129,6 +129,21 @@ static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
> >                               !!(cpc)->cpc_entry.int_value :          \
> >                               !IS_NULL_REG(&(cpc)->cpc_entry.reg))
> >
> > +static bool cpc_is_writable(const struct cpc_register_resource *cpc)
> > +{
> > +     return cpc->type == ACPI_TYPE_BUFFER &&
> > +            !IS_NULL_REG(&cpc->cpc_entry.reg);
> > +}
> > +
> > +static bool cpc_entry_present(const struct cpc_register_resource *cpc)
> > +{
> > +     if (cpc->type == ACPI_TYPE_INTEGER)
> > +             return true;
> > +
> > +     return cpc->type == ACPI_TYPE_BUFFER &&
> > +            !IS_NULL_REG(&cpc->cpc_entry.reg);
> > +}
> > +
> >  /*
> >   * Each bit indicates the optionality of the register in per-cpu
> >   * cpc_regs[] with the corresponding index. 0 means mandatory and 1
> > @@ -142,6 +157,29 @@ static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
> >   */
> >  #define IS_OPTIONAL_CPC_REG(reg_idx) (REG_OPTIONAL & (1U << (reg_idx)))
> >
> > +static bool cpc_integer_entry_valid(unsigned int reg_idx, u64 value)
> > +{
> > +     switch (reg_idx) {
> > +     case HIGHEST_PERF:
> > +     case NOMINAL_PERF:
> > +     case LOW_NON_LINEAR_PERF:
> > +     case LOWEST_PERF:
> > +     case CTR_WRAP_TIME:
> > +     case REFERENCE_PERF:
> > +     case LOWEST_FREQ:
> > +     case NOMINAL_FREQ:
> > +             return value <= U32_MAX;
>
>
> Sashiko:
> "Does this incorrectly restrict the counter wraparound time to 32 bits?
> The ACPI specification allows firmware to provide a 64-bit QWord integer
> for the Counter Wraparound Time. The cppc_perf_fb_ctrs structure already
> models this as a 64-bit value internally
> If firmware provides a valid 64-bit integer exceeding U32_MAX for this
> register, cpc_integer_entry_valid() will return false and completely abort
> CPPC initialization for the CPU. Can we remove this restriction for
> CTR_WRAP_TIME?"
> This is true. ACPI spec 6.6 and 6.5 (Table 8.23) describe it as
> Integer (DWORD) or Buffer
> The 64-bit internal representation is only for the case of firmware
> providing it as Buffer.
>
> > +     case AUTO_SEL_ENABLE:
> > +             return value <= 1;
> > +     case DESIRED_PERF:
> > +             /* Validated against Autonomous Selection after parsing. */
> > +             return value == 0;
> > +     default:
> > +             /* Tolerate the customary Integer 0 for an absent option. */
> > +             return value == 0 && IS_OPTIONAL_CPC_REG(reg_idx);
> > +     }
> > +}
> > +
> Sashiko:
> "Does this incorrectly restrict the counter wraparound time to 32 bits?
> The ACPI specification allows firmware to provide a 64-bit QWord integer
> for the Counter Wraparound Time. The cppc_perf_fb_ctrs structure already
> models this as a 64-bit value internally.
> If firmware provides a valid 64-bit integer exceeding U32_MAX for this
> register, cpc_integer_entry_valid() will return false and completely abort
> CPPC initialization for the CPU. Can we remove this restriction for
> CTR_WRAP_TIME?"

It looks like you pasted the same comment twice.  Or did Sashiko hallucinate?

> GUARANTEED_PERF and TIME_WINDOW: both are Buffer-only Register descriptors.
> Nonzero Integer encodings are invalid and Integer 0 is tolerated because
> the previous parser allowed it too. I don't know of any platform describing
> this myself.
>
> >  /*
> >   * Arbitrary Retries in case the remote processor is slow to respond
> >   * to PCC commands. Keeping it high enough to cover emulators where
> > @@ -150,6 +188,8 @@ static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
> >  #define NUM_RETRIES 500ULL
> >
> >  #define OVER_16BTS_MASK ~0xFFFFULL
> > +#define CPC_GENERIC_REGISTER_DESCRIPTOR 0x82
> > +#define CPC_GENERIC_REGISTER_LENGTH (sizeof(struct cpc_reg) - 3)
> >
> >  #define define_one_cppc_ro(_name)            \
> >  static struct kobj_attribute _name =         \
> > @@ -773,8 +813,10 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
> >       acpi_handle handle = pr->handle;
> >       unsigned int num_ent, i, cpc_rev;
> >       int pcc_subspace_id = -1;
> > +     bool cpc_present = false;
> >       acpi_status status;
> >       int ret = -ENODATA;
> > +     int err;
> >
> >       if (!osc_sb_cppc2_support_acked) {
> >               pr_debug("CPPC v2 _OSC not acked\n");
> > @@ -791,6 +833,8 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
> >               ret = -ENODEV;
> >               goto out_buf_free;
> >       }
> > +     cpc_present = true;
> > +     ret = -EINVAL;
> >
> >       out_obj = (union acpi_object *) output.pointer;
> >       if (out_obj->package.count < 2) {
> > @@ -871,11 +915,32 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
> >               cpc_obj = &out_obj->package.elements[i];
> >
> >               if (cpc_obj->type == ACPI_TYPE_INTEGER) {
> > -                     cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER;
> > -                     cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value;
> > +                     if (!cpc_integer_entry_valid(i - 2,
> > +                                                  cpc_obj->integer.value)) {
> > +                             pr_debug("Invalid Integer _CPC register %u for CPU:%d\n",
> > +                                      i - 2, pr->id);
> > +                             ret = -EINVAL;
> > +                             goto out_free;
> > +                     }
> > +                     cpc_ptr->cpc_regs[i - 2].type = ACPI_TYPE_INTEGER;
> > +                     cpc_ptr->cpc_regs[i - 2].cpc_entry.int_value = cpc_obj->integer.value;
> >               } else if (cpc_obj->type == ACPI_TYPE_BUFFER) {
> > +                     if (cpc_obj->buffer.length < sizeof(*gas_t)) {
> > +                             pr_debug("Invalid register descriptor for CPU:%d\n",
> > +                                      pr->id);
> > +                             ret = -EINVAL;
> > +                             goto out_free;
> > +                     }
> > +
> >                       gas_t = (struct cpc_reg *)
> >                               cpc_obj->buffer.pointer;
> > +                     if (gas_t->descriptor != CPC_GENERIC_REGISTER_DESCRIPTOR ||
> > +                         gas_t->length != CPC_GENERIC_REGISTER_LENGTH) {
> > +                             pr_debug("Invalid register resource for CPU:%d\n",
> > +                                      pr->id);
> > +                             ret = -EINVAL;
> > +                             goto out_free;
> > +                     }
> >
> >                       /*
> >                        * The PCC Subspace index is encoded inside
> > @@ -886,8 +951,11 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
> >                       if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
> >                               if (pcc_subspace_id < 0) {
> >                                       pcc_subspace_id = gas_t->access_width;
> > -                                     if (pcc_data_alloc(pcc_subspace_id))
> > +                                     err = pcc_data_alloc(pcc_subspace_id);
> > +                                     if (err) {
> > +                                             ret = err;
> >                                               goto out_free;
> > +                                     }
> >                               } else if (pcc_subspace_id != gas_t->access_width) {
> >                                       pr_debug("Mismatched PCC ids in _CPC for CPU:%d\n",
> >                                                pr->id);
> > @@ -900,14 +968,18 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
> >
> >                                       if (!osc_cpc_flexible_adr_space_confirmed) {
> >                                               pr_debug("Flexible address space capability not supported\n");
> > +                                             ret = -EOPNOTSUPP;
> >                                               if (!cpc_supported_by_cpu())
> >                                                       goto out_free;
> > +                                             ret = -EINVAL;
> >                                       }
> >
> >                                       access_width = GET_BIT_WIDTH(gas_t) / 8;
> >                                       addr = ioremap(gas_t->address, access_width);
> > -                                     if (!addr)
> > +                                     if (!addr) {
> > +                                             ret = -ENOMEM;
> >                                               goto out_free;
> > +                                     }
> >                                       cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr;
> >                               }
> >                       } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
> > @@ -929,14 +1001,17 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
> >                               }
> >                               if (!osc_cpc_flexible_adr_space_confirmed) {
> >                                       pr_debug("Flexible address space capability not supported\n");
> > +                                     ret = -EOPNOTSUPP;
> >                                       if (!cpc_supported_by_cpu())
> >                                               goto out_free;
> > +                                     ret = -EINVAL;
> >                               }
> >                       } else {
> >                               if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) {
> >                                       /* Support only PCC, SystemMemory, SystemIO, and FFH type regs. */
> >                                       pr_debug("Unsupported register type (%d) in _CPC\n",
> >                                                gas_t->space_id);
> > +                                     ret = -EOPNOTSUPP;
> >                                       goto out_free;
> >                               }
> >                       }
> > @@ -961,15 +1036,35 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
> >       }
> >       per_cpu(cpu_pcc_subspace_idx, pr->id) = pcc_subspace_id;
> >
> > +     /*
> > +      * Performance Limited is required by the specification, but tolerate a
> > +      * NULL descriptor used by firmware which cannot report limiting events.
> > +      * CPPC control does not depend on this status.
> > +      */
> > +     for (i = 0; i < num_ent - 2; i++) {
> > +             if (i != DESIRED_PERF && i != PERF_LIMITED &&
> > +                 !IS_OPTIONAL_CPC_REG(i) &&
> > +                 !cpc_entry_present(&cpc_ptr->cpc_regs[i])) {
> > +                     pr_debug("CPU:%d lacks mandatory _CPC register %u\n",
> > +                              pr->id, i);
> > +                     ret = -EINVAL;
> > +                     goto out_free;
> > +             }
> > +     }
> > +
> >       /*
> >        * In CPPC v1, DESIRED_PERF is mandatory. In CPPC v2, it is optional
> >        * only when AUTO_SEL_ENABLE is supported.
> >        */
> > -     if (!CPC_SUPPORTED(&cpc_ptr->cpc_regs[DESIRED_PERF]) &&
> > +     if (!cpc_is_writable(&cpc_ptr->cpc_regs[DESIRED_PERF]) &&
> >           (!osc_sb_cppc2_support_acked ||
> > -          !CPC_SUPPORTED(&cpc_ptr->cpc_regs[AUTO_SEL_ENABLE])))
> > -             pr_warn("Desired perf. register is mandatory if CPPC v2 is not supported "
> > -                     "or autonomous selection is disabled\n");
> > +          cpc_ptr->cpc_regs[AUTO_SEL_ENABLE].type != ACPI_TYPE_INTEGER ||
> > +          cpc_ptr->cpc_regs[AUTO_SEL_ENABLE].cpc_entry.int_value != 1)) {
> > +             pr_debug("CPU:%d lacks a writable Desired Performance register\n",
> > +                      pr->id);
> > +             ret = -EINVAL;
> > +             goto out_free;
> > +     }
> >
> >       /*
> >        * Initialize the remaining cpc_regs as unsupported.
> > @@ -1037,6 +1132,8 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
> >       kfree(cpc_ptr);
> >
> >  out_buf_free:
> > +     if (cpc_present)
> > +             pr_err("CPU%d: failed to initialize _CPC: %d\n", pr->id, ret);
> >       kfree(output.pointer);
> >       return ret;
> >  }
> > @@ -1217,11 +1314,18 @@ static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
> >       u64 prev_val;
> >       void __iomem *vaddr = NULL;
> >       int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
> > -     struct cpc_reg *reg = &reg_res->cpc_entry.reg;
> > +     struct cpc_reg *reg;
> >       struct cpc_desc *cpc_desc;
> >       unsigned long flags;
> >       bool locked = false;
> >
> > +     if (reg_res->type != ACPI_TYPE_BUFFER)
> > +             return -EOPNOTSUPP;
> > +
> > +     reg = &reg_res->cpc_entry.reg;
> > +     if (IS_NULL_REG(reg))
> > +             return -EOPNOTSUPP;
> > +
> >       size = GET_BIT_WIDTH(reg);
> >
> >       if (IS_ENABLED(CONFIG_HAS_IOPORT) &&
> > @@ -1364,7 +1468,9 @@ static int cppc_get_reg_val(int cpu, enum cppc_regs reg_idx, u64 *val)
> >
> >       reg = &cpc_desc->cpc_regs[reg_idx];
> >
> > -     if ((reg->type == ACPI_TYPE_INTEGER && IS_OPTIONAL_CPC_REG(reg_idx) &&
> > +     /* Desired may be absent for immutable autonomous selection. */
> > +     if ((reg->type == ACPI_TYPE_INTEGER &&
> > +          (IS_OPTIONAL_CPC_REG(reg_idx) || reg_idx == DESIRED_PERF) &&
> >            !reg->cpc_entry.int_value) || (reg->type != ACPI_TYPE_INTEGER &&
> >            IS_NULL_REG(&reg->cpc_entry.reg))) {
> >               pr_debug("CPC register is not supported\n");
> > @@ -1415,7 +1521,7 @@ static int cppc_set_reg_val(int cpu, enum cppc_regs reg_idx, u64 val)
> >       reg = &cpc_desc->cpc_regs[reg_idx];
> >
> >       /* if a register is writeable, it must be a buffer and not null */
> > -     if ((reg->type != ACPI_TYPE_BUFFER) || IS_NULL_REG(&reg->cpc_entry.reg)) {
> > +     if (!cpc_is_writable(reg)) {
> >               pr_debug("CPC register is not supported\n");
> >               return -EOPNOTSUPP;
> >       }
> > @@ -1505,7 +1611,7 @@ int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
> >       struct cpc_register_resource *highest_reg, *lowest_reg,
> >               *lowest_non_linear_reg, *nominal_reg, *reference_reg,
> >               *guaranteed_reg, *low_freq_reg = NULL, *nom_freq_reg = NULL;
> > -     u64 high, low, guaranteed, nom, ref, min_nonlinear,
> > +     u64 high, low, guaranteed = 0, nom, ref, min_nonlinear,
> >           low_f = 0, nom_f = 0;
> >       int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
> >       struct cppc_pcc_data *pcc_ss_data = NULL;
> > @@ -1588,7 +1694,12 @@ int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
> >               goto out_err;
> >       perf_caps->lowest_nonlinear_perf = min_nonlinear;
> >
> > -     if (!high || !low || !nom || !ref || !min_nonlinear) {
> > +     if (!high || !nom || !ref || !min_nonlinear ||
> > +         high > U32_MAX || low > U32_MAX || guaranteed > U32_MAX ||
> > +         nom > U32_MAX || ref > U32_MAX || min_nonlinear > U32_MAX ||
> > +         high < nom || nom < min_nonlinear || min_nonlinear < low ||
> > +         (CPC_SUPPORTED(guaranteed_reg) &&
> > +          (guaranteed < low || guaranteed > nom))) {
> >               ret = -EFAULT;
> >               goto out_err;
> >       }
> > @@ -1605,6 +1716,19 @@ int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
> >               if (ret)
> >                       goto out_err;
> >       }
> > +     /*
> > +      * Require ordered anchors and a nonzero slope when frequencies differ.
> > +      * A zero Lowest Performance needs that affine mapping to produce a
> > +      * nonzero physical minimum frequency.
> > +      */
> > +     if (low_f > U32_MAX || nom_f > U32_MAX ||
> > +         (!low && (!low_f || !nom_f || low_f == nom_f)) ||
> > +         (low_f && nom_f &&
> > +          (nom_f < low_f || nom < low ||
> > +           (nom_f != low_f && nom == low)))) {
> > +             ret = -EFAULT;
> > +             goto out_err;
> > +     }
> >
> >       perf_caps->lowest_freq = low_f;
> >       perf_caps->nominal_freq = nom_f;
> > @@ -1779,6 +1903,9 @@ int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable)
> >
> >       auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
> >       epp_set_reg = &cpc_desc->cpc_regs[ENERGY_PERF];
> > +     if (!enable && auto_sel_reg->type == ACPI_TYPE_INTEGER &&
> > +         auto_sel_reg->cpc_entry.int_value == 1)
> > +             return -EOPNOTSUPP;
> >
> >       epp_ffh_sysmem = CPC_SUPPORTED(epp_set_reg) &&
> >               (CPC_IN_FFH(epp_set_reg) || CPC_IN_SYSTEM_MEMORY(epp_set_reg));
> > @@ -1791,13 +1918,13 @@ int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable)
> >                       return -ENODEV;
> >               }
> >
> > -             if (CPC_SUPPORTED(auto_sel_reg)) {
> > +             if (cpc_is_writable(auto_sel_reg)) {
> >                       ret = cpc_write(cpu, auto_sel_reg, enable);
> >                       if (ret)
> >                               return ret;
> >               }
> >
> > -             if (CPC_SUPPORTED(epp_set_reg)) {
> > +             if (cpc_is_writable(epp_set_reg)) {
> >                       ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf);
> >                       if (ret)
> >                               return ret;
> > @@ -1996,6 +2123,8 @@ int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
> >       max_perf_reg = &cpc_desc->cpc_regs[MAX_PERF];
> >       energy_perf_reg = &cpc_desc->cpc_regs[ENERGY_PERF];
> >       auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
> > +     perf_ctrls->max_perf_valid = false;
> > +     perf_ctrls->min_perf_valid = false;
> >
> >       /* Are any of the regs PCC ?*/
> >       if (CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg) ||
> > @@ -2020,6 +2149,7 @@ int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
> >               ret = cpc_read(cpu, max_perf_reg, &max);
> >               if (ret)
> >                       goto out_err;
> > +             perf_ctrls->max_perf_valid = true;
> >       }
> >       perf_ctrls->max_perf = max;
> >
> > @@ -2027,6 +2157,7 @@ int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
> >               ret = cpc_read(cpu, min_perf_reg, &min);
> >               if (ret)
> >                       goto out_err;
> > +             perf_ctrls->min_perf_valid = true;
> >       }
> >       perf_ctrls->min_perf = min;
> >
> > @@ -2113,14 +2244,11 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
> >       if (CPC_SUPPORTED(desired_reg))
> >               cpc_write(cpu, desired_reg, perf_ctrls->desired_perf);
> >
> > -     /*
> > -      * Only write if min_perf and max_perf not zero. Some drivers pass zero
> > -      * value to min and max perf, but they don't mean to set the zero value,
> > -      * they just don't want to write to those registers.
> > -      */
> > -     if (perf_ctrls->min_perf && CPC_SUPPORTED(min_perf_reg))
> > +     if (CPC_SUPPORTED(min_perf_reg) &&
> > +         (perf_ctrls->min_perf || perf_ctrls->min_perf_valid))
> >               cpc_write(cpu, min_perf_reg, perf_ctrls->min_perf);
> > -     if (perf_ctrls->max_perf && CPC_SUPPORTED(max_perf_reg))
> > +     if (CPC_SUPPORTED(max_perf_reg) &&
> > +         (perf_ctrls->max_perf || perf_ctrls->max_perf_valid))
> >               cpc_write(cpu, max_perf_reg, perf_ctrls->max_perf);
> >
> >       if (regs_in_pcc)
> > diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
> > index d4ff8b228f86..63f0ca5f19b3 100644
> > --- a/drivers/cpufreq/amd-pstate.c
> > +++ b/drivers/cpufreq/amd-pstate.c
> > @@ -544,7 +544,13 @@ static int shmem_update_perf(struct cpufreq_policy *policy, u8 min_perf,
> >                            u8 des_perf, u8 max_perf, u8 epp, bool fast_switch)
> >  {
> >       struct amd_cpudata *cpudata = policy->driver_data;
> > -     struct cppc_perf_ctrls perf_ctrls;
> > +     struct cppc_perf_ctrls perf_ctrls = {
> > +             .max_perf = max_perf,
> > +             .min_perf = min_perf,
> > +             .desired_perf = des_perf,
> > +             .max_perf_valid = true,
> > +             .min_perf_valid = true,
> > +     };
> >       u64 value, prev;
> >       int ret;
> >
> > @@ -577,10 +583,6 @@ static int shmem_update_perf(struct cpufreq_policy *policy, u8 min_perf,
> >       if (value == prev)
> >               return 0;
> >
> > -     perf_ctrls.max_perf = max_perf;
> > -     perf_ctrls.min_perf = min_perf;
> > -     perf_ctrls.desired_perf = des_perf;
> > -
> >       ret = cppc_set_perf(cpudata->cpu, &perf_ctrls);
> >       if (ret)
> >               return ret;
> > diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h
> > index 94a6277edab2..5dcbe65c5ddc 100644
> > --- a/include/acpi/cppc_acpi.h
> > +++ b/include/acpi/cppc_acpi.h
> > @@ -141,6 +141,8 @@ struct cppc_perf_ctrls {
> >       u32 desired_perf;
> >       u32 energy_perf;
> >       bool auto_sel;
> > +     bool max_perf_valid;
> > +     bool min_perf_valid;
> >  };
> >
> >  struct cppc_perf_fb_ctrs {
>

Re: [PATCH v6 02/15] ACPI: CPPC: Validate _CPC entry and control semantics

[Rafael J. Wysocki (Intel)]

On Thu, Sep 3, 2026 at 9:27 PM Rafael J. Wysocki (Intel)
<rafael@kernel.org> wrote:
>
> On Sun, Aug 30, 2026 at 3:32 PM Christian Loehle
> <christian.loehle@arm.com> wrote:
> >
> > On 8/30/26 12:56, Christian Loehle wrote:
> > > Writable _CPC controls are Register descriptors encoded as Buffer objects.
> > > Integer entries represent fixed values or unsupported optional registers;
> > > Autonomous Selection Integer 1 is the special immutable form which enables
> > > operation without Desired Performance.
> > >
> > > The parser accepts arbitrary object types and cpc_write() assumes that its
> > > argument contains a GAS. Malformed firmware can therefore make it interpret
> > > an Integer union member as a register.
> > >
> > > Validate the portion of each encoding consumed by the driver: bound Integer
> > > DWORD forms to 32 bits, and require Buffer entries to start with a complete
> > > Generic Register descriptor with the expected header. Continue tolerating
> > > Integer 0 for an absent optional register and retain type checks in
> > > cpc_write() as defense in depth. Reject an attempt to disable immutable
> > > Autonomous Selection instead of silently applying only the EPP part of the
> > > request.
> > >
> > > Capability registers are read into u64 temporaries but exposed through u32
> > > fields. Reject values above U32_MAX instead of allowing them to be
> > > truncated. In particular, a truncated Highest Performance value can become
> > > a zero divisor in the performance-to-frequency conversion. Enforce the
> > > required ordering from Highest through Nominal, Lowest Nonlinear, and
> > > Lowest Performance, and constrain a present Guaranteed Performance to the
> > > inclusive Lowest-to-Nominal range. Also reject reversed frequency anchors
> > > and unequal frequency anchors with identical performance anchors. Those
> > > invalid tuples otherwise make affine-conversion differences wrap or divide
> > > by zero.
> > >
> > > Check mandatory object presence separately from the Integer-zero convention
> > > for absent optional fields. ACPI does not reserve zero in the abstract
> > > Lowest Performance scale, so accept a present Lowest Performance DWORD of
> > > zero when distinct frequency anchors provide a usable nonzero physical
> > > minimum. Retain the old rejection when that mapping is unavailable and the
> > > fallback conversion would expose a 0 kHz cpufreq endpoint.
> > >
> > > Minimum Performance also defines zero as a real no-limit value, but the
> > > exported cppc_set_perf() interface historically used zero to omit a bound.
> > > Add explicit validity flags so callers can request zero without changing
> > > that legacy convention. Populate the flags when reading the controls and
> > > mark the bounds supplied by amd-pstate explicitly.
> > >
> > > Performance Limited is listed as a required Buffer, but the interface does
> > > not depend on it to control performance and the specification permits a
> > > platform with no limiting indication to always report zero. Preserve
> > > the compatibility with firmware that represents that case using a NULL
> > > register descriptor instead of disabling CPPC entirely.
> > >
> > > Emit an error when a present _CPC package fails parsing or initialization
> > > so such firmware and resource failures no longer silently suppress cpufreq.
> > > Initialize malformed-package failures to -EINVAL and preserve specific
> > > allocation, mapping, and unsupported-access errors in that diagnostic.
> > >
> > > Fixes: 337aadff8e45 ("ACPI: Introduce CPU performance controls using CPPC")
> > > Reported-by: Sashiko <sashiko-bot@kernel.org>
> > > Link: https://sashiko.dev/#/patchset/20260724134251.1632824-1-christian.loehle%40arm.com
> > > Signed-off-by: Christian Loehle <christian.loehle@arm.com>
> > > ---
> > >  drivers/acpi/cppc_acpi.c     | 172 ++++++++++++++++++++++++++++++-----
> > >  drivers/cpufreq/amd-pstate.c |  12 ++-
> > >  include/acpi/cppc_acpi.h     |   2 +
> > >  3 files changed, 159 insertions(+), 27 deletions(-)
> > >
> > > diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
> > > index 3b8cdf88e31d..6f3ffa4a1845 100644
> > > --- a/drivers/acpi/cppc_acpi.c
> > > +++ b/drivers/acpi/cppc_acpi.c
> > > @@ -129,6 +129,21 @@ static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
> > >                               !!(cpc)->cpc_entry.int_value :          \
> > >                               !IS_NULL_REG(&(cpc)->cpc_entry.reg))
> > >
> > > +static bool cpc_is_writable(const struct cpc_register_resource *cpc)
> > > +{
> > > +     return cpc->type == ACPI_TYPE_BUFFER &&
> > > +            !IS_NULL_REG(&cpc->cpc_entry.reg);
> > > +}
> > > +
> > > +static bool cpc_entry_present(const struct cpc_register_resource *cpc)
> > > +{
> > > +     if (cpc->type == ACPI_TYPE_INTEGER)
> > > +             return true;
> > > +
> > > +     return cpc->type == ACPI_TYPE_BUFFER &&
> > > +            !IS_NULL_REG(&cpc->cpc_entry.reg);
> > > +}
> > > +
> > >  /*
> > >   * Each bit indicates the optionality of the register in per-cpu
> > >   * cpc_regs[] with the corresponding index. 0 means mandatory and 1
> > > @@ -142,6 +157,29 @@ static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
> > >   */
> > >  #define IS_OPTIONAL_CPC_REG(reg_idx) (REG_OPTIONAL & (1U << (reg_idx)))
> > >
> > > +static bool cpc_integer_entry_valid(unsigned int reg_idx, u64 value)
> > > +{
> > > +     switch (reg_idx) {
> > > +     case HIGHEST_PERF:
> > > +     case NOMINAL_PERF:
> > > +     case LOW_NON_LINEAR_PERF:
> > > +     case LOWEST_PERF:
> > > +     case CTR_WRAP_TIME:
> > > +     case REFERENCE_PERF:
> > > +     case LOWEST_FREQ:
> > > +     case NOMINAL_FREQ:
> > > +             return value <= U32_MAX;
> >
> >
> > Sashiko:
> > "Does this incorrectly restrict the counter wraparound time to 32 bits?
> > The ACPI specification allows firmware to provide a 64-bit QWord integer
> > for the Counter Wraparound Time. The cppc_perf_fb_ctrs structure already
> > models this as a 64-bit value internally
> > If firmware provides a valid 64-bit integer exceeding U32_MAX for this
> > register, cpc_integer_entry_valid() will return false and completely abort
> > CPPC initialization for the CPU. Can we remove this restriction for
> > CTR_WRAP_TIME?"
>
> > This is true. ACPI spec 6.6 and 6.5 (Table 8.23) describe it as
> > Integer (DWORD) or Buffer
> > The 64-bit internal representation is only for the case of firmware
> > providing it as Buffer.

Sashiko is right, the table in the spec is wrong.  If it is Integer,
it is 64-bit.

The size of an Integer in ASL cannot be restricted.

> >
> > > +     case AUTO_SEL_ENABLE:
> > > +             return value <= 1;
> > > +     case DESIRED_PERF:
> > > +             /* Validated against Autonomous Selection after parsing. */
> > > +             return value == 0;
> > > +     default:
> > > +             /* Tolerate the customary Integer 0 for an absent option. */
> > > +             return value == 0 && IS_OPTIONAL_CPC_REG(reg_idx);
> > > +     }
> > > +}
> > > +
> > Sashiko:
> > "Does this incorrectly restrict the counter wraparound time to 32 bits?
> > The ACPI specification allows firmware to provide a 64-bit QWord integer
> > for the Counter Wraparound Time. The cppc_perf_fb_ctrs structure already
> > models this as a 64-bit value internally.
> > If firmware provides a valid 64-bit integer exceeding U32_MAX for this
> > register, cpc_integer_entry_valid() will return false and completely abort
> > CPPC initialization for the CPU. Can we remove this restriction for
> > CTR_WRAP_TIME?"
>
> It looks like you pasted the same comment twice.  Or did Sashiko hallucinate?

Well, its other comment is actually different from the first one.  Let
me paste it:

Will this strict rejection break CPPC initialization on compliant firmware
that provides non-zero integers for other optional capabilities?
For capability registers not explicitly listed in the switch statement
above, such as GUARANTEED_PERF or TIME_WINDOW, the ACPI 6.5 specification
explicitly allows platforms to provide fixed non-zero values encoded as
Integer objects.

When firmware provides a valid non-zero integer for these optional
registers, this default case enforces that the value must be zero. Since
acpi_cppc_processor_probe() fails and returns -EINVAL when this returns
false, it will completely disable cpufreq and CPPC support for the CPU.
Should we allow non-zero integer values for these other optional registers?

> > GUARANTEED_PERF and TIME_WINDOW: both are Buffer-only Register descriptors.
> > Nonzero Integer encodings are invalid and Integer 0 is tolerated because
> > the previous parser allowed it too. I don't know of any platform describing
> > this myself.

Strictly speaking Integer 0 is not allowed, see

https://uefi.org/specs/ACPI/6.6/08_Processor_Configuration_and_Control.html#cpc-continuous-performance-control

> > >  /*
> > >   * Arbitrary Retries in case the remote processor is slow to respond
> > >   * to PCC commands. Keeping it high enough to cover emulators where
> > > @@ -150,6 +188,8 @@ static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
> > >  #define NUM_RETRIES 500ULL
> > >
> > >  #define OVER_16BTS_MASK ~0xFFFFULL
> > > +#define CPC_GENERIC_REGISTER_DESCRIPTOR 0x82
> > > +#define CPC_GENERIC_REGISTER_LENGTH (sizeof(struct cpc_reg) - 3)
> > >
> > >  #define define_one_cppc_ro(_name)            \
> > >  static struct kobj_attribute _name =         \
> > > @@ -773,8 +813,10 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
> > >       acpi_handle handle = pr->handle;
> > >       unsigned int num_ent, i, cpc_rev;
> > >       int pcc_subspace_id = -1;
> > > +     bool cpc_present = false;
> > >       acpi_status status;
> > >       int ret = -ENODATA;
> > > +     int err;
> > >
> > >       if (!osc_sb_cppc2_support_acked) {
> > >               pr_debug("CPPC v2 _OSC not acked\n");
> > > @@ -791,6 +833,8 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
> > >               ret = -ENODEV;
> > >               goto out_buf_free;
> > >       }
> > > +     cpc_present = true;
> > > +     ret = -EINVAL;
> > >
> > >       out_obj = (union acpi_object *) output.pointer;
> > >       if (out_obj->package.count < 2) {
> > > @@ -871,11 +915,32 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
> > >               cpc_obj = &out_obj->package.elements[i];
> > >
> > >               if (cpc_obj->type == ACPI_TYPE_INTEGER) {
> > > -                     cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER;
> > > -                     cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value;
> > > +                     if (!cpc_integer_entry_valid(i - 2,
> > > +                                                  cpc_obj->integer.value)) {
> > > +                             pr_debug("Invalid Integer _CPC register %u for CPU:%d\n",
> > > +                                      i - 2, pr->id);
> > > +                             ret = -EINVAL;
> > > +                             goto out_free;
> > > +                     }
> > > +                     cpc_ptr->cpc_regs[i - 2].type = ACPI_TYPE_INTEGER;
> > > +                     cpc_ptr->cpc_regs[i - 2].cpc_entry.int_value = cpc_obj->integer.value;
> > >               } else if (cpc_obj->type == ACPI_TYPE_BUFFER) {
> > > +                     if (cpc_obj->buffer.length < sizeof(*gas_t)) {
> > > +                             pr_debug("Invalid register descriptor for CPU:%d\n",
> > > +                                      pr->id);
> > > +                             ret = -EINVAL;
> > > +                             goto out_free;
> > > +                     }
> > > +
> > >                       gas_t = (struct cpc_reg *)
> > >                               cpc_obj->buffer.pointer;
> > > +                     if (gas_t->descriptor != CPC_GENERIC_REGISTER_DESCRIPTOR ||
> > > +                         gas_t->length != CPC_GENERIC_REGISTER_LENGTH) {
> > > +                             pr_debug("Invalid register resource for CPU:%d\n",
> > > +                                      pr->id);
> > > +                             ret = -EINVAL;
> > > +                             goto out_free;
> > > +                     }
> > >
> > >                       /*
> > >                        * The PCC Subspace index is encoded inside
> > > @@ -886,8 +951,11 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
> > >                       if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
> > >                               if (pcc_subspace_id < 0) {
> > >                                       pcc_subspace_id = gas_t->access_width;
> > > -                                     if (pcc_data_alloc(pcc_subspace_id))
> > > +                                     err = pcc_data_alloc(pcc_subspace_id);
> > > +                                     if (err) {
> > > +                                             ret = err;
> > >                                               goto out_free;
> > > +                                     }
> > >                               } else if (pcc_subspace_id != gas_t->access_width) {
> > >                                       pr_debug("Mismatched PCC ids in _CPC for CPU:%d\n",
> > >                                                pr->id);
> > > @@ -900,14 +968,18 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
> > >
> > >                                       if (!osc_cpc_flexible_adr_space_confirmed) {
> > >                                               pr_debug("Flexible address space capability not supported\n");
> > > +                                             ret = -EOPNOTSUPP;
> > >                                               if (!cpc_supported_by_cpu())
> > >                                                       goto out_free;
> > > +                                             ret = -EINVAL;
> > >                                       }
> > >
> > >                                       access_width = GET_BIT_WIDTH(gas_t) / 8;
> > >                                       addr = ioremap(gas_t->address, access_width);
> > > -                                     if (!addr)
> > > +                                     if (!addr) {
> > > +                                             ret = -ENOMEM;
> > >                                               goto out_free;
> > > +                                     }
> > >                                       cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr;
> > >                               }
> > >                       } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
> > > @@ -929,14 +1001,17 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
> > >                               }
> > >                               if (!osc_cpc_flexible_adr_space_confirmed) {
> > >                                       pr_debug("Flexible address space capability not supported\n");
> > > +                                     ret = -EOPNOTSUPP;
> > >                                       if (!cpc_supported_by_cpu())
> > >                                               goto out_free;
> > > +                                     ret = -EINVAL;
> > >                               }
> > >                       } else {
> > >                               if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) {
> > >                                       /* Support only PCC, SystemMemory, SystemIO, and FFH type regs. */
> > >                                       pr_debug("Unsupported register type (%d) in _CPC\n",
> > >                                                gas_t->space_id);
> > > +                                     ret = -EOPNOTSUPP;
> > >                                       goto out_free;
> > >                               }
> > >                       }
> > > @@ -961,15 +1036,35 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
> > >       }
> > >       per_cpu(cpu_pcc_subspace_idx, pr->id) = pcc_subspace_id;
> > >
> > > +     /*
> > > +      * Performance Limited is required by the specification, but tolerate a
> > > +      * NULL descriptor used by firmware which cannot report limiting events.
> > > +      * CPPC control does not depend on this status.
> > > +      */
> > > +     for (i = 0; i < num_ent - 2; i++) {
> > > +             if (i != DESIRED_PERF && i != PERF_LIMITED &&
> > > +                 !IS_OPTIONAL_CPC_REG(i) &&
> > > +                 !cpc_entry_present(&cpc_ptr->cpc_regs[i])) {
> > > +                     pr_debug("CPU:%d lacks mandatory _CPC register %u\n",
> > > +                              pr->id, i);
> > > +                     ret = -EINVAL;
> > > +                     goto out_free;
> > > +             }
> > > +     }
> > > +
> > >       /*
> > >        * In CPPC v1, DESIRED_PERF is mandatory. In CPPC v2, it is optional
> > >        * only when AUTO_SEL_ENABLE is supported.
> > >        */
> > > -     if (!CPC_SUPPORTED(&cpc_ptr->cpc_regs[DESIRED_PERF]) &&
> > > +     if (!cpc_is_writable(&cpc_ptr->cpc_regs[DESIRED_PERF]) &&
> > >           (!osc_sb_cppc2_support_acked ||
> > > -          !CPC_SUPPORTED(&cpc_ptr->cpc_regs[AUTO_SEL_ENABLE])))
> > > -             pr_warn("Desired perf. register is mandatory if CPPC v2 is not supported "
> > > -                     "or autonomous selection is disabled\n");
> > > +          cpc_ptr->cpc_regs[AUTO_SEL_ENABLE].type != ACPI_TYPE_INTEGER ||
> > > +          cpc_ptr->cpc_regs[AUTO_SEL_ENABLE].cpc_entry.int_value != 1)) {
> > > +             pr_debug("CPU:%d lacks a writable Desired Performance register\n",
> > > +                      pr->id);
> > > +             ret = -EINVAL;
> > > +             goto out_free;
> > > +     }
> > >
> > >       /*
> > >        * Initialize the remaining cpc_regs as unsupported.
> > > @@ -1037,6 +1132,8 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
> > >       kfree(cpc_ptr);
> > >
> > >  out_buf_free:
> > > +     if (cpc_present)
> > > +             pr_err("CPU%d: failed to initialize _CPC: %d\n", pr->id, ret);
> > >       kfree(output.pointer);
> > >       return ret;
> > >  }
> > > @@ -1217,11 +1314,18 @@ static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
> > >       u64 prev_val;
> > >       void __iomem *vaddr = NULL;
> > >       int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
> > > -     struct cpc_reg *reg = &reg_res->cpc_entry.reg;
> > > +     struct cpc_reg *reg;
> > >       struct cpc_desc *cpc_desc;
> > >       unsigned long flags;
> > >       bool locked = false;
> > >
> > > +     if (reg_res->type != ACPI_TYPE_BUFFER)
> > > +             return -EOPNOTSUPP;
> > > +
> > > +     reg = &reg_res->cpc_entry.reg;
> > > +     if (IS_NULL_REG(reg))
> > > +             return -EOPNOTSUPP;
> > > +
> > >       size = GET_BIT_WIDTH(reg);
> > >
> > >       if (IS_ENABLED(CONFIG_HAS_IOPORT) &&
> > > @@ -1364,7 +1468,9 @@ static int cppc_get_reg_val(int cpu, enum cppc_regs reg_idx, u64 *val)
> > >
> > >       reg = &cpc_desc->cpc_regs[reg_idx];
> > >
> > > -     if ((reg->type == ACPI_TYPE_INTEGER && IS_OPTIONAL_CPC_REG(reg_idx) &&
> > > +     /* Desired may be absent for immutable autonomous selection. */
> > > +     if ((reg->type == ACPI_TYPE_INTEGER &&
> > > +          (IS_OPTIONAL_CPC_REG(reg_idx) || reg_idx == DESIRED_PERF) &&
> > >            !reg->cpc_entry.int_value) || (reg->type != ACPI_TYPE_INTEGER &&
> > >            IS_NULL_REG(&reg->cpc_entry.reg))) {
> > >               pr_debug("CPC register is not supported\n");
> > > @@ -1415,7 +1521,7 @@ static int cppc_set_reg_val(int cpu, enum cppc_regs reg_idx, u64 val)
> > >       reg = &cpc_desc->cpc_regs[reg_idx];
> > >
> > >       /* if a register is writeable, it must be a buffer and not null */
> > > -     if ((reg->type != ACPI_TYPE_BUFFER) || IS_NULL_REG(&reg->cpc_entry.reg)) {
> > > +     if (!cpc_is_writable(reg)) {
> > >               pr_debug("CPC register is not supported\n");
> > >               return -EOPNOTSUPP;
> > >       }
> > > @@ -1505,7 +1611,7 @@ int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
> > >       struct cpc_register_resource *highest_reg, *lowest_reg,
> > >               *lowest_non_linear_reg, *nominal_reg, *reference_reg,
> > >               *guaranteed_reg, *low_freq_reg = NULL, *nom_freq_reg = NULL;
> > > -     u64 high, low, guaranteed, nom, ref, min_nonlinear,
> > > +     u64 high, low, guaranteed = 0, nom, ref, min_nonlinear,
> > >           low_f = 0, nom_f = 0;
> > >       int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
> > >       struct cppc_pcc_data *pcc_ss_data = NULL;
> > > @@ -1588,7 +1694,12 @@ int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
> > >               goto out_err;
> > >       perf_caps->lowest_nonlinear_perf = min_nonlinear;
> > >
> > > -     if (!high || !low || !nom || !ref || !min_nonlinear) {
> > > +     if (!high || !nom || !ref || !min_nonlinear ||
> > > +         high > U32_MAX || low > U32_MAX || guaranteed > U32_MAX ||
> > > +         nom > U32_MAX || ref > U32_MAX || min_nonlinear > U32_MAX ||
> > > +         high < nom || nom < min_nonlinear || min_nonlinear < low ||
> > > +         (CPC_SUPPORTED(guaranteed_reg) &&
> > > +          (guaranteed < low || guaranteed > nom))) {
> > >               ret = -EFAULT;
> > >               goto out_err;
> > >       }
> > > @@ -1605,6 +1716,19 @@ int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
> > >               if (ret)
> > >                       goto out_err;
> > >       }
> > > +     /*
> > > +      * Require ordered anchors and a nonzero slope when frequencies differ.
> > > +      * A zero Lowest Performance needs that affine mapping to produce a
> > > +      * nonzero physical minimum frequency.
> > > +      */
> > > +     if (low_f > U32_MAX || nom_f > U32_MAX ||
> > > +         (!low && (!low_f || !nom_f || low_f == nom_f)) ||
> > > +         (low_f && nom_f &&
> > > +          (nom_f < low_f || nom < low ||
> > > +           (nom_f != low_f && nom == low)))) {
> > > +             ret = -EFAULT;
> > > +             goto out_err;
> > > +     }
> > >
> > >       perf_caps->lowest_freq = low_f;
> > >       perf_caps->nominal_freq = nom_f;
> > > @@ -1779,6 +1903,9 @@ int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable)
> > >
> > >       auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
> > >       epp_set_reg = &cpc_desc->cpc_regs[ENERGY_PERF];
> > > +     if (!enable && auto_sel_reg->type == ACPI_TYPE_INTEGER &&
> > > +         auto_sel_reg->cpc_entry.int_value == 1)
> > > +             return -EOPNOTSUPP;
> > >
> > >       epp_ffh_sysmem = CPC_SUPPORTED(epp_set_reg) &&
> > >               (CPC_IN_FFH(epp_set_reg) || CPC_IN_SYSTEM_MEMORY(epp_set_reg));
> > > @@ -1791,13 +1918,13 @@ int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable)
> > >                       return -ENODEV;
> > >               }
> > >
> > > -             if (CPC_SUPPORTED(auto_sel_reg)) {
> > > +             if (cpc_is_writable(auto_sel_reg)) {
> > >                       ret = cpc_write(cpu, auto_sel_reg, enable);
> > >                       if (ret)
> > >                               return ret;
> > >               }
> > >
> > > -             if (CPC_SUPPORTED(epp_set_reg)) {
> > > +             if (cpc_is_writable(epp_set_reg)) {
> > >                       ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf);
> > >                       if (ret)
> > >                               return ret;
> > > @@ -1996,6 +2123,8 @@ int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
> > >       max_perf_reg = &cpc_desc->cpc_regs[MAX_PERF];
> > >       energy_perf_reg = &cpc_desc->cpc_regs[ENERGY_PERF];
> > >       auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
> > > +     perf_ctrls->max_perf_valid = false;
> > > +     perf_ctrls->min_perf_valid = false;
> > >
> > >       /* Are any of the regs PCC ?*/
> > >       if (CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg) ||
> > > @@ -2020,6 +2149,7 @@ int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
> > >               ret = cpc_read(cpu, max_perf_reg, &max);
> > >               if (ret)
> > >                       goto out_err;
> > > +             perf_ctrls->max_perf_valid = true;
> > >       }
> > >       perf_ctrls->max_perf = max;
> > >
> > > @@ -2027,6 +2157,7 @@ int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
> > >               ret = cpc_read(cpu, min_perf_reg, &min);
> > >               if (ret)
> > >                       goto out_err;
> > > +             perf_ctrls->min_perf_valid = true;
> > >       }
> > >       perf_ctrls->min_perf = min;
> > >
> > > @@ -2113,14 +2244,11 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
> > >       if (CPC_SUPPORTED(desired_reg))
> > >               cpc_write(cpu, desired_reg, perf_ctrls->desired_perf);
> > >
> > > -     /*
> > > -      * Only write if min_perf and max_perf not zero. Some drivers pass zero
> > > -      * value to min and max perf, but they don't mean to set the zero value,
> > > -      * they just don't want to write to those registers.
> > > -      */
> > > -     if (perf_ctrls->min_perf && CPC_SUPPORTED(min_perf_reg))
> > > +     if (CPC_SUPPORTED(min_perf_reg) &&
> > > +         (perf_ctrls->min_perf || perf_ctrls->min_perf_valid))
> > >               cpc_write(cpu, min_perf_reg, perf_ctrls->min_perf);
> > > -     if (perf_ctrls->max_perf && CPC_SUPPORTED(max_perf_reg))
> > > +     if (CPC_SUPPORTED(max_perf_reg) &&
> > > +         (perf_ctrls->max_perf || perf_ctrls->max_perf_valid))
> > >               cpc_write(cpu, max_perf_reg, perf_ctrls->max_perf);
> > >
> > >       if (regs_in_pcc)
> > > diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
> > > index d4ff8b228f86..63f0ca5f19b3 100644
> > > --- a/drivers/cpufreq/amd-pstate.c
> > > +++ b/drivers/cpufreq/amd-pstate.c
> > > @@ -544,7 +544,13 @@ static int shmem_update_perf(struct cpufreq_policy *policy, u8 min_perf,
> > >                            u8 des_perf, u8 max_perf, u8 epp, bool fast_switch)
> > >  {
> > >       struct amd_cpudata *cpudata = policy->driver_data;
> > > -     struct cppc_perf_ctrls perf_ctrls;
> > > +     struct cppc_perf_ctrls perf_ctrls = {
> > > +             .max_perf = max_perf,
> > > +             .min_perf = min_perf,
> > > +             .desired_perf = des_perf,
> > > +             .max_perf_valid = true,
> > > +             .min_perf_valid = true,
> > > +     };
> > >       u64 value, prev;
> > >       int ret;
> > >
> > > @@ -577,10 +583,6 @@ static int shmem_update_perf(struct cpufreq_policy *policy, u8 min_perf,
> > >       if (value == prev)
> > >               return 0;
> > >
> > > -     perf_ctrls.max_perf = max_perf;
> > > -     perf_ctrls.min_perf = min_perf;
> > > -     perf_ctrls.desired_perf = des_perf;
> > > -
> > >       ret = cppc_set_perf(cpudata->cpu, &perf_ctrls);
> > >       if (ret)
> > >               return ret;
> > > diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h
> > > index 94a6277edab2..5dcbe65c5ddc 100644
> > > --- a/include/acpi/cppc_acpi.h
> > > +++ b/include/acpi/cppc_acpi.h
> > > @@ -141,6 +141,8 @@ struct cppc_perf_ctrls {
> > >       u32 desired_perf;
> > >       u32 energy_perf;
> > >       bool auto_sel;
> > > +     bool max_perf_valid;
> > > +     bool min_perf_valid;
> > >  };
> > >
> > >  struct cppc_perf_fb_ctrs {
> >

Re: [PATCH v6 02/15] ACPI: CPPC: Validate _CPC entry and control semantics

[Christian Loehle]

On 9/3/26 20:44, Rafael J. Wysocki (Intel) wrote:
> On Thu, Sep 3, 2026 at 9:27 PM Rafael J. Wysocki (Intel)
> <rafael@kernel.org> wrote:
>>
>> On Sun, Aug 30, 2026 at 3:32 PM Christian Loehle
>> <christian.loehle@arm.com> wrote:
>>>
>>> On 8/30/26 12:56, Christian Loehle wrote:
>>>> Writable _CPC controls are Register descriptors encoded as Buffer objects.
>>>> Integer entries represent fixed values or unsupported optional registers;
>>>> Autonomous Selection Integer 1 is the special immutable form which enables
>>>> operation without Desired Performance.
>>>>
>>>> The parser accepts arbitrary object types and cpc_write() assumes that its
>>>> argument contains a GAS. Malformed firmware can therefore make it interpret
>>>> an Integer union member as a register.
>>>>
>>>> Validate the portion of each encoding consumed by the driver: bound Integer
>>>> DWORD forms to 32 bits, and require Buffer entries to start with a complete
>>>> Generic Register descriptor with the expected header. Continue tolerating
>>>> Integer 0 for an absent optional register and retain type checks in
>>>> cpc_write() as defense in depth. Reject an attempt to disable immutable
>>>> Autonomous Selection instead of silently applying only the EPP part of the
>>>> request.
>>>>
>>>> Capability registers are read into u64 temporaries but exposed through u32
>>>> fields. Reject values above U32_MAX instead of allowing them to be
>>>> truncated. In particular, a truncated Highest Performance value can become
>>>> a zero divisor in the performance-to-frequency conversion. Enforce the
>>>> required ordering from Highest through Nominal, Lowest Nonlinear, and
>>>> Lowest Performance, and constrain a present Guaranteed Performance to the
>>>> inclusive Lowest-to-Nominal range. Also reject reversed frequency anchors
>>>> and unequal frequency anchors with identical performance anchors. Those
>>>> invalid tuples otherwise make affine-conversion differences wrap or divide
>>>> by zero.
>>>>
>>>> Check mandatory object presence separately from the Integer-zero convention
>>>> for absent optional fields. ACPI does not reserve zero in the abstract
>>>> Lowest Performance scale, so accept a present Lowest Performance DWORD of
>>>> zero when distinct frequency anchors provide a usable nonzero physical
>>>> minimum. Retain the old rejection when that mapping is unavailable and the
>>>> fallback conversion would expose a 0 kHz cpufreq endpoint.
>>>>
>>>> Minimum Performance also defines zero as a real no-limit value, but the
>>>> exported cppc_set_perf() interface historically used zero to omit a bound.
>>>> Add explicit validity flags so callers can request zero without changing
>>>> that legacy convention. Populate the flags when reading the controls and
>>>> mark the bounds supplied by amd-pstate explicitly.
>>>>
>>>> Performance Limited is listed as a required Buffer, but the interface does
>>>> not depend on it to control performance and the specification permits a
>>>> platform with no limiting indication to always report zero. Preserve
>>>> the compatibility with firmware that represents that case using a NULL
>>>> register descriptor instead of disabling CPPC entirely.
>>>>
>>>> Emit an error when a present _CPC package fails parsing or initialization
>>>> so such firmware and resource failures no longer silently suppress cpufreq.
>>>> Initialize malformed-package failures to -EINVAL and preserve specific
>>>> allocation, mapping, and unsupported-access errors in that diagnostic.
>>>>
>>>> Fixes: 337aadff8e45 ("ACPI: Introduce CPU performance controls using CPPC")
>>>> Reported-by: Sashiko <sashiko-bot@kernel.org>
>>>> Link: https://sashiko.dev/#/patchset/20260724134251.1632824-1-christian.loehle%40arm.com
>>>> Signed-off-by: Christian Loehle <christian.loehle@arm.com>
>>>> ---
>>>>  drivers/acpi/cppc_acpi.c     | 172 ++++++++++++++++++++++++++++++-----
>>>>  drivers/cpufreq/amd-pstate.c |  12 ++-
>>>>  include/acpi/cppc_acpi.h     |   2 +
>>>>  3 files changed, 159 insertions(+), 27 deletions(-)
>>>>
>>>> diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
>>>> index 3b8cdf88e31d..6f3ffa4a1845 100644
>>>> --- a/drivers/acpi/cppc_acpi.c
>>>> +++ b/drivers/acpi/cppc_acpi.c
>>>> @@ -129,6 +129,21 @@ static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
>>>>                               !!(cpc)->cpc_entry.int_value :          \
>>>>                               !IS_NULL_REG(&(cpc)->cpc_entry.reg))
>>>>
>>>> +static bool cpc_is_writable(const struct cpc_register_resource *cpc)
>>>> +{
>>>> +     return cpc->type == ACPI_TYPE_BUFFER &&
>>>> +            !IS_NULL_REG(&cpc->cpc_entry.reg);
>>>> +}
>>>> +
>>>> +static bool cpc_entry_present(const struct cpc_register_resource *cpc)
>>>> +{
>>>> +     if (cpc->type == ACPI_TYPE_INTEGER)
>>>> +             return true;
>>>> +
>>>> +     return cpc->type == ACPI_TYPE_BUFFER &&
>>>> +            !IS_NULL_REG(&cpc->cpc_entry.reg);
>>>> +}
>>>> +
>>>>  /*
>>>>   * Each bit indicates the optionality of the register in per-cpu
>>>>   * cpc_regs[] with the corresponding index. 0 means mandatory and 1
>>>> @@ -142,6 +157,29 @@ static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
>>>>   */
>>>>  #define IS_OPTIONAL_CPC_REG(reg_idx) (REG_OPTIONAL & (1U << (reg_idx)))
>>>>
>>>> +static bool cpc_integer_entry_valid(unsigned int reg_idx, u64 value)
>>>> +{
>>>> +     switch (reg_idx) {
>>>> +     case HIGHEST_PERF:
>>>> +     case NOMINAL_PERF:
>>>> +     case LOW_NON_LINEAR_PERF:
>>>> +     case LOWEST_PERF:
>>>> +     case CTR_WRAP_TIME:
>>>> +     case REFERENCE_PERF:
>>>> +     case LOWEST_FREQ:
>>>> +     case NOMINAL_FREQ:
>>>> +             return value <= U32_MAX;
>>>
>>>
>>> Sashiko:
>>> "Does this incorrectly restrict the counter wraparound time to 32 bits?
>>> The ACPI specification allows firmware to provide a 64-bit QWord integer
>>> for the Counter Wraparound Time. The cppc_perf_fb_ctrs structure already
>>> models this as a 64-bit value internally
>>> If firmware provides a valid 64-bit integer exceeding U32_MAX for this
>>> register, cpc_integer_entry_valid() will return false and completely abort
>>> CPPC initialization for the CPU. Can we remove this restriction for
>>> CTR_WRAP_TIME?"
>>
>>> This is true. ACPI spec 6.6 and 6.5 (Table 8.23) describe it as
>>> Integer (DWORD) or Buffer
>>> The 64-bit internal representation is only for the case of firmware
>>> providing it as Buffer.
> 
> Sashiko is right, the table in the spec is wrong.  If it is Integer,
> it is 64-bit.
> 
> The size of an Integer in ASL cannot be restricted.

Duh, thanks!

> 
>>>
>>>> +     case AUTO_SEL_ENABLE:
>>>> +             return value <= 1;
>>>> +     case DESIRED_PERF:
>>>> +             /* Validated against Autonomous Selection after parsing. */
>>>> +             return value == 0;
>>>> +     default:
>>>> +             /* Tolerate the customary Integer 0 for an absent option. */
>>>> +             return value == 0 && IS_OPTIONAL_CPC_REG(reg_idx);
>>>> +     }
>>>> +}
>>>> +
>>> Sashiko:
>>> "Does this incorrectly restrict the counter wraparound time to 32 bits?
>>> The ACPI specification allows firmware to provide a 64-bit QWord integer
>>> for the Counter Wraparound Time. The cppc_perf_fb_ctrs structure already
>>> models this as a 64-bit value internally.
>>> If firmware provides a valid 64-bit integer exceeding U32_MAX for this
>>> register, cpc_integer_entry_valid() will return false and completely abort
>>> CPPC initialization for the CPU. Can we remove this restriction for
>>> CTR_WRAP_TIME?"
>>
>> It looks like you pasted the same comment twice.  Or did Sashiko hallucinate?
> 
> Well, its other comment is actually different from the first one.  Let
> me paste it:

Apparently I hallucinated :)

> 
> Will this strict rejection break CPPC initialization on compliant firmware
> that provides non-zero integers for other optional capabilities?
> For capability registers not explicitly listed in the switch statement
> above, such as GUARANTEED_PERF or TIME_WINDOW, the ACPI 6.5 specification
> explicitly allows platforms to provide fixed non-zero values encoded as
> Integer objects.
> 
> When firmware provides a valid non-zero integer for these optional
> registers, this default case enforces that the value must be zero. Since
> acpi_cppc_processor_probe() fails and returns -EINVAL when this returns
> false, it will completely disable cpufreq and CPPC support for the CPU.
> Should we allow non-zero integer values for these other optional registers?
> 
>>> GUARANTEED_PERF and TIME_WINDOW: both are Buffer-only Register descriptors.
>>> Nonzero Integer encodings are invalid and Integer 0 is tolerated because
>>> the previous parser allowed it too. I don't know of any platform describing
>>> this myself.
> 
> Strictly speaking Integer 0 is not allowed, see
> 
> https://uefi.org/specs/ACPI/6.6/08_Processor_Configuration_and_Control.html#cpc-continuous-performance-control

I'm happy to reject it too, I was just being careful here because I only have
a tiny subset of ACPI platforms to test this on with and it's for -fixes

> [snip]