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* [PATCH v4 0/2] Unfiy PCI suspend and hibernate paths
@ 2026-09-16  5:10 Mario Limonciello
  2026-09-16  5:10 ` [PATCH v4 1/2] PCI/PM: Split out code from pci_pm_suspend_noirq() into helper Mario Limonciello
  2026-09-16  5:10 ` [PATCH v4 2/2] PCI: Put PCIe bridges with downstream devices into D3 at hibernate Mario Limonciello
  0 siblings, 2 replies; 5+ messages in thread
From: Mario Limonciello @ 2026-09-16  5:10 UTC (permalink / raw)
  To: Bjorn Helgaas
  Cc: open list:PCI SUBSYSTEM, open list, Rafael J . Wysocki,
	Lukas Wunner, linux-pm, Mario Limonciello

Many cycles ago I sent out a kernel series for using the S4 paths when
the system goes to S5.  Some parts of it got merged, and Rafael suggested
to split the other parts into smaller pieces across multiple kernel cycles
to make bisecting easier.

This series attempts to unify the PCI suspend and hibernate paths so that
PCIe bridges with downstream devices are put into D3 at hibernate the same
way they already are at S3 suspend.  I have been carrying it, rebasing it
and personally using it for a while now.

v4:
 - Change pci_pm_suspend_noirq_common() to bool (Rafael)
 - Drop patch 2/3 from v3, mostly dead code (Sashiko)
 - Rework patch 3/3 from v3 (Sashiko)

Mario Limonciello (AMD) (2):
  PCI/PM: Split out code from pci_pm_suspend_noirq() into helper
  PCI: Put PCIe bridges with downstream devices into D3 at hibernate

 drivers/pci/pci-driver.c | 86 ++++++++++++++++++++++++++--------------
 1 file changed, 56 insertions(+), 30 deletions(-)

-- 
2.43.0


^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2026-09-16 13:57 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-09-16  5:10 [PATCH v4 0/2] Unfiy PCI suspend and hibernate paths Mario Limonciello
2026-09-16  5:10 ` [PATCH v4 1/2] PCI/PM: Split out code from pci_pm_suspend_noirq() into helper Mario Limonciello
2026-09-16 13:49   ` Rafael J. Wysocki (Intel)
2026-09-16  5:10 ` [PATCH v4 2/2] PCI: Put PCIe bridges with downstream devices into D3 at hibernate Mario Limonciello
2026-09-16 13:56   ` Rafael J. Wysocki (Intel)

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