[PATCH DNI v3 00/15] media: rcar-fcp, vsp1: Enable on R-Car X5H

[PATCH DNI v3 00/15] media: rcar-fcp, vsp1: Enable on R-Car X5H

[Paul Elder]

This series is based on Geert's
"topic/rcar-x5h-ironhide-scmi-cpg-mdlc-remapping-v3" branch [0]. A
branch including this series is available here [1].

This series enables the FCPV{B,I,D} and the VSP{B,I,D} blocks on the Renesas
R-Car X5H SoC.

This has been tested on an Ironhide with the vsp-tests test suite [2].

Full summary:
/dev/media0 (VSP2-D (a)): 114 tests: 99 passed, 0 failed, 15 skipped
/dev/media1 (VSP2-D (a)): 114 tests: 99 passed, 0 failed, 15 skipped
/dev/media10 (VSP2-I): 157 tests: 150 passed, 0 failed, 7 skipped
/dev/media11 (VSP2-I): 157 tests: 150 passed, 0 failed, 7 skipped
/dev/media12 (VSP2-I): 157 tests: 150 passed, 0 failed, 7 skipped
/dev/media13 (VSP2-I): 157 tests: 150 passed, 0 failed, 7 skipped
/dev/media14 (VSP2-B): 127 tests: 116 passed, 0 failed, 11 skipped
/dev/media15 (VSP2-B): 127 tests: 116 passed, 0 failed, 11 skipped
/dev/media16 (VSP2-B): 127 tests: 116 passed, 0 failed, 11 skipped
/dev/media17 (VSP2-B): 127 tests: 116 passed, 0 failed, 11 skipped
/dev/media18 (VSP2-B): 127 tests: 116 passed, 0 failed, 11 skipped
/dev/media2 (VSP2-D (a)): 114 tests: 99 passed, 0 failed, 15 skipped
/dev/media3 (VSP2-D (a)): 114 tests: 99 passed, 0 failed, 15 skipped
/dev/media4 (VSP2-D (a)): 114 tests: 99 passed, 0 failed, 15 skipped
/dev/media5 (VSP2-D (b)): 114 tests: 99 passed, 0 failed, 15 skipped
/dev/media6 (VSP2-D (b)): 114 tests: 99 passed, 0 failed, 15 skipped
/dev/media7 (VSP2-D (b)): 114 tests: 99 passed, 0 failed, 15 skipped
/dev/media8 (VSP2-D (b)): 114 tests: 99 passed, 0 failed, 15 skipped
/dev/media9 (VSP2-D (b)): 114 tests: 99 passed, 0 failed, 15 skipped

The first couple patches add clocks that are used by the FCP and VSP,
but as the upstream X5H CPG driver is barebones at the moment and we
don't yet ensure that the parents are enabled, these are marked as DNI
for the moment.

The last patch checks the device revision and prints it, which is useful
for debugging but is unnecessary processing for driver operation so it
is marked as DNI as well.

In v3, most of the patches have become DNI because they depend on wip
cpg and mdlc driver work. The non-DNI patches are targets for immediate
upstreaming though.

There was some odd behavior with the clocks, where from what I
understood was that the clocks for the FCPV{B,I} and VSP{B,I} are
always-on, but the tests would hang unless I explicitly enabled...  the
always-on clock (or fsleep). Then after I removed the patch that
explicitly enabled the always-on clock everything ran fine. Just
reporting that this happened just in case it's relevant.

[0] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git/log/?h=topic/rcar-x5h-ironhide-scmi-cpg-mdlc-remapping-v3
[1] https://git.ideasonboard.com/epaul/linux/src/branch/epaul/v7.3-rc1/x5h/vsp/fcp-v3
[2] https://git.ideasonboard.com/renesas/vsp-tests/src/branch/epaul/fix

Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
---
Changes in v3:
- Added a couple bsp patches for upstreaming
- Marked dt patches as DNI
- Fix some VSPD instances hanging
- Update dt-bindings documentation for the expanded module identifier
  bit width
- Link to v2: https://lore.kernel.org/r/20260919-epaul-v7-3-rc1-x5h-vsp-fcp-v2-0-dbe9236bfd22@ideasonboard.com

Changes in v2:
- Add FCPVD and VSPD
- Fixed author (I mistakenly overwrote a few when I renamed my email)
- Link to v1: https://lore.kernel.org/r/20260917-epaul-v7-3-rc1-x5h-vsp-fcp-v1-0-4c72d4e086dd@ideasonboard.com

---
Laurent Pinchart (3):
      [DNI] arm64: renesas: r8a78000: Add VSP[BI] nodes
      media: vsp1: Support full VSPB on R-Car M3-W, M3-N and E3
      [DNI] media: rcar-fcp: Check device revision at probe time

Paul Elder (9):
      [DNI] dt-bindings: clock: renesas,r8a78000-cpg: Add CPG_SGD4_VIO_DP_{TX,OTHER}
      [DNI] clk: renesas: r8a78000: Add clock for FCPV and VSP for SCP FW SDKv4.36
      [DNI] pmdomain: renesas: r8a78000: Add maps for VIO for SCP FW SDKv4.36
      [DNI] arm64: renesas: r8a78000: Add FCPV[BI] nodes
      [DNI] arm64: renesas: r8a78000: Add FCPVD and VSPD nodes
      media: vsp1: Add device info entries for VSPD on X5H
      media: rcar-fcp: Handle resets
      dt-bindings: Increase Renesas X5H MDLC PD specifier bit width
      media: vsp1: Complete buffers as queued in start_streaming error path

Phong Hoang (3):
      media: vsp1: Fix access to reserved registers
      media: vsp1: Fix du_complete race condition issue
      media: vsp1: Fix setting control register by display list

 .../bindings/power/renesas,r8a78000-mdlc.yaml      |   7 +-
 arch/arm64/boot/dts/renesas/r8a78000.dtsi          | 361 +++++++++++++++++++++
 drivers/clk/renesas/r8a78000-cpg.c                 |   2 +
 drivers/media/platform/renesas/rcar-fcp.c          | 158 ++++++++-
 drivers/media/platform/renesas/vsp1/vsp1_drm.c     |  10 +-
 drivers/media/platform/renesas/vsp1/vsp1_drv.c     |  74 ++++-
 drivers/media/platform/renesas/vsp1/vsp1_regs.h    |   4 +-
 drivers/media/platform/renesas/vsp1/vsp1_video.c   |   9 +-
 drivers/media/platform/renesas/vsp1/vsp1_wpf.c     |   5 +-
 drivers/pmdomain/renesas/r8a78000-mdlc.c           |  54 ++-
 include/dt-bindings/clock/renesas,r8a78000-cpg.h   |   2 +
 11 files changed, 647 insertions(+), 39 deletions(-)
---
base-commit: b97eed181007d4d71116add157a5dfa50c76dc72
change-id: 20260917-epaul-v7-3-rc1-x5h-vsp-fcp-8afdeb2740f7

Best regards,
-- 
Paul Elder <paul.elder+renesas@ideasonboard.com>

[PATCH DNI v3 01/15] dt-bindings: clock: renesas,r8a78000-cpg: Add CPG_SGD4_VIO_DP_{TX,OTHER}

[Paul Elder]

Add the CPG_SGD4_VIO_DP_TX and CPG_SGD4_VIO_DP_OTHER clocks. The former
is used by FCPV{B,D,I} and VSPD while the latter is used by VSP{B,I} on
the Renesas R-Car X5H.

Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
---
 include/dt-bindings/clock/renesas,r8a78000-cpg.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/dt-bindings/clock/renesas,r8a78000-cpg.h b/include/dt-bindings/clock/renesas,r8a78000-cpg.h
index 5851a29847f961b9b4ec270f263eb3aa19e45308..8c1a01e28ddbb26c583d7c9b387400ef6626c06c 100644
--- a/include/dt-bindings/clock/renesas,r8a78000-cpg.h
+++ b/include/dt-bindings/clock/renesas,r8a78000-cpg.h
@@ -12,5 +12,7 @@
 #define R8A78000_CPG_SGASYNCD16_PERW_BUS	2
 #define R8A78000_CPG_S0D4_PERE_MAIN		3	// FIXME Preliminary
 #define R8A78000_CPG_MSOCK_PERW_BUS		4	// FIXME Preliminary
+#define R8A78000_CPG_SGD4_VIO_DP_TX		5	// FIXME Preliminary
+#define R8A78000_CPG_SGD4_VIO_DP_OTHER		6	// FIXME Preliminary
 
 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A78000_CPG_H__ */

-- 
2.47.3

Re: [PATCH DNI v3 01/15] dt-bindings: clock: renesas,r8a78000-cpg: Add CPG_SGD4_VIO_DP_{TX,OTHER}

[Laurent Pinchart]

Hi Paul,

Thank you for the patch.

On Thu, Oct 15, 2026 at 04:51:41PM +0900, Paul Elder wrote:
> Add the CPG_SGD4_VIO_DP_TX and CPG_SGD4_VIO_DP_OTHER clocks. The former
> is used by FCPV{B,D,I} and VSPD while the latter is used by VSP{B,I} on
> the Renesas R-Car X5H.

The comment message should probably be updated based on the discussion
in 04/15.

> Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
> ---
>  include/dt-bindings/clock/renesas,r8a78000-cpg.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/include/dt-bindings/clock/renesas,r8a78000-cpg.h b/include/dt-bindings/clock/renesas,r8a78000-cpg.h
> index 5851a29847f961b9b4ec270f263eb3aa19e45308..8c1a01e28ddbb26c583d7c9b387400ef6626c06c 100644
> --- a/include/dt-bindings/clock/renesas,r8a78000-cpg.h
> +++ b/include/dt-bindings/clock/renesas,r8a78000-cpg.h
> @@ -12,5 +12,7 @@
>  #define R8A78000_CPG_SGASYNCD16_PERW_BUS	2
>  #define R8A78000_CPG_S0D4_PERE_MAIN		3	// FIXME Preliminary
>  #define R8A78000_CPG_MSOCK_PERW_BUS		4	// FIXME Preliminary
> +#define R8A78000_CPG_SGD4_VIO_DP_TX		5	// FIXME Preliminary
> +#define R8A78000_CPG_SGD4_VIO_DP_OTHER		6	// FIXME Preliminary

Rebasing the next version on top of Geert's v4 of the CPG, those won't
be preliminary any more \o/

Please define all SGD clocks in one go (see the discussion in [1]).

[1] https://lore.kernel.org/all/e723696e02cfb34fb808e2ae3ccb6faf68528c00.1793026273.git.geert+renesas@glider.be

>  
>  #endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A78000_CPG_H__ */
> 

-- 
Regards,

Laurent Pinchart

[PATCH DNI v3 02/15] clk: renesas: r8a78000: Add clock for FCPV and VSP for SCP FW SDKv4.36

[Paul Elder]

Add clocks for the FCPV{B,D,I} and VSP{B,D, I}. They each have one clock
from an option of two: a 1066MHz and a quarter-divided 266MHz. As we
already have support for the 266MHz one, add just those for now.

Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
---
 drivers/clk/renesas/r8a78000-cpg.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/renesas/r8a78000-cpg.c b/drivers/clk/renesas/r8a78000-cpg.c
index b820d09e1a195068debe8a6eea7a01c534a97b23..17792ff6ab8ae2f7eb5c8f7e3d581b43177e195d 100644
--- a/drivers/clk/renesas/r8a78000-cpg.c
+++ b/drivers/clk/renesas/r8a78000-cpg.c
@@ -326,6 +326,8 @@ static const struct clk_map_in r8a78000_cpg_fw_4_31_0[] = {
 	{ R8A78000_CPG_SGASYNCD16_PERW_BUS,	FIXED_CLK(66M) },
 	{ R8A78000_CPG_S0D4_PERE_MAIN,		FIXED_CLK(200M) },
 	{ R8A78000_CPG_MSOCK_PERW_BUS,		1667 },
+	{ R8A78000_CPG_SGD4_VIO_DP_TX,		FIXED_CLK(266M)},
+	{ R8A78000_CPG_SGD4_VIO_DP_OTHER,	FIXED_CLK(266M)},
 	{ -1 }
 };
 

-- 
2.47.3

[PATCH DNI v3 03/15] pmdomain: renesas: r8a78000: Add maps for VIO for SCP FW SDKv4.36

[Paul Elder]

Add maps for VIO for the VSP and FCP power domains and reset domains.

Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>

---
Changes in v2:
- add VSPD and FCPVD
---
 drivers/pmdomain/renesas/r8a78000-mdlc.c | 54 ++++++++++++++++++++++++++++++--
 1 file changed, 52 insertions(+), 2 deletions(-)

diff --git a/drivers/pmdomain/renesas/r8a78000-mdlc.c b/drivers/pmdomain/renesas/r8a78000-mdlc.c
index a0d83f27735e7deacb060e4102e510726b34e62e..cabe6435ecd791e358fd6987ce9394898d8c87f8 100644
--- a/drivers/pmdomain/renesas/r8a78000-mdlc.c
+++ b/drivers/pmdomain/renesas/r8a78000-mdlc.c
@@ -861,6 +861,56 @@ static const struct mdlc_info r8a78000_mdlc_fw_4_28_0[] = {
 	{ /* sentinel */ }
 };
 
+static const struct power_map_in r8a78000_mdlc_vio_power_fw_4_31_0[] = {
+	{ 0, 4 },	/* PD_VIO0 */
+	{ 1, 5 },	/* PD_VIO1 */
+	{ 2, 6 },	/* PD_VIO2 */
+	{ 3, 7 },	/* PD_VIO3 */
+	{ 7, 11 },	/* PD_VIO4 */
+	{ -1 }
+};
+static const struct mod_map_in r8a78000_mdlc_vio_mod_fw_4_31_0[] = {
+	{ 0x70, 26 },	/* VSPD0 */
+	{ 0x71, 27 },	/* VSPD1 */
+	{ 0x72, 28 },	/* VSPD2 */
+	{ 0x73, 29 },	/* VSPD3 */
+	{ 0x74, 30 },	/* VSPD4 */
+	{ 0x75, 31 },	/* VSPDB0 */
+	{ 0x76, 32 },	/* VSPDB1 */
+	{ 0x77, 33 },	/* VSPDB2 */
+	{ 0x78, 34 },	/* VSPDB3 */
+	{ 0x79, 35 },	/* VSPDB4 */
+	{ 0x7e, 40 },	/* FCPVD0 */
+	{ 0x7f, 41 },	/* FCPVD1 */
+	{ 0x80, 42 },	/* FCPVD2 */
+	{ 0x81, 43 },	/* FCPVD3 */
+	{ 0x82, 44 },	/* FCPVD4 */
+	{ 0x83, 45 },	/* FCPVD5 */
+	{ 0x84, 46 },	/* FCPVD6 */
+	{ 0x85, 47 },	/* FCPVD7 */
+	{ 0x86, 48 },	/* FCPVD8 */
+	{ 0x87, 49 },	/* FCPVD9 */
+	{ 0xf9, 163 },	/* VSPB0 */
+	{ 0xfa, 164 },	/* VSPB1 */
+	{ 0xfb, 165 },	/* VSPB2 */
+	{ 0xfc, 166 },	/* VSPB3 */
+	{ 0xfd, 167 },	/* VSPB4 */
+	{ 0xfe, 168 },	/* VSPI0 */
+	{ 0xff, 169 },	/* VSPI1 */
+	{ 0x100, 170 },	/* VSPI2 */
+	{ 0x101, 171 },	/* VSPI3 */
+	{ 0x102, 172 },	/* FCPVB0 */
+	{ 0x103, 173 },	/* FCPVB1 */
+	{ 0x104, 174 },	/* FCPVB2 */
+	{ 0x105, 175 },	/* FCPVB3 */
+	{ 0x106, 176 },	/* FCPVB4 */
+	{ 0x107, 177 },	/* FCPVI0 */
+	{ 0x108, 178 },	/* FCPVI1 */
+	{ 0x109, 179 },	/* FCPVI2 */
+	{ 0x10a, 180 },	/* FCPVI3 */
+	{ -1 }
+};
+
 static const struct mod_map_in r8a78000_mdlc_pere_mod_fw_4_31_0[] = {
 	{ 0x30, 193 },	/* PERE_GPIODM0 */
 	// No CLOCK_ATTRIBUTES { 0x31, 194 },	/* PERE_GPIODM1 */
@@ -997,8 +1047,8 @@ static const struct mdlc_info r8a78000_mdlc_fw_4_31_0[] = {
 		/* FIXME .mod_map = r8a78000_mdlc_vips_mod_fw_4_31_0, */
 	}, {
 		.base = 0xc5000000 /* mdlc_vio */,
-		/* FIXME .power_map = r8a78000_mdlc_vio_power_fw_4_28_0, */
-		/* FIXME .mod_map = r8a78000_mdlc_vio_mod_fw_4_31_0, */
+		.power_map = r8a78000_mdlc_vio_power_fw_4_31_0,
+		.mod_map = r8a78000_mdlc_vio_mod_fw_4_31_0,
 	}, {
 		.base = 0xc08f0000 /* mdlc_pere */,
 		.power_map = r8a78000_mdlc_pere_power_fw_4_28_0,

-- 
2.47.3

Re: [PATCH DNI v3 03/15] pmdomain: renesas: r8a78000: Add maps for VIO for SCP FW SDKv4.36

[Laurent Pinchart]

On Thu, Oct 15, 2026 at 04:51:43PM +0900, Paul Elder wrote:
> Add maps for VIO for the VSP and FCP power domains and reset domains.

s/reset domains/module control/ as its not just reset (and there's no
"reset domain") but also module control clock ?

> 
> Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
> 
> ---
> Changes in v2:
> - add VSPD and FCPVD
> ---
>  drivers/pmdomain/renesas/r8a78000-mdlc.c | 54 ++++++++++++++++++++++++++++++--
>  1 file changed, 52 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pmdomain/renesas/r8a78000-mdlc.c b/drivers/pmdomain/renesas/r8a78000-mdlc.c
> index a0d83f27735e7deacb060e4102e510726b34e62e..cabe6435ecd791e358fd6987ce9394898d8c87f8 100644
> --- a/drivers/pmdomain/renesas/r8a78000-mdlc.c
> +++ b/drivers/pmdomain/renesas/r8a78000-mdlc.c
> @@ -861,6 +861,56 @@ static const struct mdlc_info r8a78000_mdlc_fw_4_28_0[] = {
>  	{ /* sentinel */ }
>  };
>  
> +static const struct power_map_in r8a78000_mdlc_vio_power_fw_4_31_0[] = {
> +	{ 0, 4 },	/* PD_VIO0 */
> +	{ 1, 5 },	/* PD_VIO1 */
> +	{ 2, 6 },	/* PD_VIO2 */
> +	{ 3, 7 },	/* PD_VIO3 */
> +	{ 7, 11 },	/* PD_VIO4 */
> +	{ -1 }
> +};
> +static const struct mod_map_in r8a78000_mdlc_vio_mod_fw_4_31_0[] = {
> +	{ 0x70, 26 },	/* VSPD0 */
> +	{ 0x71, 27 },	/* VSPD1 */
> +	{ 0x72, 28 },	/* VSPD2 */
> +	{ 0x73, 29 },	/* VSPD3 */
> +	{ 0x74, 30 },	/* VSPD4 */
> +	{ 0x75, 31 },	/* VSPDB0 */
> +	{ 0x76, 32 },	/* VSPDB1 */
> +	{ 0x77, 33 },	/* VSPDB2 */
> +	{ 0x78, 34 },	/* VSPDB3 */
> +	{ 0x79, 35 },	/* VSPDB4 */
> +	{ 0x7e, 40 },	/* FCPVD0 */
> +	{ 0x7f, 41 },	/* FCPVD1 */
> +	{ 0x80, 42 },	/* FCPVD2 */
> +	{ 0x81, 43 },	/* FCPVD3 */
> +	{ 0x82, 44 },	/* FCPVD4 */
> +	{ 0x83, 45 },	/* FCPVD5 */
> +	{ 0x84, 46 },	/* FCPVD6 */
> +	{ 0x85, 47 },	/* FCPVD7 */
> +	{ 0x86, 48 },	/* FCPVD8 */
> +	{ 0x87, 49 },	/* FCPVD9 */
> +	{ 0xf9, 163 },	/* VSPB0 */
> +	{ 0xfa, 164 },	/* VSPB1 */
> +	{ 0xfb, 165 },	/* VSPB2 */
> +	{ 0xfc, 166 },	/* VSPB3 */
> +	{ 0xfd, 167 },	/* VSPB4 */
> +	{ 0xfe, 168 },	/* VSPI0 */
> +	{ 0xff, 169 },	/* VSPI1 */
> +	{ 0x100, 170 },	/* VSPI2 */
> +	{ 0x101, 171 },	/* VSPI3 */
> +	{ 0x102, 172 },	/* FCPVB0 */
> +	{ 0x103, 173 },	/* FCPVB1 */
> +	{ 0x104, 174 },	/* FCPVB2 */
> +	{ 0x105, 175 },	/* FCPVB3 */
> +	{ 0x106, 176 },	/* FCPVB4 */
> +	{ 0x107, 177 },	/* FCPVI0 */
> +	{ 0x108, 178 },	/* FCPVI1 */
> +	{ 0x109, 179 },	/* FCPVI2 */
> +	{ 0x10a, 180 },	/* FCPVI3 */

The values look fine. After rebasing the MDLC v4 from Geert,

Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

> +	{ -1 }
> +};
> +
>  static const struct mod_map_in r8a78000_mdlc_pere_mod_fw_4_31_0[] = {
>  	{ 0x30, 193 },	/* PERE_GPIODM0 */
>  	// No CLOCK_ATTRIBUTES { 0x31, 194 },	/* PERE_GPIODM1 */
> @@ -997,8 +1047,8 @@ static const struct mdlc_info r8a78000_mdlc_fw_4_31_0[] = {
>  		/* FIXME .mod_map = r8a78000_mdlc_vips_mod_fw_4_31_0, */
>  	}, {
>  		.base = 0xc5000000 /* mdlc_vio */,
> -		/* FIXME .power_map = r8a78000_mdlc_vio_power_fw_4_28_0, */
> -		/* FIXME .mod_map = r8a78000_mdlc_vio_mod_fw_4_31_0, */
> +		.power_map = r8a78000_mdlc_vio_power_fw_4_31_0,
> +		.mod_map = r8a78000_mdlc_vio_mod_fw_4_31_0,
>  	}, {
>  		.base = 0xc08f0000 /* mdlc_pere */,
>  		.power_map = r8a78000_mdlc_pere_power_fw_4_28_0,

-- 
Regards,

Laurent Pinchart

[PATCH DNI v3 04/15] arm64: renesas: r8a78000: Add FCPV[BI] nodes

[Paul Elder]

Add DT nodes for the FCPVB and FCPVI IP cores in the R-Car X5H SoC.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
 arch/arm64/boot/dts/renesas/r8a78000.dtsi | 72 +++++++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
index 9a07753b221541ed49a975e0c95f2f5d1fdc6ac2..2f8886f8b6545026397fd83969882f8c62afa9d3 100644
--- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
@@ -1000,6 +1000,78 @@ mdlc_aon: system-controller@c1338000 {
 			bootph-all;
 		};
 
+		fcpvi0: fcp@c5030000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5030000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x107>;
+			resets = <&mdlc_vio 0x107>;
+		};
+
+		fcpvi1: fcp@c5031000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5031000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x108>;
+			resets = <&mdlc_vio 0x108>;
+		};
+
+		fcpvi2: fcp@c5032000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5032000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x109>;
+			resets = <&mdlc_vio 0x109>;
+		};
+
+		fcpvi3: fcp@c5033000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5033000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x10a>;
+			resets = <&mdlc_vio 0x10a>;
+		};
+
+		fcpvb0: fcp@c5038000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5038000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x102>;
+			resets = <&mdlc_vio 0x102>;
+		};
+
+		fcpvb1: fcp@c5039000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5039000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x103>;
+			resets = <&mdlc_vio 0x103>;
+		};
+
+		fcpvb2: fcp@c503a000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc503a000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x104>;
+			resets = <&mdlc_vio 0x104>;
+		};
+
+		fcpvb3: fcp@c503b000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc503b000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x105>;
+			resets = <&mdlc_vio 0x105>;
+		};
+
+		fcpvb4: fcp@c503c000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc503c000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x106>;
+			resets = <&mdlc_vio 0x106>;
+		};
+
 		mdlc_cmnn: system-controller@ca410000 {
 			compatible = "renesas,r8a78000-mdlc";
 			reg = <0 0xca410000 0 0x1000>;

-- 
2.47.3

Re: [PATCH DNI v3 04/15] arm64: renesas: r8a78000: Add FCPV[BI] nodes

[Laurent Pinchart]

Hi Paul,

Thank you for the patch.

On Thu, Oct 15, 2026 at 04:51:44PM +0900, Paul Elder wrote:
> Add DT nodes for the FCPVB and FCPVI IP cores in the R-Car X5H SoC.
> 
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

I need to reconsider this...

> Tested-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> ---
>  arch/arm64/boot/dts/renesas/r8a78000.dtsi | 72 +++++++++++++++++++++++++++++++
>  1 file changed, 72 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> index 9a07753b221541ed49a975e0c95f2f5d1fdc6ac2..2f8886f8b6545026397fd83969882f8c62afa9d3 100644
> --- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> @@ -1000,6 +1000,78 @@ mdlc_aon: system-controller@c1338000 {
>  			bootph-all;
>  		};
>  
> +		fcpvi0: fcp@c5030000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc5030000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;

... as this may not be the correct clock.

The user manual lists the following SGD clocks for the media-related IP
cores:

- CSI[0123]:		SGD1_VIO_CSI[0123]φ, SGD2_VIO_CSI[0123]φ,
			SGD4_VIO_CSI[0123]φ, SGD16_VIO_CSI[0123]φ

- VIN[012]:		SGD1_VIO_CSI0φ, SGD4_VIO_CSI0φ
- VIN[345]:		SGD1_VIO_CSI1φ, SGD4_VIO_CSI1φ
- VIN[678]:		SGD1_VIO_CSI2φ, SGD4_VIO_CSI2φ
- VIN{9,10,11}:		SGD1_VIO_CSI3φ, SGD4_VIO_CSI3φ

- ISP CS[0123]:		SGD1_VIO_CSI[0123]φ, SGD2_VIO_CSI[0123]φ
- ISP Core[0123]:	SGD1_VIO_ISP[0123]φ, SGD2_VIO_ISP[0123]φ

- FCPV[BI][0-9]:	SGD1_VIO_DP_TXφ, SGD4_VIO_DP_TXφ
- FCPVD[ab][0-9]:	SGD1_VIO_DP_TXφ, SGD4_VIO_DP_TXφ
- FCPVX[0123]:		SGD1_VIO_ISP[0123]φ, SGD4_VIO_ISP[0123]φ

- VSP[BI][0-9]:		SGD1_VIO_DP_OTHERφ, SGD4_VIO_DP_OTHERφ
- VSPD[ab][0-9]:	SGD1_VIO_DP_TXφ, SGD4_VIO_DP_TXφ
- VSPX[0123]:		SGD1_VIO_ISP[0123]φ, SGD4_VIO_ISP[0123]φ

- VCON[0123]:		SGD1_VIO_DP_OTHER0φ, SGD4_VIO_DP_OTHER0φ
- VCON[4567]:		SGD1_VIO_DP_OTHER1φ, SGD4_VIO_DP_OTHER2φ
- VCON[89]:		SGD1_VIO_DP_OTHER2φ, SGD4_VIO_DP_OTHER2φ

- DPTX[012]:		SGD2_VIO_DP_TXφ, SGD16_VIO_DP_TXφ

Those IP cores are connected in four types of pipelines:

- FCPV[BI] -> VSP[BI]
- FCPVD -> VSPD -> VCON -> DPTX
- FCPVX -> VSPX -> ISP Core
- CSI -> VIN -> ISP CS

It would be quite logical for all IP cores in the same pipeline to use
the same clock. This would be

- FCPV[BI] -> VSP[BI]:			SGD*_VIO_DP_OTHERφ
- FCPVD -> VSPD -> VCON -> DPTX:	SGD*_VIO_DP_TXφ
- FCPVX -> VSPX -> ISP Core:		SGD*_VIO_ISP[0123]φ
- CSI -> VIN -> ISP CS:			SGD*_VIO_CSI[0123]φ

This mostly matches the clocks listed in the user manual, except for

- FCPV[BI] that is listed as using SGD*_VIO_DP_TXφ
- VCON that is listed as using SGD*_VIO_DP_OTHER[012]φ

Now, note how in the clock diagram document the VIO "ISP" and "CSI"
hierarchies both show 4 groups of SGD clocks (respectively named
SGD*_VIO_ISP0 and SGD*_VIO_CSI0 in the first group), the VIO "DP"
hierarchies show 3 groups of SGD clocks (named SGD*_VIO_DP0 in the first
group) and the VIO "DP_OTHER" hierarchy shows a single group of SGD
clocks (named SGD*_VIO_DP_OTHER).

This makes me believe that, wherever the user manual lists
SGD*_VIO_DP_TXφ, it actually means SGD*_VIO_DP[012]φ. Similarly, where
the user manual lists SGD*_VIO_DP_OTHER[012]φ for VCON, I believe it
should be SGD*_VIO_DP[012]φ, both because there is a single
SGD*_VIO_DP_OTHERφ, and because the rest of the VCON pipelines (FCPVD,
VSPD and DPTX) all use SGD*_VIO_DP[012]φ.

For full consistency, I also suppose that the FCPV[BI][0-9] instances
match the corresponding VSP[BI][0-9] and use the SGD*_VIO_DP_OTHERφ
clocks, not the listed SGD*_VIO_DP_TXφ clocks.

This being said, in practice this probably makes no difference, as all
those clocks derive from the same SGD1_VIO_MAIN clock and none of them
are programmable or gateable.

If the above explanation makes sense to you (and to Geert), we can ask
Renesas to check if the issue I suspect are errors in the documentation.

Finally, while neither the FCP nor the VSP chapters indicate what the
SGD1 and SGD4 clocks are used for, the VCON chapter lists SGD1 as the
"VSPD I/F clock" and SGD4 as the "APB I/F clock", and the ISPCS chapter
lists SGD1 as the "Processing clock of ISP CS" and SGD2 as the "APB I/F
clock". The APB clocks are used for register access, while the "I/F
clock" or "processing clocks" are used for the data flow. If the FCP
driver (or the VSP driver) had a need to know any clock frequency, it
would be the data clock. I would therefore use SGD1 instead of SGD4 here
(same for the VSP).

> +			power-domains = <&mdlc_vio 0x07 0x107>;
> +			resets = <&mdlc_vio 0x107>;
> +		};
> +
> +		fcpvi1: fcp@c5031000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc5031000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x108>;
> +			resets = <&mdlc_vio 0x108>;
> +		};
> +
> +		fcpvi2: fcp@c5032000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc5032000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x109>;
> +			resets = <&mdlc_vio 0x109>;
> +		};
> +
> +		fcpvi3: fcp@c5033000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc5033000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x10a>;
> +			resets = <&mdlc_vio 0x10a>;
> +		};
> +
> +		fcpvb0: fcp@c5038000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc5038000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x102>;
> +			resets = <&mdlc_vio 0x102>;
> +		};
> +
> +		fcpvb1: fcp@c5039000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc5039000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x103>;
> +			resets = <&mdlc_vio 0x103>;
> +		};
> +
> +		fcpvb2: fcp@c503a000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc503a000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x104>;
> +			resets = <&mdlc_vio 0x104>;
> +		};
> +
> +		fcpvb3: fcp@c503b000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc503b000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x105>;
> +			resets = <&mdlc_vio 0x105>;
> +		};
> +
> +		fcpvb4: fcp@c503c000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc503c000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x106>;
> +			resets = <&mdlc_vio 0x106>;
> +		};
> +
>  		mdlc_cmnn: system-controller@ca410000 {
>  			compatible = "renesas,r8a78000-mdlc";
>  			reg = <0 0xca410000 0 0x1000>;

-- 
Regards,

Laurent Pinchart

[PATCH DNI v3 05/15] arm64: renesas: r8a78000: Add VSP[BI] nodes

[Paul Elder]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Add DT nodes for the VSPB and VSPI IP cores in the R-Car X5H SoC.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
 arch/arm64/boot/dts/renesas/r8a78000.dtsi | 99 +++++++++++++++++++++++++++++++
 1 file changed, 99 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
index 2f8886f8b6545026397fd83969882f8c62afa9d3..f90b869579d384e3fc13d0a13625b7cddaac2868 100644
--- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
@@ -1072,6 +1072,105 @@ fcpvb4: fcp@c503c000 {
 			resets = <&mdlc_vio 0x106>;
 		};
 
+		vspi0: vsp@c5080000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc5080000 0 0x8000>;
+			interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
+			power-domains = <&mdlc_vio 0x07 0xfe>;
+			resets = <&mdlc_vio 0xfe>;
+
+			renesas,fcp = <&fcpvi0>;
+		};
+
+		vspi1: vsp@c5088000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc5088000 0 0x8000>;
+			interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
+			power-domains = <&mdlc_vio 0x07 0xff>;
+			resets = <&mdlc_vio 0xff>;
+
+			renesas,fcp = <&fcpvi1>;
+		};
+
+		vspi2: vsp@c5090000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc5090000 0 0x8000>;
+			interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
+			power-domains = <&mdlc_vio 0x07 0x100>;
+			resets = <&mdlc_vio 0x100>;
+
+			renesas,fcp = <&fcpvi2>;
+		};
+
+		vspi3: vsp@c5098000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc5098000 0 0x8000>;
+			interrupts = <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
+			power-domains = <&mdlc_vio 0x07 0x101>;
+			resets = <&mdlc_vio 0x101>;
+
+			renesas,fcp = <&fcpvi3>;
+		};
+
+		vspb0: vsp@c50c0000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc50c0000 0 0x8000>;
+			interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
+			power-domains = <&mdlc_vio 0x07 0xf9>;
+			resets = <&mdlc_vio 0xf9>;
+
+			renesas,fcp = <&fcpvb0>;
+		};
+
+		vspb1: vsp@c50c8000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc50c8000 0 0x8000>;
+			interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
+			power-domains = <&mdlc_vio 0x07 0xfa>;
+			resets = <&mdlc_vio 0xfa>;
+
+			renesas,fcp = <&fcpvb1>;
+		};
+
+		vspb2: vsp@c50d0000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc50d0000 0 0x8000>;
+			interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
+			power-domains = <&mdlc_vio 0x07 0xfb>;
+			resets = <&mdlc_vio 0xfb>;
+
+			renesas,fcp = <&fcpvb2>;
+		};
+
+		vspb3: vsp@c50d8000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc50d8000 0 0x8000>;
+			interrupts = <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
+			power-domains = <&mdlc_vio 0x07 0xfc>;
+			resets = <&mdlc_vio 0xfc>;
+
+			renesas,fcp = <&fcpvb3>;
+		};
+
+		vspb4: vsp@c50e0000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc50e0000 0 0x8000>;
+			interrupts = <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
+			power-domains = <&mdlc_vio 0x07 0xfd>;
+			resets = <&mdlc_vio 0xfd>;
+
+			renesas,fcp = <&fcpvb4>;
+		};
+
 		mdlc_cmnn: system-controller@ca410000 {
 			compatible = "renesas,r8a78000-mdlc";
 			reg = <0 0xca410000 0 0x1000>;

-- 
2.47.3

Re: [PATCH DNI v3 05/15] arm64: renesas: r8a78000: Add VSP[BI] nodes

[Laurent Pinchart]

Hi Paul,

On Thu, Oct 15, 2026 at 04:51:45PM +0900, Paul Elder wrote:
> From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> 
> Add DT nodes for the VSPB and VSPI IP cores in the R-Car X5H SoC.
> 
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Tested-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> ---
>  arch/arm64/boot/dts/renesas/r8a78000.dtsi | 99 +++++++++++++++++++++++++++++++
>  1 file changed, 99 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> index 2f8886f8b6545026397fd83969882f8c62afa9d3..f90b869579d384e3fc13d0a13625b7cddaac2868 100644
> --- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> @@ -1072,6 +1072,105 @@ fcpvb4: fcp@c503c000 {
>  			resets = <&mdlc_vio 0x106>;
>  		};
>  
> +		vspi0: vsp@c5080000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc5080000 0 0x8000>;
> +			interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;

For the reason explained in 04/15, I would use
R8A78000_CPG_SGD1_VIO_DP_OTHER here and below.

> +			power-domains = <&mdlc_vio 0x07 0xfe>;
> +			resets = <&mdlc_vio 0xfe>;
> +
> +			renesas,fcp = <&fcpvi0>;
> +		};
> +
> +		vspi1: vsp@c5088000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc5088000 0 0x8000>;
> +			interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
> +			power-domains = <&mdlc_vio 0x07 0xff>;
> +			resets = <&mdlc_vio 0xff>;
> +
> +			renesas,fcp = <&fcpvi1>;
> +		};
> +
> +		vspi2: vsp@c5090000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc5090000 0 0x8000>;
> +			interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
> +			power-domains = <&mdlc_vio 0x07 0x100>;
> +			resets = <&mdlc_vio 0x100>;
> +
> +			renesas,fcp = <&fcpvi2>;
> +		};
> +
> +		vspi3: vsp@c5098000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc5098000 0 0x8000>;
> +			interrupts = <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
> +			power-domains = <&mdlc_vio 0x07 0x101>;
> +			resets = <&mdlc_vio 0x101>;
> +
> +			renesas,fcp = <&fcpvi3>;
> +		};
> +
> +		vspb0: vsp@c50c0000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc50c0000 0 0x8000>;
> +			interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
> +			power-domains = <&mdlc_vio 0x07 0xf9>;
> +			resets = <&mdlc_vio 0xf9>;
> +
> +			renesas,fcp = <&fcpvb0>;
> +		};
> +
> +		vspb1: vsp@c50c8000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc50c8000 0 0x8000>;
> +			interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
> +			power-domains = <&mdlc_vio 0x07 0xfa>;
> +			resets = <&mdlc_vio 0xfa>;
> +
> +			renesas,fcp = <&fcpvb1>;
> +		};
> +
> +		vspb2: vsp@c50d0000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc50d0000 0 0x8000>;
> +			interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
> +			power-domains = <&mdlc_vio 0x07 0xfb>;
> +			resets = <&mdlc_vio 0xfb>;
> +
> +			renesas,fcp = <&fcpvb2>;
> +		};
> +
> +		vspb3: vsp@c50d8000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc50d8000 0 0x8000>;
> +			interrupts = <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
> +			power-domains = <&mdlc_vio 0x07 0xfc>;
> +			resets = <&mdlc_vio 0xfc>;
> +
> +			renesas,fcp = <&fcpvb3>;
> +		};
> +
> +		vspb4: vsp@c50e0000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc50e0000 0 0x8000>;
> +			interrupts = <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
> +			power-domains = <&mdlc_vio 0x07 0xfd>;
> +			resets = <&mdlc_vio 0xfd>;
> +
> +			renesas,fcp = <&fcpvb4>;
> +		};
> +
>  		mdlc_cmnn: system-controller@ca410000 {
>  			compatible = "renesas,r8a78000-mdlc";
>  			reg = <0 0xca410000 0 0x1000>;

-- 
Regards,

Laurent Pinchart

[PATCH DNI v3 06/15] arm64: renesas: r8a78000: Add FCPVD and VSPD nodes

[Paul Elder]

Add DT nodes for the FCPVD and VSPD IP cores in the R-Car X5H SoC.

Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

---
Changes in v3:
- Fix the mapping between VSPD and FCPVD nodes so that they all work
---
 arch/arm64/boot/dts/renesas/r8a78000.dtsi | 190 ++++++++++++++++++++++++++++++
 1 file changed, 190 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
index f90b869579d384e3fc13d0a13625b7cddaac2868..1fa4896739110de1e445bfcd631d4937bda40714 100644
--- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
@@ -1000,6 +1000,196 @@ mdlc_aon: system-controller@c1338000 {
 			bootph-all;
 		};
 
+		fcpvd0: fcp@c5010000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5010000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x7e>;
+			resets = <&mdlc_vio 0x7e>;
+		};
+
+		fcpvd1: fcp@c5011000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5011000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x7f>;
+			resets = <&mdlc_vio 0x7f>;
+		};
+
+		fcpvd2: fcp@c5012000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5012000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x80>;
+			resets = <&mdlc_vio 0x80>;
+		};
+
+		fcpvd3: fcp@c5013000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5013000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x81>;
+			resets = <&mdlc_vio 0x81>;
+		};
+
+		fcpvd4: fcp@c5014000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5014000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x82>;
+			resets = <&mdlc_vio 0x82>;
+		};
+
+		fcpvd5: fcp@c5015000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5015000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x83>;
+			resets = <&mdlc_vio 0x83>;
+		};
+
+		fcpvd6: fcp@c5016000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5016000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x84>;
+			resets = <&mdlc_vio 0x84>;
+		};
+
+		fcpvd7: fcp@c5017000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5017000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x85>;
+			resets = <&mdlc_vio 0x85>;
+		};
+
+		fcpvd8: fcp@c5018000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5018000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x86>;
+			resets = <&mdlc_vio 0x86>;
+		};
+
+		fcpvd9: fcp@c5019000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5019000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x87>;
+			resets = <&mdlc_vio 0x87>;
+		};
+
+		vspd0: vsp@c4800000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc4800000 0 0x8000>;
+			interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x70>;
+			resets = <&mdlc_vio 0x70>;
+
+			renesas,fcp = <&fcpvd0>;
+		};
+
+		vspd1: vsp@c4808000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc4808000 0 0x8000>;
+			interrupts = <GIC_SPI 624 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x71>;
+			resets = <&mdlc_vio 0x71>;
+
+			renesas,fcp = <&fcpvd1>;
+		};
+
+		vspd2: vsp@c4810000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc4810000 0 0x8000>;
+			interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x72>;
+			resets = <&mdlc_vio 0x72>;
+
+			renesas,fcp = <&fcpvd4>;
+		};
+
+		vspd3: vsp@c4818000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc4818000 0 0x8000>;
+			interrupts = <GIC_SPI 626 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x73>;
+			resets = <&mdlc_vio 0x73>;
+
+			renesas,fcp = <&fcpvd5>;
+		};
+
+		vspd4: vsp@c4820000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc4820000 0 0x8000>;
+			interrupts = <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x74>;
+			resets = <&mdlc_vio 0x74>;
+
+			renesas,fcp = <&fcpvd8>;
+		};
+
+		vspdb0: vsp@c4828000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc4828000 0 0x8000>;
+			interrupts = <GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x75>;
+			resets = <&mdlc_vio 0x75>;
+
+			renesas,fcp = <&fcpvd2>;
+		};
+
+		vspdb1: vsp@c4830000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc4830000 0 0x8000>;
+			interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x76>;
+			resets = <&mdlc_vio 0x76>;
+
+			renesas,fcp = <&fcpvd3>;
+		};
+
+		vspdb2: vsp@c4838000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc4838000 0 0x8000>;
+			interrupts = <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x77>;
+			resets = <&mdlc_vio 0x77>;
+
+			renesas,fcp = <&fcpvd6>;
+		};
+
+		vspdb3: vsp@c4840000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc4840000 0 0x8000>;
+			interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x78>;
+			resets = <&mdlc_vio 0x78>;
+
+			renesas,fcp = <&fcpvd7>;
+		};
+
+		vspdb4: vsp@c4848000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc4848000 0 0x8000>;
+			interrupts = <GIC_SPI 632 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x79>;
+			resets = <&mdlc_vio 0x79>;
+
+			renesas,fcp = <&fcpvd9>;
+		};
+
 		fcpvi0: fcp@c5030000 {
 			compatible = "renesas,fcpv";
 			reg = <0 0xc5030000 0 0x1000>;

-- 
2.47.3

Re: [PATCH DNI v3 06/15] arm64: renesas: r8a78000: Add FCPVD and VSPD nodes

[Laurent Pinchart]

On Thu, Oct 15, 2026 at 04:51:46PM +0900, Paul Elder wrote:
> Add DT nodes for the FCPVD and VSPD IP cores in the R-Car X5H SoC.
> 
> Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> 
> ---
> Changes in v3:
> - Fix the mapping between VSPD and FCPVD nodes so that they all work

That was a good catch. I think the weird mapping comes from how the VSPD
instances are connected to VCON groups:

- VCON group 0 (VCON[0123], DPTX0): VSPDa0, VSPDa1, VSPDb0, VSPDb1
- VCON group 1 (VCON[4567], DPTX1): VSPDa2, VSPDa3, VSPDb2, VSPDb3
- VCON group 2 (VCON[89], DPTX2): VSPDa4, VSPDb4

> ---
>  arch/arm64/boot/dts/renesas/r8a78000.dtsi | 190 ++++++++++++++++++++++++++++++
>  1 file changed, 190 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> index f90b869579d384e3fc13d0a13625b7cddaac2868..1fa4896739110de1e445bfcd631d4937bda40714 100644
> --- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> @@ -1000,6 +1000,196 @@ mdlc_aon: system-controller@c1338000 {
>  			bootph-all;
>  		};
>  
> +		fcpvd0: fcp@c5010000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc5010000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;

Here (and below) too I would use SGD1.

> +			power-domains = <&mdlc_vio 0x07 0x7e>;
> +			resets = <&mdlc_vio 0x7e>;
> +		};
> +
> +		fcpvd1: fcp@c5011000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc5011000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x7f>;
> +			resets = <&mdlc_vio 0x7f>;
> +		};
> +
> +		fcpvd2: fcp@c5012000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc5012000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x80>;
> +			resets = <&mdlc_vio 0x80>;
> +		};
> +
> +		fcpvd3: fcp@c5013000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc5013000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x81>;
> +			resets = <&mdlc_vio 0x81>;
> +		};
> +
> +		fcpvd4: fcp@c5014000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc5014000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x82>;
> +			resets = <&mdlc_vio 0x82>;
> +		};
> +
> +		fcpvd5: fcp@c5015000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc5015000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x83>;
> +			resets = <&mdlc_vio 0x83>;
> +		};
> +
> +		fcpvd6: fcp@c5016000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc5016000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x84>;
> +			resets = <&mdlc_vio 0x84>;
> +		};
> +
> +		fcpvd7: fcp@c5017000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc5017000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x85>;
> +			resets = <&mdlc_vio 0x85>;
> +		};
> +
> +		fcpvd8: fcp@c5018000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc5018000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x86>;
> +			resets = <&mdlc_vio 0x86>;
> +		};
> +
> +		fcpvd9: fcp@c5019000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc5019000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x87>;
> +			resets = <&mdlc_vio 0x87>;
> +		};
> +
> +		vspd0: vsp@c4800000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc4800000 0 0x8000>;
> +			interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x70>;
> +			resets = <&mdlc_vio 0x70>;
> +
> +			renesas,fcp = <&fcpvd0>;
> +		};
> +
> +		vspd1: vsp@c4808000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc4808000 0 0x8000>;
> +			interrupts = <GIC_SPI 624 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x71>;
> +			resets = <&mdlc_vio 0x71>;
> +
> +			renesas,fcp = <&fcpvd1>;
> +		};
> +
> +		vspd2: vsp@c4810000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc4810000 0 0x8000>;
> +			interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x72>;
> +			resets = <&mdlc_vio 0x72>;
> +
> +			renesas,fcp = <&fcpvd4>;
> +		};
> +
> +		vspd3: vsp@c4818000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc4818000 0 0x8000>;
> +			interrupts = <GIC_SPI 626 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x73>;
> +			resets = <&mdlc_vio 0x73>;
> +
> +			renesas,fcp = <&fcpvd5>;
> +		};
> +
> +		vspd4: vsp@c4820000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc4820000 0 0x8000>;
> +			interrupts = <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x74>;
> +			resets = <&mdlc_vio 0x74>;
> +
> +			renesas,fcp = <&fcpvd8>;
> +		};
> +
> +		vspdb0: vsp@c4828000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc4828000 0 0x8000>;
> +			interrupts = <GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x75>;
> +			resets = <&mdlc_vio 0x75>;
> +
> +			renesas,fcp = <&fcpvd2>;
> +		};
> +
> +		vspdb1: vsp@c4830000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc4830000 0 0x8000>;
> +			interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x76>;
> +			resets = <&mdlc_vio 0x76>;
> +
> +			renesas,fcp = <&fcpvd3>;
> +		};
> +
> +		vspdb2: vsp@c4838000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc4838000 0 0x8000>;
> +			interrupts = <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x77>;
> +			resets = <&mdlc_vio 0x77>;
> +
> +			renesas,fcp = <&fcpvd6>;
> +		};
> +
> +		vspdb3: vsp@c4840000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc4840000 0 0x8000>;
> +			interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x78>;
> +			resets = <&mdlc_vio 0x78>;
> +
> +			renesas,fcp = <&fcpvd7>;
> +		};
> +
> +		vspdb4: vsp@c4848000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc4848000 0 0x8000>;
> +			interrupts = <GIC_SPI 632 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x79>;
> +			resets = <&mdlc_vio 0x79>;
> +
> +			renesas,fcp = <&fcpvd9>;
> +		};
> +
>  		fcpvi0: fcp@c5030000 {
>  			compatible = "renesas,fcpv";
>  			reg = <0 0xc5030000 0 0x1000>;
> 

-- 
Regards,

Laurent Pinchart

[PATCH v3 07/15] media: vsp1: Support full VSPB on R-Car M3-W, M3-N and E3

[Paul Elder]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

The M3-W, M3-N and E3 SoCs integrate a VSPB that reports the same
version ID as the VSPBD in the H3 and H3-N, but includes additional
entities compared to the VSPBD. The VSPBD device entry in the driver
matches on the version ID only, which results in the VSPB being handled
as a VSPBD. The driver therefore doesn't support the CLU, LUT and HGO
entities in the M3-W, M3-N and E3 SoCs.

To fix it, split the device entry in two, one for the VSPBD with an
additional SoC ID match, and one for the VSPB. The VSPBD entry needs to
be listed first, otherwise the VSPB entry will match on H3 and H3-N as
well.

The VI6_IP_VERSION_MODEL_VSPBD_GEN3 macro is renamed to
VI6_IP_VERSION_MODEL_VSPB_GEN3 to indicate that the VSPBD is the special
case.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
---
 drivers/media/platform/renesas/vsp1/vsp1_drv.c  | 13 ++++++++++++-
 drivers/media/platform/renesas/vsp1/vsp1_regs.h |  2 +-
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/media/platform/renesas/vsp1/vsp1_drv.c b/drivers/media/platform/renesas/vsp1/vsp1_drv.c
index 762a9e776a94d50accad070068f92f6dabb81035..5597595414fe787413c7daa5a3142faa9ced8408 100644
--- a/drivers/media/platform/renesas/vsp1/vsp1_drv.c
+++ b/drivers/media/platform/renesas/vsp1/vsp1_drv.c
@@ -781,14 +781,25 @@ static const struct vsp1_device_info vsp1_device_infos[] = {
 		.wpf_count = 1,
 		.uapi = true,
 	}, {
-		.version = VI6_IP_VERSION_MODEL_VSPBD_GEN3,
+		.version = VI6_IP_VERSION_MODEL_VSPB_GEN3,
 		.model = "VSP2-BD",
+		.soc = VI6_IP_VERSION_SOC_H3,
 		.gen = 3,
 		.features = VSP1_HAS_BRU | VSP1_HAS_WPF_VFLIP,
 		.rpf_count = 5,
 		.wpf_count = 1,
 		.num_bru_inputs = 5,
 		.uapi = true,
+	}, {
+		.version = VI6_IP_VERSION_MODEL_VSPB_GEN3,
+		.model = "VSP2-B",
+		.gen = 3,
+		.features = VSP1_HAS_BRU | VSP1_HAS_CLU | VSP1_HAS_HGO
+			  | VSP1_HAS_LUT | VSP1_HAS_WPF_VFLIP,
+		.rpf_count = 5,
+		.wpf_count = 1,
+		.num_bru_inputs = 5,
+		.uapi = true,
 	}, {
 		.version = VI6_IP_VERSION_MODEL_VSPBC_GEN3,
 		.model = "VSP2-BC",
diff --git a/drivers/media/platform/renesas/vsp1/vsp1_regs.h b/drivers/media/platform/renesas/vsp1/vsp1_regs.h
index 10cfbcd1b6e0b3a9c0a8daaa990babfaeb8dde0c..4c0315656e9f81a9656b58fb6f0233f8a22ac0e1 100644
--- a/drivers/media/platform/renesas/vsp1/vsp1_regs.h
+++ b/drivers/media/platform/renesas/vsp1/vsp1_regs.h
@@ -792,7 +792,7 @@
 #define VI6_IP_VERSION_MODEL_VSPS_V2H	(0x12 << 8)
 #define VI6_IP_VERSION_MODEL_VSPD_V2H	(0x13 << 8)
 #define VI6_IP_VERSION_MODEL_VSPI_GEN3	(0x14 << 8)
-#define VI6_IP_VERSION_MODEL_VSPBD_GEN3	(0x15 << 8)
+#define VI6_IP_VERSION_MODEL_VSPB_GEN3	(0x15 << 8)
 #define VI6_IP_VERSION_MODEL_VSPBC_GEN3	(0x16 << 8)
 #define VI6_IP_VERSION_MODEL_VSPD_GEN3	(0x17 << 8)
 #define VI6_IP_VERSION_MODEL_VSPD_V3	(0x18 << 8)

-- 
2.47.3

[PATCH v3 08/15] media: vsp1: Add device info entries for VSPD on X5H

[Paul Elder]

Add device info entries for the VSPD so that the driver can match on the
VSPD on the X5H and handle its slightly different hardware configuration.

On the X5H there are two variants, the VSPD (a) and VSPD (b). As the (b)
version has a separate version number, add that as well.

The R-Car X5H uses 0x09 as the SoC ID in the version register. Document
is with a macro, as done for other R-Car SoCs.

Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

---
Changes in v3:
- fix IP version macro
- add comment about UIF
- squashed with adding the SoC ID
---
 drivers/media/platform/renesas/vsp1/vsp1_drv.c  | 27 +++++++++++++++++++++++++
 drivers/media/platform/renesas/vsp1/vsp1_regs.h |  2 ++
 2 files changed, 29 insertions(+)

diff --git a/drivers/media/platform/renesas/vsp1/vsp1_drv.c b/drivers/media/platform/renesas/vsp1/vsp1_drv.c
index 5597595414fe787413c7daa5a3142faa9ced8408..6ec8c234ea29939e4aebdf56fc51ae1cc5c69156 100644
--- a/drivers/media/platform/renesas/vsp1/vsp1_drv.c
+++ b/drivers/media/platform/renesas/vsp1/vsp1_drv.c
@@ -860,6 +860,23 @@ static const struct vsp1_device_info vsp1_device_infos[] = {
 		.uif_count = 2,
 		.wpf_count = 2,
 		.num_bru_inputs = 5,
+	}, {
+		.version = VI6_IP_VERSION_MODEL_VSPD_GEN4,
+		.model = "VSP2-D (a)",
+		.soc = VI6_IP_VERSION_SOC_X5H,
+		.gen = 4,
+		.features = VSP1_HAS_BRU | VSP1_HAS_EXT_DL,
+		.lif_count = 1,
+		.rpf_count = 5,
+		/*
+		 * TODO This VSP has 8 UIFs but it is not supported by the
+		 * driver yet, and the driver hardcodes usage of one UIF per
+		 * LIF starting at UIF4. Declare just 2 UIFs here for now until
+		 * the driver supports more.
+		 */
+		.uif_count = 2,
+		.wpf_count = 1,
+		.num_bru_inputs = 5,
 	}, {
 		.version = VI6_IP_VERSION_MODEL_VSPD_GEN4,
 		.model = "VSP2-D",
@@ -870,6 +887,16 @@ static const struct vsp1_device_info vsp1_device_infos[] = {
 		.uif_count = 2,
 		.wpf_count = 1,
 		.num_bru_inputs = 5,
+	}, {
+		.version = VI6_IP_VERSION_MODEL_VSPDB_GEN5,
+		.model = "VSP2-D (b)",
+		.gen = 4,
+		.features = VSP1_HAS_BRU | VSP1_HAS_EXT_DL,
+		.lif_count = 1,
+		.rpf_count = 5,
+		.uif_count = 1,
+		.wpf_count = 1,
+		.num_bru_inputs = 5,
 	}, {
 		.version = VI6_IP_VERSION_MODEL_VSPX_GEN4,
 		.model = "VSP2-X",
diff --git a/drivers/media/platform/renesas/vsp1/vsp1_regs.h b/drivers/media/platform/renesas/vsp1/vsp1_regs.h
index 4c0315656e9f81a9656b58fb6f0233f8a22ac0e1..cc4755354b7797a7a4e7592c262be2741477b81a 100644
--- a/drivers/media/platform/renesas/vsp1/vsp1_regs.h
+++ b/drivers/media/platform/renesas/vsp1/vsp1_regs.h
@@ -800,6 +800,7 @@
 #define VI6_IP_VERSION_MODEL_VSPBS_GEN3	(0x1a << 8)
 #define VI6_IP_VERSION_MODEL_VSPD_GEN4	(0x1c << 8)
 #define VI6_IP_VERSION_MODEL_VSPX_GEN4	(0x1d << 8)
+#define VI6_IP_VERSION_MODEL_VSPDB_GEN5	(0x20 << 8)
 /* RZ/G2L SoCs have no version register, So use 0x80 as the model version */
 #define VI6_IP_VERSION_MODEL_VSPD_RZG2L	(0x80 << 8)
 
@@ -816,6 +817,7 @@
 #define VI6_IP_VERSION_SOC_E3		(0x04 << 0)
 #define VI6_IP_VERSION_SOC_V3U		(0x05 << 0)
 #define VI6_IP_VERSION_SOC_V4H		(0x06 << 0)
+#define VI6_IP_VERSION_SOC_X5H		(0x09 << 0)
 /* RZ/G2L SoCs have no version register, So use 0x80 for SoC Identification */
 #define VI6_IP_VERSION_SOC_RZG2L	(0x80 << 0)
 

-- 
2.47.3

[PATCH v3 09/15] media: rcar-fcp: Handle resets

[Paul Elder]

On some versions of the FCP, such as the one on the X5H, reset control
is required to operate the FCP. Add support for handling resets
optionally, to continue supporting versions that do not require it.

Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

---
Changes in v2:
- handle errors
---
 drivers/media/platform/renesas/rcar-fcp.c | 30 ++++++++++++++++++++++++++++--
 1 file changed, 28 insertions(+), 2 deletions(-)

diff --git a/drivers/media/platform/renesas/rcar-fcp.c b/drivers/media/platform/renesas/rcar-fcp.c
index dfb0ca93e854dd0bb8aedfb757fd786ef6e45542..76d4c250b30815d9eac58f9b54ad923748df79f6 100644
--- a/drivers/media/platform/renesas/rcar-fcp.c
+++ b/drivers/media/platform/renesas/rcar-fcp.c
@@ -16,6 +16,7 @@
 #include <linux/mutex.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
+#include <linux/reset.h>
 #include <linux/slab.h>
 
 #include <media/rcar-fcp.h>
@@ -29,6 +30,7 @@ struct rcar_fcp_device {
 	struct list_head list;
 	struct device *dev;
 	void __iomem *base;
+	struct reset_control *rstc;
 };
 
 static LIST_HEAD(fcp_devices);
@@ -162,20 +164,25 @@ static int rcar_fcp_probe(struct platform_device *pdev)
 
 	fcp->dev = &pdev->dev;
 
+	platform_set_drvdata(pdev, fcp);
+
 	fcp->base = devm_platform_ioremap_resource(pdev, 0);
 	if (IS_ERR(fcp->base))
 		return PTR_ERR(fcp->base);
 
 	dma_set_max_seg_size(fcp->dev, UINT_MAX);
 
+	fcp->rstc = devm_reset_control_get_optional(&pdev->dev, NULL);
+	if (IS_ERR(fcp->rstc))
+		return dev_err_probe(&pdev->dev, PTR_ERR(fcp->rstc),
+				     "failed to get reset control\n");
+
 	pm_runtime_enable(&pdev->dev);
 
 	mutex_lock(&fcp_lock);
 	list_add_tail(&fcp->list, &fcp_devices);
 	mutex_unlock(&fcp_lock);
 
-	platform_set_drvdata(pdev, fcp);
-
 	return 0;
 }
 
@@ -190,6 +197,24 @@ static void rcar_fcp_remove(struct platform_device *pdev)
 	pm_runtime_disable(&pdev->dev);
 }
 
+static int fcp_pm_runtime_suspend(struct device *dev)
+{
+	struct rcar_fcp_device *fcp = dev_get_drvdata(dev);
+
+	return reset_control_assert(fcp->rstc);
+}
+
+static int fcp_pm_runtime_resume(struct device *dev)
+{
+	struct rcar_fcp_device *fcp = dev_get_drvdata(dev);
+
+	return reset_control_deassert(fcp->rstc);
+}
+
+static const struct dev_pm_ops fcp_pm_ops = {
+	RUNTIME_PM_OPS(fcp_pm_runtime_suspend, fcp_pm_runtime_resume, NULL)
+};
+
 static const struct of_device_id rcar_fcp_of_match[] = {
 	{ .compatible = "renesas,fcpf" },
 	{ .compatible = "renesas,fcpv" },
@@ -202,6 +227,7 @@ static struct platform_driver rcar_fcp_platform_driver = {
 	.remove		= rcar_fcp_remove,
 	.driver		= {
 		.name	= "rcar-fcp",
+		.pm = pm_ptr(&fcp_pm_ops),
 		.of_match_table = rcar_fcp_of_match,
 		.suppress_bind_attrs = true,
 	},

-- 
2.47.3

[PATCH v3 10/15] media: vsp1: Fix access to reserved registers

[Paul Elder]

From: Phong Hoang <phong.hoang.wz@renesas.com>

Some modules of VSP are not available in all instances,
so fix access to reserved registers.

Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
Reviewed-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
---
 drivers/media/platform/renesas/vsp1/vsp1_drv.c | 34 ++++++++++++++++++--------
 1 file changed, 24 insertions(+), 10 deletions(-)

diff --git a/drivers/media/platform/renesas/vsp1/vsp1_drv.c b/drivers/media/platform/renesas/vsp1/vsp1_drv.c
index 6ec8c234ea29939e4aebdf56fc51ae1cc5c69156..819c5eda9171d8ef7c8fc88adc959019b6bed497 100644
--- a/drivers/media/platform/renesas/vsp1/vsp1_drv.c
+++ b/drivers/media/platform/renesas/vsp1/vsp1_drv.c
@@ -560,20 +560,34 @@ static int vsp1_device_init(struct vsp1_device *vsp1)
 	for (unsigned int i = 0; i < vsp1->info->uif_count; ++i)
 		vsp1_write(vsp1, VI6_DPR_UIF_ROUTE(i), VI6_DPR_NODE_UNUSED);
 
-	vsp1_write(vsp1, VI6_DPR_SRU_ROUTE, VI6_DPR_NODE_UNUSED);
-	vsp1_write(vsp1, VI6_DPR_LUT_ROUTE, VI6_DPR_NODE_UNUSED);
-	vsp1_write(vsp1, VI6_DPR_CLU_ROUTE, VI6_DPR_NODE_UNUSED);
-	vsp1_write(vsp1, VI6_DPR_HST_ROUTE, VI6_DPR_NODE_UNUSED);
-	vsp1_write(vsp1, VI6_DPR_HSI_ROUTE, VI6_DPR_NODE_UNUSED);
-	vsp1_write(vsp1, VI6_DPR_BRU_ROUTE, VI6_DPR_NODE_UNUSED);
+	if (vsp1_feature(vsp1, VSP1_HAS_SRU))
+		vsp1_write(vsp1, VI6_DPR_SRU_ROUTE, VI6_DPR_NODE_UNUSED);
+
+	if (vsp1_feature(vsp1, VSP1_HAS_LUT))
+		vsp1_write(vsp1, VI6_DPR_LUT_ROUTE, VI6_DPR_NODE_UNUSED);
+
+	if (vsp1_feature(vsp1, VSP1_HAS_CLU))
+		vsp1_write(vsp1, VI6_DPR_CLU_ROUTE, VI6_DPR_NODE_UNUSED);
+
+	if (vsp1_feature(vsp1, VSP1_HAS_HSIT))
+		vsp1_write(vsp1, VI6_DPR_HST_ROUTE, VI6_DPR_NODE_UNUSED);
+
+	if (vsp1_feature(vsp1, VSP1_HAS_HSIT))
+		vsp1_write(vsp1, VI6_DPR_HSI_ROUTE, VI6_DPR_NODE_UNUSED);
+
+	if (vsp1_feature(vsp1, VSP1_HAS_BRU))
+		vsp1_write(vsp1, VI6_DPR_BRU_ROUTE, VI6_DPR_NODE_UNUSED);
 
 	if (vsp1_feature(vsp1, VSP1_HAS_BRS))
 		vsp1_write(vsp1, VI6_DPR_ILV_BRS_ROUTE, VI6_DPR_NODE_UNUSED);
 
-	vsp1_write(vsp1, VI6_DPR_HGO_SMPPT, (7 << VI6_DPR_SMPPT_TGW_SHIFT) |
-		   (VI6_DPR_NODE_UNUSED << VI6_DPR_SMPPT_PT_SHIFT));
-	vsp1_write(vsp1, VI6_DPR_HGT_SMPPT, (7 << VI6_DPR_SMPPT_TGW_SHIFT) |
-		   (VI6_DPR_NODE_UNUSED << VI6_DPR_SMPPT_PT_SHIFT));
+	if (vsp1_feature(vsp1, VSP1_HAS_HGO))
+		vsp1_write(vsp1, VI6_DPR_HGO_SMPPT, (7 << VI6_DPR_SMPPT_TGW_SHIFT) |
+			   (VI6_DPR_NODE_UNUSED << VI6_DPR_SMPPT_PT_SHIFT));
+
+	if (vsp1_feature(vsp1, VSP1_HAS_HGT))
+		vsp1_write(vsp1, VI6_DPR_HGT_SMPPT, (7 << VI6_DPR_SMPPT_TGW_SHIFT) |
+			   (VI6_DPR_NODE_UNUSED << VI6_DPR_SMPPT_PT_SHIFT));
 
 	vsp1_dlm_setup(vsp1);
 

-- 
2.47.3

Re: [PATCH v3 10/15] media: vsp1: Fix access to reserved registers

[Laurent Pinchart]

On Thu, Oct 15, 2026 at 04:51:50PM +0900, Paul Elder wrote:
> From: Phong Hoang <phong.hoang.wz@renesas.com>
> 
> Some modules of VSP are not available in all instances,
> so fix access to reserved registers.
> 
> Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
> Reviewed-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
> Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
> ---
>  drivers/media/platform/renesas/vsp1/vsp1_drv.c | 34 ++++++++++++++++++--------
>  1 file changed, 24 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/media/platform/renesas/vsp1/vsp1_drv.c b/drivers/media/platform/renesas/vsp1/vsp1_drv.c
> index 6ec8c234ea29939e4aebdf56fc51ae1cc5c69156..819c5eda9171d8ef7c8fc88adc959019b6bed497 100644
> --- a/drivers/media/platform/renesas/vsp1/vsp1_drv.c
> +++ b/drivers/media/platform/renesas/vsp1/vsp1_drv.c
> @@ -560,20 +560,34 @@ static int vsp1_device_init(struct vsp1_device *vsp1)
>  	for (unsigned int i = 0; i < vsp1->info->uif_count; ++i)
>  		vsp1_write(vsp1, VI6_DPR_UIF_ROUTE(i), VI6_DPR_NODE_UNUSED);
>  
> -	vsp1_write(vsp1, VI6_DPR_SRU_ROUTE, VI6_DPR_NODE_UNUSED);
> -	vsp1_write(vsp1, VI6_DPR_LUT_ROUTE, VI6_DPR_NODE_UNUSED);
> -	vsp1_write(vsp1, VI6_DPR_CLU_ROUTE, VI6_DPR_NODE_UNUSED);
> -	vsp1_write(vsp1, VI6_DPR_HST_ROUTE, VI6_DPR_NODE_UNUSED);
> -	vsp1_write(vsp1, VI6_DPR_HSI_ROUTE, VI6_DPR_NODE_UNUSED);
> -	vsp1_write(vsp1, VI6_DPR_BRU_ROUTE, VI6_DPR_NODE_UNUSED);
> +	if (vsp1_feature(vsp1, VSP1_HAS_SRU))
> +		vsp1_write(vsp1, VI6_DPR_SRU_ROUTE, VI6_DPR_NODE_UNUSED);
> +
> +	if (vsp1_feature(vsp1, VSP1_HAS_LUT))
> +		vsp1_write(vsp1, VI6_DPR_LUT_ROUTE, VI6_DPR_NODE_UNUSED);
> +
> +	if (vsp1_feature(vsp1, VSP1_HAS_CLU))
> +		vsp1_write(vsp1, VI6_DPR_CLU_ROUTE, VI6_DPR_NODE_UNUSED);
> +
> +	if (vsp1_feature(vsp1, VSP1_HAS_HSIT))
> +		vsp1_write(vsp1, VI6_DPR_HST_ROUTE, VI6_DPR_NODE_UNUSED);
> +
> +	if (vsp1_feature(vsp1, VSP1_HAS_HSIT))
> +		vsp1_write(vsp1, VI6_DPR_HSI_ROUTE, VI6_DPR_NODE_UNUSED);
> +
> +	if (vsp1_feature(vsp1, VSP1_HAS_BRU))
> +		vsp1_write(vsp1, VI6_DPR_BRU_ROUTE, VI6_DPR_NODE_UNUSED);
>  
>  	if (vsp1_feature(vsp1, VSP1_HAS_BRS))
>  		vsp1_write(vsp1, VI6_DPR_ILV_BRS_ROUTE, VI6_DPR_NODE_UNUSED);
>  
> -	vsp1_write(vsp1, VI6_DPR_HGO_SMPPT, (7 << VI6_DPR_SMPPT_TGW_SHIFT) |
> -		   (VI6_DPR_NODE_UNUSED << VI6_DPR_SMPPT_PT_SHIFT));
> -	vsp1_write(vsp1, VI6_DPR_HGT_SMPPT, (7 << VI6_DPR_SMPPT_TGW_SHIFT) |
> -		   (VI6_DPR_NODE_UNUSED << VI6_DPR_SMPPT_PT_SHIFT));
> +	if (vsp1_feature(vsp1, VSP1_HAS_HGO))
> +		vsp1_write(vsp1, VI6_DPR_HGO_SMPPT, (7 << VI6_DPR_SMPPT_TGW_SHIFT) |
> +			   (VI6_DPR_NODE_UNUSED << VI6_DPR_SMPPT_PT_SHIFT));
> +
> +	if (vsp1_feature(vsp1, VSP1_HAS_HGT))
> +		vsp1_write(vsp1, VI6_DPR_HGT_SMPPT, (7 << VI6_DPR_SMPPT_TGW_SHIFT) |
> +			   (VI6_DPR_NODE_UNUSED << VI6_DPR_SMPPT_PT_SHIFT));

I'm fairly sure the hardware would work fine without those checks, but I
understand there's a desire to pass certifications. As this isn't in a
hot patch,

Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

>  
>  	vsp1_dlm_setup(vsp1);
>  

-- 
Regards,

Laurent Pinchart

[PATCH v3 11/15] media: vsp1: Fix du_complete race condition issue

[Paul Elder]

From: Phong Hoang <phong.hoang.wz@renesas.com>

vsp1_du_pipeline_frame_end() runs in hardirq context and tests
drm_pipe->du_complete before calling it. vsp1_du_setup_lif() clears
the same pointer on the CRTC-disable path while holding only drm->lock,
a mutex that does not serialize against the IRQ. On SMP, du_complete
can be cleared between the NULL check and the call, leading to NULL
pointer dereference.

Therefore, fixing this issue by using READ_ONCE()/WRITE_ONCE() for
du_complete and ensuring du_private is initialized first.

Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
Reviewed-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
---
 drivers/media/platform/renesas/vsp1/vsp1_drm.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/media/platform/renesas/vsp1/vsp1_drm.c b/drivers/media/platform/renesas/vsp1/vsp1_drm.c
index 9cd5c025d2be8461bd76e14b15f990eb8bfa2909..3dcb83df46f485ecc94334e7a48871e2368a3527 100644
--- a/drivers/media/platform/renesas/vsp1/vsp1_drm.c
+++ b/drivers/media/platform/renesas/vsp1/vsp1_drm.c
@@ -35,8 +35,10 @@ static void vsp1_du_pipeline_frame_end(struct vsp1_pipeline *pipe,
 				       unsigned int completion)
 {
 	struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
+	void (*du_complete)(void *data, unsigned int status, u32 crc);
 
-	if (drm_pipe->du_complete) {
+	du_complete = READ_ONCE(drm_pipe->du_complete);
+	if (du_complete) {
 		struct vsp1_entity *uif = drm_pipe->uif;
 		unsigned int status = completion
 				    & (VSP1_DU_STATUS_COMPLETE |
@@ -44,7 +46,7 @@ static void vsp1_du_pipeline_frame_end(struct vsp1_pipeline *pipe,
 		u32 crc;
 
 		crc = uif ? vsp1_uif_get_crc(to_uif(&uif->subdev)) : 0;
-		drm_pipe->du_complete(drm_pipe->du_private, status, crc);
+		du_complete(drm_pipe->du_private, status, crc);
 	}
 
 	if (completion & VSP1_DL_FRAME_END_INTERNAL) {
@@ -694,8 +696,8 @@ int vsp1_du_enable(struct device *dev, unsigned int pipe_index,
 		 * Register a callback to allow us to notify the DRM driver of frame
 		 * completion events.
 		 */
-		drm_pipe->du_complete = cfg->callback;
 		drm_pipe->du_private = cfg->callback_data;
+		WRITE_ONCE(drm_pipe->du_complete, cfg->callback);
 
 		/* Disable the display interrupts. */
 		vsp1_write(vsp1, VI6_DISP_IRQ_STA(pipe_index), 0);
@@ -764,7 +766,7 @@ int vsp1_du_disable(struct device *dev, unsigned int pipe_index)
 			brx->inputs[rpf->brx_input].rpf = NULL;
 		}
 
-		drm_pipe->du_complete = NULL;
+		WRITE_ONCE(drm_pipe->du_complete, NULL);
 		pipe->num_inputs = 0;
 
 		dev_dbg(vsp1->dev, "%s: pipe %u: releasing %s\n",

-- 
2.47.3

[PATCH v3 12/15] media: vsp1: Fix setting control register by display list

[Paul Elder]

From: Phong Hoang <phong.hoang.wz@renesas.com>

According to R-Car Hardware User's Manual, VSP HW does not
support to download register settings for the control registers
by display list, so set those registers by APB interface instead.

This limitation is especially enforced within the VDK.

Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
Reviewed-by: Paul Elder <paul.elder@ideasonboard.com>
Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
---
 drivers/media/platform/renesas/vsp1/vsp1_wpf.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/media/platform/renesas/vsp1/vsp1_wpf.c b/drivers/media/platform/renesas/vsp1/vsp1_wpf.c
index 821887815eb2e38d3a51791161de8cd3c135ef3c..4a5ad8e4903e99d5a522af2239889d7899f629cd 100644
--- a/drivers/media/platform/renesas/vsp1/vsp1_wpf.c
+++ b/drivers/media/platform/renesas/vsp1/vsp1_wpf.c
@@ -332,9 +332,8 @@ static void wpf_configure_stream(struct vsp1_entity *entity,
 	vsp1_wpf_write(wpf, dlb, VI6_WPF_SRCRPF, srcrpf);
 
 	/* Enable interrupts. */
-	vsp1_dl_body_write(dlb, VI6_WPF_IRQ_STA(index), 0);
-	vsp1_dl_body_write(dlb, VI6_WPF_IRQ_ENB(index),
-			   VI6_WPF_IRQ_ENB_DFEE);
+	vsp1_write(vsp1, VI6_WPF_IRQ_STA(index), 0);
+	vsp1_write(vsp1, VI6_WPF_IRQ_ENB(index), VI6_WPF_IRQ_ENB_DFEE);
 
 	if (pipe->iif)
 		return;

-- 
2.47.3

Re: [PATCH v3 12/15] media: vsp1: Fix setting control register by display list

[Laurent Pinchart]

On Thu, Oct 15, 2026 at 04:51:52PM +0900, Paul Elder wrote:
> From: Phong Hoang <phong.hoang.wz@renesas.com>
> 
> According to R-Car Hardware User's Manual, VSP HW does not
> support to download register settings for the control registers
> by display list, so set those registers by APB interface instead.
> 
> This limitation is especially enforced within the VDK.
> 
> Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
> Reviewed-by: Paul Elder <paul.elder@ideasonboard.com>
> Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
> ---
>  drivers/media/platform/renesas/vsp1/vsp1_wpf.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/media/platform/renesas/vsp1/vsp1_wpf.c b/drivers/media/platform/renesas/vsp1/vsp1_wpf.c
> index 821887815eb2e38d3a51791161de8cd3c135ef3c..4a5ad8e4903e99d5a522af2239889d7899f629cd 100644
> --- a/drivers/media/platform/renesas/vsp1/vsp1_wpf.c
> +++ b/drivers/media/platform/renesas/vsp1/vsp1_wpf.c
> @@ -332,9 +332,8 @@ static void wpf_configure_stream(struct vsp1_entity *entity,
>  	vsp1_wpf_write(wpf, dlb, VI6_WPF_SRCRPF, srcrpf);
>  
>  	/* Enable interrupts. */
> -	vsp1_dl_body_write(dlb, VI6_WPF_IRQ_STA(index), 0);
> -	vsp1_dl_body_write(dlb, VI6_WPF_IRQ_ENB(index),
> -			   VI6_WPF_IRQ_ENB_DFEE);
> +	vsp1_write(vsp1, VI6_WPF_IRQ_STA(index), 0);
> +	vsp1_write(vsp1, VI6_WPF_IRQ_ENB(index), VI6_WPF_IRQ_ENB_DFEE);

Unfortunately I think this will cause a problem. For the V4L2 and DRM
clients, all should be fine. The configure_stream operation is called
after starting streaming, which calls vsp1_device_get() to
runtime-resume the device. For the ISP client, however, I think this
function can be called from the .buf_queue() handler before the start
streaming operation, as vb2 enqueues buffer in the driver before calling
.start_streaming() on the queue. We would then try to write the register
while the device is suspended, which won't lead to any good outcome.

>  
>  	if (pipe->iif)
>  		return;

-- 
Regards,

Laurent Pinchart

[PATCH v3 13/15] dt-bindings: Increase Renesas X5H MDLC PD specifier bit width

[Paul Elder]

In the Renesas R-Car X5H, the module controller's power domain specifier
cell's bit width has been increased. Update the bindings documentation
to reflect this.

Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>

---
I'm guessing that the maximum number is now 512 but I can't find
definite proof of this.
---
 Documentation/devicetree/bindings/power/renesas,r8a78000-mdlc.yaml | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/power/renesas,r8a78000-mdlc.yaml b/Documentation/devicetree/bindings/power/renesas,r8a78000-mdlc.yaml
index 27d85dd49f9546230ba9632aaa324986261d2156..644b07a07955b98b1832074eefcfd63eb6d45adb 100644
--- a/Documentation/devicetree/bindings/power/renesas,r8a78000-mdlc.yaml
+++ b/Documentation/devicetree/bindings/power/renesas,r8a78000-mdlc.yaml
@@ -12,7 +12,8 @@ maintainers:
 description:
   Each instance of the R-Car X5H Module Controller (MODULE CONTROL) provides
   Power Gating for up to 64 Power Domains, and Module Standby and Reset for up
-  to 256 modules in the Power Domain of each Module hierarchy.
+  to 256 modules in the Power Domain of each Module hierarchy. Recent hardware
+  versions have increased the number of supported modules.
 
 properties:
   compatible:
@@ -32,14 +33,14 @@ properties:
         are always on, and for which there are no MPDG bits to control them.
 
       - The second power domain specifier cell is the module standby part, and
-        must be the module number (0x00-0xff), composed of the Module System
+        must be the module number (0x00-0x1ff), composed of the Module System
         Reset (MSRES) register index in the high nibble, and the Module Reset
         Destination bitfield index in the low nibble.
     const: 2
 
   '#reset-cells':
     description:
-      The single reset specifier cell must be the module number (0x00-0xff),
+      The single reset specifier cell must be the module number (0x00-0x1ff),
       and thus identical to the second power domain specifier cell.
     const: 1
 

-- 
2.47.3

Re: [PATCH v3 13/15] dt-bindings: Increase Renesas X5H MDLC PD specifier bit width

[Krzysztof Kozlowski]

On Thu, Oct 15, 2026 at 04:51:53PM +0900, Paul Elder wrote:
> In the Renesas R-Car X5H, the module controller's power domain specifier
> cell's bit width has been increased. Update the bindings documentation
> to reflect this.
> 
> Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
> 
> ---
> I'm guessing that the maximum number is now 512 but I can't find
> definite proof of this.
> ---
>  Documentation/devicetree/bindings/power/renesas,r8a78000-mdlc.yaml | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

Re: [PATCH v3 13/15] dt-bindings: Increase Renesas X5H MDLC PD specifier bit width

[Laurent Pinchart]

On Thu, Oct 15, 2026 at 04:51:53PM +0900, Paul Elder wrote:
> In the Renesas R-Car X5H, the module controller's power domain specifier
> cell's bit width has been increased. Update the bindings documentation
> to reflect this.
> 
> Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
> ---
> I'm guessing that the maximum number is now 512 but I can't find
> definite proof of this.
> ---
>  Documentation/devicetree/bindings/power/renesas,r8a78000-mdlc.yaml | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/power/renesas,r8a78000-mdlc.yaml b/Documentation/devicetree/bindings/power/renesas,r8a78000-mdlc.yaml
> index 27d85dd49f9546230ba9632aaa324986261d2156..644b07a07955b98b1832074eefcfd63eb6d45adb 100644
> --- a/Documentation/devicetree/bindings/power/renesas,r8a78000-mdlc.yaml
> +++ b/Documentation/devicetree/bindings/power/renesas,r8a78000-mdlc.yaml
> @@ -12,7 +12,8 @@ maintainers:
>  description:
>    Each instance of the R-Car X5H Module Controller (MODULE CONTROL) provides
>    Power Gating for up to 64 Power Domains, and Module Standby and Reset for up
> -  to 256 modules in the Power Domain of each Module hierarchy.
> +  to 256 modules in the Power Domain of each Module hierarchy. Recent hardware
> +  versions have increased the number of supported modules.
>  
>  properties:
>    compatible:
> @@ -32,14 +33,14 @@ properties:
>          are always on, and for which there are no MPDG bits to control them.
>  
>        - The second power domain specifier cell is the module standby part, and
> -        must be the module number (0x00-0xff), composed of the Module System
> +        must be the module number (0x00-0x1ff), composed of the Module System
>          Reset (MSRES) register index in the high nibble, and the Module Reset

Technically it's high nibble plus one bit, but I think this is fine
as-is.

Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

>          Destination bitfield index in the low nibble.
>      const: 2
>  
>    '#reset-cells':
>      description:
> -      The single reset specifier cell must be the module number (0x00-0xff),
> +      The single reset specifier cell must be the module number (0x00-0x1ff),
>        and thus identical to the second power domain specifier cell.
>      const: 1
>  

-- 
Regards,

Laurent Pinchart

[PATCH v3 14/15] media: vsp1: Complete buffers as queued in start_streaming error path

[Paul Elder]

In the error path of vsp1_video_start_streaming, the queued buffers are
released via vsp1_video_release_buffers with the state
VB2_BUF_STATE_ERROR. This causes subsequent start_streaming calls to hit
the following warning in vb2_start_streaming:

/*
 * If done_list is not empty, then start_streaming() didn't call
 * vb2_buffer_done(vb, VB2_BUF_STATE_QUEUED) but STATE_ERROR or
 * STATE_DONE.
*/
WARN_ON(!list_empty(&q->done_list));

Fix this by completing the queued buffers with the state set to
VB2_BUF_STATE_QUEUED in the error path of vsp1_video_start_streaming.

Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
---
 drivers/media/platform/renesas/vsp1/vsp1_video.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/media/platform/renesas/vsp1/vsp1_video.c b/drivers/media/platform/renesas/vsp1/vsp1_video.c
index b85351986fae50aa678032b05b0352dff2b5a26a..46e0d6f8a66bddb4064e52e1521f3c9da7192868 100644
--- a/drivers/media/platform/renesas/vsp1/vsp1_video.c
+++ b/drivers/media/platform/renesas/vsp1/vsp1_video.c
@@ -765,7 +765,8 @@ static int vsp1_video_setup_pipeline(struct vsp1_pipeline *pipe)
 	return 0;
 }
 
-static void vsp1_video_release_buffers(struct vsp1_video *video)
+static void vsp1_video_release_buffers(struct vsp1_video *video,
+				       enum vb2_buffer_state state)
 {
 	struct vsp1_vb2_buffer *buffer;
 
@@ -773,7 +774,7 @@ static void vsp1_video_release_buffers(struct vsp1_video *video)
 	guard(spinlock_irqsave)(&video->irqlock);
 
 	list_for_each_entry(buffer, &video->irqqueue, queue)
-		vb2_buffer_done(&buffer->buf.vb2_buf, VB2_BUF_STATE_ERROR);
+		vb2_buffer_done(&buffer->buf.vb2_buf, state);
 	INIT_LIST_HEAD(&video->irqqueue);
 }
 
@@ -802,7 +803,7 @@ static int vsp1_video_start_streaming(struct vb2_queue *vq, unsigned int count)
 		if (pipe->stream_count == pipe->num_inputs) {
 			ret = vsp1_video_setup_pipeline(pipe);
 			if (ret < 0) {
-				vsp1_video_release_buffers(video);
+				vsp1_video_release_buffers(video, VB2_BUF_STATE_QUEUED);
 				vsp1_video_cleanup_pipeline(pipe);
 				return ret;
 			}
@@ -858,7 +859,7 @@ static void vsp1_video_stop_streaming(struct vb2_queue *vq)
 	}
 
 	video_device_pipeline_stop(&video->video);
-	vsp1_video_release_buffers(video);
+	vsp1_video_release_buffers(video, VB2_BUF_STATE_ERROR);
 	vsp1_video_pipeline_put(pipe);
 }
 

-- 
2.47.3

Re: [PATCH v3 14/15] media: vsp1: Complete buffers as queued in start_streaming error path

[Laurent Pinchart]

Hi Paul,

Thank you for the patch.

On Thu, Oct 15, 2026 at 04:51:54PM +0900, Paul Elder wrote:
> In the error path of vsp1_video_start_streaming, the queued buffers are
> released via vsp1_video_release_buffers with the state
> VB2_BUF_STATE_ERROR. This causes subsequent start_streaming calls to hit
> the following warning in vb2_start_streaming:
> 
> /*
>  * If done_list is not empty, then start_streaming() didn't call
>  * vb2_buffer_done(vb, VB2_BUF_STATE_QUEUED) but STATE_ERROR or
>  * STATE_DONE.
> */

Missing space. I recommend copying indentation from the original source
to make it clearer:

	/*
	 * If done_list is not empty, then start_streaming() didn't call
	 * vb2_buffer_done(vb, VB2_BUF_STATE_QUEUED) but STATE_ERROR or
	 * STATE_DONE.
	 */
	WARN_ON(!list_empty(&q->done_list));

> WARN_ON(!list_empty(&q->done_list));
> 
> Fix this by completing the queued buffers with the state set to
> VB2_BUF_STATE_QUEUED in the error path of vsp1_video_start_streaming.
> 
> Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>

Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

> ---
>  drivers/media/platform/renesas/vsp1/vsp1_video.c | 9 +++++----
>  1 file changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/media/platform/renesas/vsp1/vsp1_video.c b/drivers/media/platform/renesas/vsp1/vsp1_video.c
> index b85351986fae50aa678032b05b0352dff2b5a26a..46e0d6f8a66bddb4064e52e1521f3c9da7192868 100644
> --- a/drivers/media/platform/renesas/vsp1/vsp1_video.c
> +++ b/drivers/media/platform/renesas/vsp1/vsp1_video.c
> @@ -765,7 +765,8 @@ static int vsp1_video_setup_pipeline(struct vsp1_pipeline *pipe)
>  	return 0;
>  }
>  
> -static void vsp1_video_release_buffers(struct vsp1_video *video)
> +static void vsp1_video_release_buffers(struct vsp1_video *video,
> +				       enum vb2_buffer_state state)
>  {
>  	struct vsp1_vb2_buffer *buffer;
>  
> @@ -773,7 +774,7 @@ static void vsp1_video_release_buffers(struct vsp1_video *video)
>  	guard(spinlock_irqsave)(&video->irqlock);
>  
>  	list_for_each_entry(buffer, &video->irqqueue, queue)
> -		vb2_buffer_done(&buffer->buf.vb2_buf, VB2_BUF_STATE_ERROR);
> +		vb2_buffer_done(&buffer->buf.vb2_buf, state);
>  	INIT_LIST_HEAD(&video->irqqueue);
>  }
>  
> @@ -802,7 +803,7 @@ static int vsp1_video_start_streaming(struct vb2_queue *vq, unsigned int count)
>  		if (pipe->stream_count == pipe->num_inputs) {
>  			ret = vsp1_video_setup_pipeline(pipe);
>  			if (ret < 0) {
> -				vsp1_video_release_buffers(video);
> +				vsp1_video_release_buffers(video, VB2_BUF_STATE_QUEUED);
>  				vsp1_video_cleanup_pipeline(pipe);
>  				return ret;
>  			}
> @@ -858,7 +859,7 @@ static void vsp1_video_stop_streaming(struct vb2_queue *vq)
>  	}
>  
>  	video_device_pipeline_stop(&video->video);
> -	vsp1_video_release_buffers(video);
> +	vsp1_video_release_buffers(video, VB2_BUF_STATE_ERROR);
>  	vsp1_video_pipeline_put(pipe);
>  }
>  

-- 
Regards,

Laurent Pinchart

[PATCH DNI v3 15/15] media: rcar-fcp: Check device revision at probe time

[Paul Elder]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Verify that the device revision register reports a valid value,
otherwise reject the device.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
---
Changes since v2:

- Add FCP type information
- Reject devices with an unsupported version

Changes since v1:

- Use devm_platform_ioremap_resource()
---
 drivers/media/platform/renesas/rcar-fcp.c | 132 +++++++++++++++++++++++++++---
 1 file changed, 121 insertions(+), 11 deletions(-)

diff --git a/drivers/media/platform/renesas/rcar-fcp.c b/drivers/media/platform/renesas/rcar-fcp.c
index 76d4c250b30815d9eac58f9b54ad923748df79f6..5f2c483f71f42f0fc614db216c54d65e2372e8fb 100644
--- a/drivers/media/platform/renesas/rcar-fcp.c
+++ b/drivers/media/platform/renesas/rcar-fcp.c
@@ -14,28 +14,78 @@
 #include <linux/list.h>
 #include <linux/module.h>
 #include <linux/mutex.h>
+#include <linux/of_device.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
+#include <linux/property.h>
 #include <linux/reset.h>
 #include <linux/slab.h>
 
 #include <media/rcar-fcp.h>
 
-#define RCAR_FCP_REG_RST		0x0010
-#define RCAR_FCP_REG_RST_SOFTRST	BIT(0)
-#define RCAR_FCP_REG_STA		0x0018
-#define RCAR_FCP_REG_STA_ACT		BIT(0)
+#define RCAR_FCP_REG_VCR			0x0000
+#define RCAR_FCP_REG_VCR_CATEGORY		(1 << 8)
+#define RCAR_FCP_REG_VCR_REVISION_H3_ES1	(1 << 0)
+#define RCAR_FCP_REG_VCR_REVISION_M3W		(2 << 0)
+#define RCAR_FCP_REG_VCR_REVISION_V3M		(3 << 0)
+#define RCAR_FCP_REG_VCR_REVISION_H3		(4 << 0)
+#define RCAR_FCP_REG_VCR_REVISION_D3		(5 << 0)
+#define RCAR_FCP_REG_VCR_REVISION_M3N		(6 << 0)
+#define RCAR_FCP_REG_VCR_REVISION_V3H		(7 << 0)
+#define RCAR_FCP_REG_VCR_REVISION_E3		(8 << 0)
+#define RCAR_FCP_REG_VCR_REVISION_X5H_V1	(12 << 0)
+
+#define RCAR_FCP_REG_CFG0			0x0004
+#define RCAR_FCP_REG_CFG0_FCPVSEL		BIT(1)
+
+#define RCAR_FCP_REG_RST			0x0010
+#define RCAR_FCP_REG_RST_RIIFRST		BIT(22)
+#define RCAR_FCP_REG_RST_RSIFRST		BIT(21)
+#define RCAR_FCP_REG_RST_DCMPRST		BIT(20)
+#define RCAR_FCP_REG_RST_MODRST			BIT(4)
+#define RCAR_FCP_REG_RST_SOFTRST		BIT(0)
+
+#define RCAR_FCP_REG_STA			0x0018
+#define RCAR_FCP_REG_STA_ACT			BIT(0)
+
+#define RCAR_FCP_REG_TL_CTRL			0x0070
+#define RCAR_FCP_REG_TL_CTRL_TLEN		BIT(31)
+#define RCAR_FCP_REG_TL_CTRL_VPOS_C(n)		((n) << 16)
+#define RCAR_FCP_REG_TL_CTRL_VPOS_Y(n)		((n) << 0)
+
+#define RCAR_FCP_REG_PICINFO1			0x00c4
+#define RCAR_FCP_REG_PICINFO1_STRIDE_DIV16	((n) << 0)
+
+#define RCAR_FCP_REG_BA_ANC_Y0			0x0100
+#define RCAR_FCP_REG_BA_ANC_Y1			0x0104
+#define RCAR_FCP_REG_BA_ANC_Y2			0x0108
+#define RCAR_FCP_REG_BA_ANC_C			0x010c
+#define RCAR_FCP_REG_BA_REF_Y0			0x0110
+#define RCAR_FCP_REG_BA_REF_Y1			0x0114
+#define RCAR_FCP_REG_BA_REF_Y2			0x0118
+#define RCAR_FCP_REG_BA_REF_C			0x011c
+
+enum rcar_fcp_type {
+	RCAR_FCPF,
+	RCAR_FCPV,
+};
 
 struct rcar_fcp_device {
 	struct list_head list;
 	struct device *dev;
 	void __iomem *base;
 	struct reset_control *rstc;
+	enum rcar_fcp_type type;
 };
 
 static LIST_HEAD(fcp_devices);
 static DEFINE_MUTEX(fcp_lock);
 
+static inline u32 rcar_fcp_read(struct rcar_fcp_device *fcp, u32 reg)
+{
+	return ioread32(fcp->base + reg);
+}
+
 static inline void rcar_fcp_write(struct rcar_fcp_device *fcp, u32 reg, u32 val)
 {
 	iowrite32(val, fcp->base + reg);
@@ -154,15 +204,67 @@ EXPORT_SYMBOL_GPL(rcar_fcp_soft_reset);
  * Platform Driver
  */
 
+static int rcar_fcp_setup(struct rcar_fcp_device *fcp)
+{
+	static const char * const models[] = {
+		[RCAR_FCPF] = "FCPF",
+		[RCAR_FCPV] = "FCPV",
+	};
+	static struct {
+		u32 version;
+		const char *name;
+	} versions[] = {
+		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_H3_ES1, "H3 ES1.x" },
+		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_M3W, "M3W" },
+		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_V3M, "V3M" },
+		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_H3, "H3" },
+		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_D3, "D3" },
+		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_M3N, "M3N" },
+		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_V3H, "V3H" },
+		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_E3, "E3" },
+		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_X5H_V1, "X5H v1.0" },
+	};
+
+	unsigned int i;
+	u32 version;
+
+	/* Check the device version register. */
+	version = rcar_fcp_read(fcp, RCAR_FCP_REG_VCR);
+
+	for (i = 0; i < ARRAY_SIZE(versions); ++i) {
+		if (versions[i].version == version)
+			break;
+	}
+
+	if (i >= ARRAY_SIZE(versions)) {
+		dev_err(fcp->dev, "Invalid FCP version 0x%08x\n", version);
+		return -ENODEV;
+	}
+
+	dev_dbg(fcp->dev, "%s %s device found\n", models[fcp->type],
+		versions[i].name);
+
+	return 0;
+}
+
+static const struct of_device_id rcar_fcp_of_match[] = {
+	{ .compatible = "renesas,fcpf", .data = (void *)RCAR_FCPF },
+	{ .compatible = "renesas,fcpv", .data = (void *)RCAR_FCPV },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, rcar_fcp_of_match);
+
 static int rcar_fcp_probe(struct platform_device *pdev)
 {
 	struct rcar_fcp_device *fcp;
+	int ret;
 
 	fcp = devm_kzalloc(&pdev->dev, sizeof(*fcp), GFP_KERNEL);
 	if (fcp == NULL)
 		return -ENOMEM;
 
 	fcp->dev = &pdev->dev;
+	fcp->type = (enum rcar_fcp_type)device_get_match_data(&pdev->dev);
 
 	platform_set_drvdata(pdev, fcp);
 
@@ -178,12 +280,27 @@ static int rcar_fcp_probe(struct platform_device *pdev)
 				     "failed to get reset control\n");
 
 	pm_runtime_enable(&pdev->dev);
+	ret = pm_runtime_resume_and_get(&pdev->dev);
+	if (ret < 0)
+		goto error_pm_disable;
+
+	ret = rcar_fcp_setup(fcp);
+	if (ret < 0)
+		goto error_pm_put;
+
+	pm_runtime_put(&pdev->dev);
 
 	mutex_lock(&fcp_lock);
 	list_add_tail(&fcp->list, &fcp_devices);
 	mutex_unlock(&fcp_lock);
 
 	return 0;
+
+error_pm_put:
+	pm_runtime_put(&pdev->dev);
+error_pm_disable:
+	pm_runtime_disable(&pdev->dev);
+	return ret;
 }
 
 static void rcar_fcp_remove(struct platform_device *pdev)
@@ -215,13 +332,6 @@ static const struct dev_pm_ops fcp_pm_ops = {
 	RUNTIME_PM_OPS(fcp_pm_runtime_suspend, fcp_pm_runtime_resume, NULL)
 };
 
-static const struct of_device_id rcar_fcp_of_match[] = {
-	{ .compatible = "renesas,fcpf" },
-	{ .compatible = "renesas,fcpv" },
-	{ },
-};
-MODULE_DEVICE_TABLE(of, rcar_fcp_of_match);
-
 static struct platform_driver rcar_fcp_platform_driver = {
 	.probe		= rcar_fcp_probe,
 	.remove		= rcar_fcp_remove,

-- 
2.47.3

Re: [PATCH DNI v3 15/15] media: rcar-fcp: Check device revision at probe time

[Geert Uytterhoeven]

Hi Paul,

On Thu, 15 Oct 2026 at 09:53, Paul Elder
<paul.elder+renesas@ideasonboard.com> wrote:
> From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
>
> Verify that the device revision register reports a valid value,
> otherwise reject the device.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>

Thanks for your patch!

> --- a/drivers/media/platform/renesas/rcar-fcp.c
> +++ b/drivers/media/platform/renesas/rcar-fcp.c

> +
> +static const struct of_device_id rcar_fcp_of_match[] = {
> +       { .compatible = "renesas,fcpf", .data = (void *)RCAR_FCPF },
> +       { .compatible = "renesas,fcpv", .data = (void *)RCAR_FCPV },
> +       { },
> +};
> +MODULE_DEVICE_TABLE(of, rcar_fcp_of_match);

I don't see a good reason for moving this around?

> +
>  static int rcar_fcp_probe(struct platform_device *pdev)
>  {
>         struct rcar_fcp_device *fcp;
> +       int ret;
>
>         fcp = devm_kzalloc(&pdev->dev, sizeof(*fcp), GFP_KERNEL);
>         if (fcp == NULL)
>                 return -ENOMEM;
>
>         fcp->dev = &pdev->dev;
> +       fcp->type = (enum rcar_fcp_type)device_get_match_data(&pdev->dev);

s/rcar_fcp_type/uintptr_t/, although this no longer seems to trigger
a conversion between pointer and integer of different sizes warning?

>
>         platform_set_drvdata(pdev, fcp);
>

> @@ -215,13 +332,6 @@ static const struct dev_pm_ops fcp_pm_ops = {
>         RUNTIME_PM_OPS(fcp_pm_runtime_suspend, fcp_pm_runtime_resume, NULL)
>  };
>
> -static const struct of_device_id rcar_fcp_of_match[] = {
> -       { .compatible = "renesas,fcpf" },
> -       { .compatible = "renesas,fcpv" },
> -       { },
> -};
> -MODULE_DEVICE_TABLE(of, rcar_fcp_of_match);
> -
>  static struct platform_driver rcar_fcp_platform_driver = {
>         .probe          = rcar_fcp_probe,
>         .remove         = rcar_fcp_remove,
>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH DNI v3 15/15] media: rcar-fcp: Check device revision at probe time

[Laurent Pinchart]

On Tue, Oct 20, 2026 at 02:20:43PM +0200, Geert Uytterhoeven wrote:
> On Thu, 15 Oct 2026 at 09:53, Paul Elder wrote:
> > From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> >
> > Verify that the device revision register reports a valid value,
> > otherwise reject the device.
> >
> > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
> 
> Thanks for your patch!
> 
> > --- a/drivers/media/platform/renesas/rcar-fcp.c
> > +++ b/drivers/media/platform/renesas/rcar-fcp.c
> 
> > +
> > +static const struct of_device_id rcar_fcp_of_match[] = {
> > +       { .compatible = "renesas,fcpf", .data = (void *)RCAR_FCPF },
> > +       { .compatible = "renesas,fcpv", .data = (void *)RCAR_FCPV },
> > +       { },
> > +};
> > +MODULE_DEVICE_TABLE(of, rcar_fcp_of_match);
> 
> I don't see a good reason for moving this around?

I think it's a leftover from the original version of the patch, which
was using of_match_device(). It's not needed any more now that the code
below uses device_get_match_data()/

> > +
> >  static int rcar_fcp_probe(struct platform_device *pdev)
> >  {
> >         struct rcar_fcp_device *fcp;
> > +       int ret;
> >
> >         fcp = devm_kzalloc(&pdev->dev, sizeof(*fcp), GFP_KERNEL);
> >         if (fcp == NULL)
> >                 return -ENOMEM;
> >
> >         fcp->dev = &pdev->dev;
> > +       fcp->type = (enum rcar_fcp_type)device_get_match_data(&pdev->dev);
> 
> s/rcar_fcp_type/uintptr_t/, although this no longer seems to trigger
> a conversion between pointer and integer of different sizes warning?
> 
> >
> >         platform_set_drvdata(pdev, fcp);
> >
> 
> > @@ -215,13 +332,6 @@ static const struct dev_pm_ops fcp_pm_ops = {
> >         RUNTIME_PM_OPS(fcp_pm_runtime_suspend, fcp_pm_runtime_resume, NULL)
> >  };
> >
> > -static const struct of_device_id rcar_fcp_of_match[] = {
> > -       { .compatible = "renesas,fcpf" },
> > -       { .compatible = "renesas,fcpv" },
> > -       { },
> > -};
> > -MODULE_DEVICE_TABLE(of, rcar_fcp_of_match);
> > -
> >  static struct platform_driver rcar_fcp_platform_driver = {
> >         .probe          = rcar_fcp_probe,
> >         .remove         = rcar_fcp_remove,
> >

-- 
Regards,

Laurent Pinchart

Re: [PATCH DNI v3 15/15] media: rcar-fcp: Check device revision at probe time

[Geert Uytterhoeven]

Hi Paul,

On Thu, 15 Oct 2026 at 09:53, Paul Elder
<paul.elder+renesas@ideasonboard.com> wrote:
> From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
>
> Verify that the device revision register reports a valid value,
> otherwise reject the device.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
> ---
> Changes since v2:
>
> - Add FCP type information
> - Reject devices with an unsupported version

Thanks for the update!

> --- a/drivers/media/platform/renesas/rcar-fcp.c
> +++ b/drivers/media/platform/renesas/rcar-fcp.c

> @@ -154,15 +204,67 @@ EXPORT_SYMBOL_GPL(rcar_fcp_soft_reset);
>   * Platform Driver
>   */
>
> +static int rcar_fcp_setup(struct rcar_fcp_device *fcp)
> +{
> +       static const char * const models[] = {
> +               [RCAR_FCPF] = "FCPF",
> +               [RCAR_FCPV] = "FCPV",
> +       };
> +       static struct {
> +               u32 version;
> +               const char *name;
> +       } versions[] = {
> +               { RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_H3_ES1, "H3 ES1.x" },
> +               { RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_M3W, "M3W" },
> +               { RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_V3M, "V3M" },
> +               { RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_H3, "H3" },
> +               { RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_D3, "D3" },
> +               { RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_M3N, "M3N" },
> +               { RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_V3H, "V3H" },
> +               { RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_E3, "E3" },
> +               { RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_X5H_V1, "X5H v1.0" },
> +       };
> +
> +       unsigned int i;
> +       u32 version;
> +
> +       /* Check the device version register. */
> +       version = rcar_fcp_read(fcp, RCAR_FCP_REG_VCR);
> +
> +       for (i = 0; i < ARRAY_SIZE(versions); ++i) {
> +               if (versions[i].version == version)
> +                       break;
> +       }
> +
> +       if (i >= ARRAY_SIZE(versions)) {
> +               dev_err(fcp->dev, "Invalid FCP version 0x%08x\n", version);

You're missing a few variants:

    R-Car V4H: rcar-fcp fea10000.fcp: Invalid FCP version 0x0000010a
    R-Car V4M: rcar-fcp fea10000.fcp: Invalid FCP version 0x0000010b

> +               return -ENODEV;
> +       }

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds