[PATCH v3 0/1] cpufreq/amd-pstate: Fix EPP initialization for shared memory systems

[PATCH v3 0/1] cpufreq/amd-pstate: Fix EPP initialization for shared memory systems

[Marco Scardovi]

Hi Prateek, Mario,

Following discussion, I have dropped the previous second patch (EPP capability
checks) since EPP is supported on all Zen CPUs that support CPPC. The
frequency capping on Zen 2 systems was purely caused by a false cache hit
during driver initialization.

Thus, we consolidate the series to a single patch that fixes the false EPP
cache hit at boot and explicitly toggles AUTO_SEL_ENABLE on shared memory
systems.

If you have a znver2 or 1 under hand please test them as I don't own them.

Changes in v3:
- Patch 1: Cache the firmware-programmed default EPP value at CPU EPP
  initialization (resolving the boot-time false cache hit) and explicitly
  toggle the AUTO_SEL_ENABLE register to 1 on shared memory systems,
  rather than utilizing a state-tracking flag as proposed in v2.
- Patch 2: Dropped as CPPC systems universally support EPP.

Changes in v2:
- Patch 1: Rename `epp_initialized` to `epp_hw_programmed` and add a comment
  documenting the EPP cache guard optimization behavior.
- Patch 2: Add comments explaining the uniform CPU capability check on x86,
  handle EPP capability check errors robustly (only treat -EOPNOTSUPP as
  unsupported, warn and assume supported for other errors to avoid false
  negatives), and reject runtime active mode transitions at sysfs store time
  (preventing the driver from being left in an unregistered state).

Changes in v1:
- Fix the boot-time CPPC EPP/auto_sel initialization regression in
  shmem_set_epp() using a state tracking flag while preserving runtime
  cache optimization.
- Add an EPP capability check helper during initialization.
- Fall back to passive mode at boot if EPP is not supported, and reject
  transitions to active mode at runtime if EPP is not supported.


Marco Scardovi (1):
  cpufreq/amd-pstate: Fix EPP initialization for shared memory systems

 drivers/cpufreq/amd-pstate.c | 24 +++++++++++++++++++++++-
 1 file changed, 23 insertions(+), 1 deletion(-)

-- 
2.54.0

[PATCH v3 1/1] cpufreq/amd-pstate: Fix EPP initialization for shared memory systems

[Marco Scardovi]

At CPU initialization, the private cpudata structure is allocated via
kzalloc, which means cpudata->cppc_req_cached is initialized to 0. This
makes the default cached EPP value 0 (AMD_CPPC_EPP_PERFORMANCE).

When initializing a system that defaults to performance EPP, the driver
attempts to configure the EPP via amd_pstate_set_epp(). Because the
requested EPP (0) matches the uninitialized cached value (0), the cache
guard check triggers, and the driver skips writing to the hardware.

On shared memory systems, the EPP write via cppc_set_epp_perf() is also
responsible for toggling on the autonomous selection register (auto_sel).
Skipping the EPP write consequently skips enabling auto_sel, leaving the
CPU in non-autonomous mode. This prevents the hardware from boosting and
leaves the CPU frequency stuck at the lowest non-linear frequency (1.7GHz).

Fix this by:
1. Cache the firmware programmed default EPP value in cppc_req_cached
   during CPU EPP initialization.
2. Explicitly toggle the AUTO_SEL_ENABLE register to 1 during EPP CPU
   initialization for shared memory systems, independent of whether the EPP
   write is skipped due to a cache match.

Fixes: ffa5096a7c33 ("cpufreq: amd-pstate: implement Pstate EPP support for the AMD processors")
Link: https://bugzilla.kernel.org/show_bug.cgi?id=221473
Suggested-by: Mario Limonciello <mario.limonciello@amd.com>
Suggested-by: K Prateek Nayak <kprateek.nayak@amd.com>
Assisted-by: Antigravity:gemini-3.5-flash
Signed-off-by: Marco Scardovi <scardracs@disroot.org>
---
 drivers/cpufreq/amd-pstate.c | 24 +++++++++++++++++++++++-
 1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
index 8d55e2be825b..8e0099eba512 100644
--- a/drivers/cpufreq/amd-pstate.c
+++ b/drivers/cpufreq/amd-pstate.c
@@ -1877,6 +1877,7 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy)
 	struct amd_cpudata *cpudata;
 	union perf_cached perf;
 	struct device *dev;
+	s16 default_epp;
 	int ret;
 
 	/*
@@ -1926,6 +1927,27 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy)
 
 	policy->boost_supported = READ_ONCE(cpudata->boost_supported);
 
+	/* Cache the firmware programmed EPP */
+	default_epp = amd_pstate_get_epp(cpudata);
+	if (default_epp < 0) {
+		ret = default_epp;
+		goto free_cpudata1;
+	}
+	FIELD_MODIFY(AMD_CPPC_EPP_PERF_MASK, &cpudata->cppc_req_cached, default_epp);
+
+	/*
+	 * Shared memory based systems may require the AUTO_SEL_ENABLE register
+	 * to be toggled on to function correctly. Since the first call to
+	 * amd_pstate_set_epp() may bail out early if the desired EPP is
+	 * same as the one configured by the firmware, attempt to toggle the
+	 * AUTO_SEL_ENABLE here, independent of EPP programming.
+	 */
+	if (!cpu_feature_enabled(X86_FEATURE_CPPC)) {
+		ret = cppc_set_auto_sel(policy->cpu, 1);
+		if (ret)
+			pr_warn("failed to enable auto_sel for cpu %d: %d\n", policy->cpu, ret);
+	}
+
 	/*
 	 * Set the policy to provide a valid fallback value in case
 	 * the default cpufreq governor is neither powersave nor performance.
@@ -1933,7 +1955,7 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy)
 	if (amd_pstate_acpi_pm_profile_server() ||
 	    amd_pstate_acpi_pm_profile_undefined()) {
 		policy->policy = CPUFREQ_POLICY_PERFORMANCE;
-		cpudata->epp_default_ac = cpudata->epp_default_dc = amd_pstate_get_epp(cpudata);
+		cpudata->epp_default_ac = cpudata->epp_default_dc = default_epp;
 		cpudata->current_profile = PLATFORM_PROFILE_PERFORMANCE;
 	} else {
 		policy->policy = CPUFREQ_POLICY_POWERSAVE;
-- 
2.54.0

Re: [PATCH v3 1/1] cpufreq/amd-pstate: Fix EPP initialization for shared memory systems

[Mario Limonciello]

On 6/5/26 05:26, Marco Scardovi wrote:
> At CPU initialization, the private cpudata structure is allocated via
> kzalloc, which means cpudata->cppc_req_cached is initialized to 0. This
> makes the default cached EPP value 0 (AMD_CPPC_EPP_PERFORMANCE).
> 
> When initializing a system that defaults to performance EPP, the driver
> attempts to configure the EPP via amd_pstate_set_epp(). Because the
> requested EPP (0) matches the uninitialized cached value (0), the cache
> guard check triggers, and the driver skips writing to the hardware.
> 
> On shared memory systems, the EPP write via cppc_set_epp_perf() is also
> responsible for toggling on the autonomous selection register (auto_sel).
> Skipping the EPP write consequently skips enabling auto_sel, leaving the
> CPU in non-autonomous mode. This prevents the hardware from boosting and
> leaves the CPU frequency stuck at the lowest non-linear frequency (1.7GHz).
> 
> Fix this by:
> 1. Cache the firmware programmed default EPP value in cppc_req_cached
>     during CPU EPP initialization.
> 2. Explicitly toggle the AUTO_SEL_ENABLE register to 1 during EPP CPU
>     initialization for shared memory systems, independent of whether the EPP
>     write is skipped due to a cache match.
> 
> Fixes: ffa5096a7c33 ("cpufreq: amd-pstate: implement Pstate EPP support for the AMD processors")
> Link: https://bugzilla.kernel.org/show_bug.cgi?id=221473
> Suggested-by: Mario Limonciello <mario.limonciello@amd.com>
> Suggested-by: K Prateek Nayak <kprateek.nayak@amd.com>
> Assisted-by: Antigravity:gemini-3.5-flash
> Signed-off-by: Marco Scardovi <scardracs@disroot.org>
> ---
>   drivers/cpufreq/amd-pstate.c | 24 +++++++++++++++++++++++-
>   1 file changed, 23 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
> index 8d55e2be825b..8e0099eba512 100644
> --- a/drivers/cpufreq/amd-pstate.c
> +++ b/drivers/cpufreq/amd-pstate.c
> @@ -1877,6 +1877,7 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy)
>   	struct amd_cpudata *cpudata;
>   	union perf_cached perf;
>   	struct device *dev;
> +	s16 default_epp;

Reviewing this code I realize we have a problem with the return types.

Both possible functions return u8:

static u8 msr_get_epp(struct amd_cpudata *cpudata)
static u8 shmem_get_epp(struct amd_cpudata *cpudata)

The static call returns s16:
static inline s16 amd_pstate_get_epp(struct amd_cpudata *cpudata)

But then both shmem_get_epp and msr_get_epp can return negative integers 
on failure.

So the return type for all of them should be changed to be an integer to 
support this change.

Als othe variable used in amd_pstate_epp_cpu_init needs to be an integer 
too.

>   	int ret;
>   
>   	/*
> @@ -1926,6 +1927,27 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy)
>   
>   	policy->boost_supported = READ_ONCE(cpudata->boost_supported);
>   
> +	/* Cache the firmware programmed EPP */
> +	default_epp = amd_pstate_get_epp(cpudata);
> +	if (default_epp < 0) {
> +		ret = default_epp;
> +		goto free_cpudata1;
> +	}
> +	FIELD_MODIFY(AMD_CPPC_EPP_PERF_MASK, &cpudata->cppc_req_cached, default_epp);
> +
> +	/*
> +	 * Shared memory based systems may require the AUTO_SEL_ENABLE register
> +	 * to be toggled on to function correctly. Since the first call to
> +	 * amd_pstate_set_epp() may bail out early if the desired EPP is
> +	 * same as the one configured by the firmware, attempt to toggle the
> +	 * AUTO_SEL_ENABLE here, independent of EPP programming.
> +	 */
> +	if (!cpu_feature_enabled(X86_FEATURE_CPPC)) {
> +		ret = cppc_set_auto_sel(policy->cpu, 1);
> +		if (ret)
> +			pr_warn("failed to enable auto_sel for cpu %d: %d\n", policy->cpu, ret);
> +	}

This doesn't really make sense to me.  I think it's actually pointing to 
a logic error in shmem_init_perf().

I think you can just drop the call to bail in active mode and get the 
same result.

> +
>   	/*
>   	 * Set the policy to provide a valid fallback value in case
>   	 * the default cpufreq governor is neither powersave nor performance.
> @@ -1933,7 +1955,7 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy)
>   	if (amd_pstate_acpi_pm_profile_server() ||
>   	    amd_pstate_acpi_pm_profile_undefined()) {
>   		policy->policy = CPUFREQ_POLICY_PERFORMANCE;
> -		cpudata->epp_default_ac = cpudata->epp_default_dc = amd_pstate_get_epp(cpudata);
> +		cpudata->epp_default_ac = cpudata->epp_default_dc = default_epp;
>   		cpudata->current_profile = PLATFORM_PROFILE_PERFORMANCE;
>   	} else {
>   		policy->policy = CPUFREQ_POLICY_POWERSAVE;