From: "Jiaxun Yang" <jiaxun.yang@flygoat.com>
To: "Huacai Chen" <chenhuacai@kernel.org>
Cc: "Xuerui Wang" <kernel@xen0n.name>,
"Rafael J. Wysocki" <rafael@kernel.org>,
"Viresh Kumar" <viresh.kumar@linaro.org>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Thomas Bogendoerfer" <tsbogend@alpha.franken.de>,
loongarch@lists.linux.dev, linux-kernel@vger.kernel.org,
linux-pm@vger.kernel.org,
"linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>,
kvm@vger.kernel.org
Subject: Re: [PATCH v2 1/4] LoongArch: Probe more CPU features from CPUCFG
Date: Fri, 13 Sep 2024 10:10:09 +0100 [thread overview]
Message-ID: <84c6e819-e2b8-40b6-8de4-9f550e652acc@app.fastmail.com> (raw)
In-Reply-To: <CAAhV-H74OCxnRQjHXtu-CuVaEb5bsMQ4vR4wCOvztZdV-HWEVg@mail.gmail.com>
在2024年9月13日九月 上午9:46，Huacai Chen写道：
> Hi, Jiaxun,
>
> On Fri, Sep 13, 2024 at 4:56 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>>
>> Probe ISA level, TLB, IOCSR information from CPUCFG to
>> improve kernel resilience to different core implementations.
>>
>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>> ---
>> arch/loongarch/include/asm/cpu.h | 4 +++
>> arch/loongarch/include/asm/loongarch.h | 3 +-
>> arch/loongarch/kernel/cpu-probe.c | 54 ++++++++++++++++++++++++----------
>> 3 files changed, 44 insertions(+), 17 deletions(-)
>>
>> diff --git a/arch/loongarch/include/asm/cpu.h b/arch/loongarch/include/asm/cpu.h
>> index 843f9c4ec980..251a15439cff 100644
>> --- a/arch/loongarch/include/asm/cpu.h
>> +++ b/arch/loongarch/include/asm/cpu.h
>> @@ -100,6 +100,8 @@ enum cpu_type_enum {
>> #define CPU_FEATURE_HYPERVISOR 25 /* CPU has hypervisor (running in VM) */
>> #define CPU_FEATURE_PTW 26 /* CPU has hardware page table walker */
>> #define CPU_FEATURE_AVECINT 27 /* CPU has avec interrupt */
>> +#define CPU_FEATURE_IOCSR 28 /* CPU has IOCSR */
>> +#define CPU_FEATURE_LSPW 29 /* CPU has LSPW */
> I don't see LSPW being used, so just remove it now?
I’m going to submit a page table walker for CPU without SPW later on :-)
I’m fine with adding that later.
Thanks
- Jiaxun
>
>>
>> #define LOONGARCH_CPU_CPUCFG BIT_ULL(CPU_FEATURE_CPUCFG)
>> #define LOONGARCH_CPU_LAM BIT_ULL(CPU_FEATURE_LAM)
>> @@ -129,5 +131,7 @@ enum cpu_type_enum {
>> #define LOONGARCH_CPU_HYPERVISOR BIT_ULL(CPU_FEATURE_HYPERVISOR)
>> #define LOONGARCH_CPU_PTW BIT_ULL(CPU_FEATURE_PTW)
>> #define LOONGARCH_CPU_AVECINT BIT_ULL(CPU_FEATURE_AVECINT)
>> +#define LOONGARCH_CPU_IOCSR BIT_ULL(CPU_FEATURE_IOCSR)
>> +#define LOONGARCH_CPU_LSPW BIT_ULL(CPU_FEATURE_LSPW)
>>
>> #endif /* _ASM_CPU_H */
>> diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
>> index 631d249b3ef2..23af28f00c3c 100644
>> --- a/arch/loongarch/include/asm/loongarch.h
>> +++ b/arch/loongarch/include/asm/loongarch.h
>> @@ -60,8 +60,7 @@
>> #define CPUCFG0_PRID GENMASK(31, 0)
>>
>> #define LOONGARCH_CPUCFG1 0x1
>> -#define CPUCFG1_ISGR32 BIT(0)
>> -#define CPUCFG1_ISGR64 BIT(1)
>> +#define CPUCFG1_ISA GENMASK(1, 0)
>> #define CPUCFG1_PAGING BIT(2)
>> #define CPUCFG1_IOCSR BIT(3)
>> #define CPUCFG1_PABITS GENMASK(11, 4)
>> diff --git a/arch/loongarch/kernel/cpu-probe.c b/arch/loongarch/kernel/cpu-probe.c
>> index 14f0449f5452..5dc8ca3c4387 100644
>> --- a/arch/loongarch/kernel/cpu-probe.c
>> +++ b/arch/loongarch/kernel/cpu-probe.c
>> @@ -92,11 +92,29 @@ static void cpu_probe_common(struct cpuinfo_loongarch *c)
>> unsigned long asid_mask;
>>
>> c->options = LOONGARCH_CPU_CPUCFG | LOONGARCH_CPU_CSR |
>> - LOONGARCH_CPU_TLB | LOONGARCH_CPU_VINT | LOONGARCH_CPU_WATCH;
>> + LOONGARCH_CPU_VINT | LOONGARCH_CPU_WATCH;
>>
>> elf_hwcap = HWCAP_LOONGARCH_CPUCFG;
>>
>> config = read_cpucfg(LOONGARCH_CPUCFG1);
>> +
>> + switch (config & CPUCFG1_ISA) {
>> + case 0:
>> + set_isa(c, LOONGARCH_CPU_ISA_LA32R);
>> + break;
>> + case 1:
>> + set_isa(c, LOONGARCH_CPU_ISA_LA32S);
>> + break;
>> + case 2:
>> + set_isa(c, LOONGARCH_CPU_ISA_LA64);
>> + break;
>> + default:
>> + pr_warn("Warning: unknown ISA level\n");
>> + }
>> + if (config & CPUCFG1_PAGING)
>> + c->options |= LOONGARCH_CPU_TLB;
>> + if (config & CPUCFG1_IOCSR)
>> + c->options |= LOONGARCH_CPU_IOCSR;
>> if (config & CPUCFG1_UAL) {
>> c->options |= LOONGARCH_CPU_UAL;
>> elf_hwcap |= HWCAP_LOONGARCH_UAL;
>> @@ -157,6 +175,8 @@ static void cpu_probe_common(struct cpuinfo_loongarch *c)
>> elf_hwcap |= HWCAP_LOONGARCH_LBT_MIPS;
>> }
>> #endif
>> + if (config & CPUCFG2_LSPW)
>> + c->options |= LOONGARCH_CPU_LSPW;
>>
>> config = read_cpucfg(LOONGARCH_CPUCFG6);
>> if (config & CPUCFG6_PMP)
>> @@ -222,6 +242,7 @@ static inline void cpu_probe_loongson(struct cpuinfo_loongarch *c, unsigned int
>> {
>> uint64_t *vendor = (void *)(&cpu_full_name[VENDOR_OFFSET]);
>> uint64_t *cpuname = (void *)(&cpu_full_name[CPUNAME_OFFSET]);
>> + const char *core_name = "Unknown";
>>
>> if (!__cpu_full_name[cpu])
>> __cpu_full_name[cpu] = cpu_full_name;
>> @@ -232,40 +253,43 @@ static inline void cpu_probe_loongson(struct cpuinfo_loongarch *c, unsigned int
>> switch (c->processor_id & PRID_SERIES_MASK) {
>> case PRID_SERIES_LA132:
>> c->cputype = CPU_LOONGSON32;
>> - set_isa(c, LOONGARCH_CPU_ISA_LA32S);
>> __cpu_family[cpu] = "Loongson-32bit";
>> - pr_info("32-bit Loongson Processor probed (LA132 Core)\n");
>> + core_name = "LA132";
>> break;
>> case PRID_SERIES_LA264:
>> c->cputype = CPU_LOONGSON64;
>> - set_isa(c, LOONGARCH_CPU_ISA_LA64);
>> __cpu_family[cpu] = "Loongson-64bit";
>> - pr_info("64-bit Loongson Processor probed (LA264 Core)\n");
>> + core_name = "LA264";
>> break;
>> case PRID_SERIES_LA364:
>> c->cputype = CPU_LOONGSON64;
>> - set_isa(c, LOONGARCH_CPU_ISA_LA64);
>> __cpu_family[cpu] = "Loongson-64bit";
>> - pr_info("64-bit Loongson Processor probed (LA364 Core)\n");
>> + core_name = "LA364";
>> break;
>> case PRID_SERIES_LA464:
>> c->cputype = CPU_LOONGSON64;
>> - set_isa(c, LOONGARCH_CPU_ISA_LA64);
>> __cpu_family[cpu] = "Loongson-64bit";
>> - pr_info("64-bit Loongson Processor probed (LA464 Core)\n");
>> + core_name = "LA464";
>> break;
>> case PRID_SERIES_LA664:
>> c->cputype = CPU_LOONGSON64;
>> - set_isa(c, LOONGARCH_CPU_ISA_LA64);
>> __cpu_family[cpu] = "Loongson-64bit";
>> - pr_info("64-bit Loongson Processor probed (LA664 Core)\n");
>> + core_name = "LA664";
>> break;
>> default: /* Default to 64 bit */
>> - c->cputype = CPU_LOONGSON64;
>> - set_isa(c, LOONGARCH_CPU_ISA_LA64);
>> - __cpu_family[cpu] = "Loongson-64bit";
>> - pr_info("64-bit Loongson Processor probed (Unknown Core)\n");
>> + if (c->isa_level & LOONGARCH_CPU_ISA_LA64) {
>> + c->cputype = CPU_LOONGSON64;
>> + __cpu_family[cpu] = "Loongson-64bit";
>> + } else if (c->isa_level & LOONGARCH_CPU_ISA_LA32S) {
>> + c->cputype = CPU_LOONGSON32;
>> + __cpu_family[cpu] = "Loongson-32bit";
>> + } else if (c->isa_level & LOONGARCH_CPU_ISA_LA32R) {
>> + c->cputype = CPU_LOONGSON32;
>> + __cpu_family[cpu] = "Loongson-32bit Reduced";
>> + }
> I prefer to move this part before the switch-case of PRID (and it is
> better to convert to a switch-case too), then the switch-case of PRID
> can be only used for probing core-name.
>
> Huacai
>
>> }
>> +
>> + pr_info("%s Processor probed (%s Core)\n", __cpu_family[cpu], core_name);
>> }
>>
>> #ifdef CONFIG_64BIT
>>
>> --
>> 2.46.0
>>
--
- Jiaxun
next prev parent reply other threads:[~2024-09-13 9:10 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-12 20:55 [PATCH v2 0/4] LoongArch, MIPS: Unify Loongson IOCSR handling Jiaxun Yang
2024-09-12 20:55 ` [PATCH v2 1/4] LoongArch: Probe more CPU features from CPUCFG Jiaxun Yang
2024-09-13 8:46 ` Huacai Chen
2024-09-13 9:10 ` Jiaxun Yang [this message]
2024-09-12 20:55 ` [PATCH v2 2/4] LoongArch: cpu-probe: Move IOCSR probing out of cpu_probe_common Jiaxun Yang
2024-09-12 20:59 ` Jiaxun Yang
2024-09-13 8:48 ` Huacai Chen
2024-09-12 20:55 ` [PATCH v2 3/4] LoongArch: Extract IOCSR definitions to standalone header Jiaxun Yang
2024-09-12 20:55 ` [PATCH v2 4/4] MIPS: Loongson64: Use shared IOCSR header Jiaxun Yang
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