Re: [PATCH 1/2] x86: intel_pstate: Fix wrong definition of Disable Energy Efficiency Optimization bit

[Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>]

On Sun, 2019-04-14 at 23:48 +0300, Liran Alon wrote:
> Bit definition can be found in Intel SDM Section 2.16 MSRS IN THE 6TH
> GENERATION, 7TH GENERATION AND 8TH GENERATION
> INTEL® CORE™ PROCESSORS, INTEL® XEON® PROCESSOR SCALABLE
> FAMILY, AND FUTURE INTEL® CORE™ PROCESSORS.
> 
> Definition of all Skylake MSR_POWER_CTL bits can also be found at
> EDK2
> source at UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h union
> MSR_SKYLAKE_POWER_CTL_REGISTER.
> 
> Fixes: 6e978b22efa1 ("cpufreq: intel_pstate: Disable energy
> efficiency optimization")
What are you trying to address? This bit 19 has a special meaning when
system is in HWP mode. So this is correct.

Bit 20 has a different meaning depending on legacy or in HWP mode.

Thanks,
Srinivas




> 
> Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
> Signed-off-by: Liran Alon <liran.alon@oracle.com>
> ---
>  drivers/cpufreq/intel_pstate.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/cpufreq/intel_pstate.c
> b/drivers/cpufreq/intel_pstate.c
> index dd66decf2087..3ce39c332c7b 100644
> --- a/drivers/cpufreq/intel_pstate.c
> +++ b/drivers/cpufreq/intel_pstate.c
> @@ -1200,7 +1200,7 @@ static void intel_pstate_hwp_enable(struct
> cpudata *cpudata)corrrect
>  		cpudata->epp_default = intel_pstate_get_epp(cpudata,
> 0);
>  }
>  
> -#define MSR_IA32_POWER_CTL_BIT_EE	19
> +#define MSR_IA32_POWER_CTL_BIT_EE	20
>  
>  /* Disable energy efficiency optimization */
>  static void intel_pstate_disable_ee(int cpu)