[PATCH v4 0/4] Add RZ/G2L MTU3a MFD, Counter and pwm driver

[PATCH v4 0/4] Add RZ/G2L MTU3a MFD, Counter and pwm driver

[Biju Das]

The RZ/G2L multi-function timer pulse unit 3 (MTU3a) is embedded in
the Renesas RZ/G2L family SoC's. It consists of eight 16-bit timer
channels and one 32-bit timer channel. It supports the following
functions
 - Counter
 - Timer
 - PWM

This patch series aim to add MFD and pwm driver for MTU3a.

The 8/16/32 bit registers are mixed in each channel. The HW
specifications of the IP is described in patch#1.

Current patch set is tested for PWM mode1 on MTU3 channel
and 16 and 32 bit phase counting modes.

v3->v4:
 * Dropped counter and pwm compatibeles as they don't have any resources.
 * Made rz-mtu3 as pwm provider.
 * Updated the example and description.
 * A single driver that registers both the counter and the pwm functionalities
   that binds against "renesas,rz-mtu3".
 * Moved PM handling from child devices to here.
 * replaced include/linux/mfd/rz-mtu3.h->drivers/mfd/rz-mtu3.h
 * Removed "remove" callback from mfd driver
 * There is no resource associated with "rz-mtu3-counter" and "rz-mtu3-pwm"
   compatible and moved the code to mfd subsystem as it binds against "rz-mtu".
 * Removed struct platform_driver rz_mtu3_cnt_driver.
 * Removed struct platform_driver rz_mtu3_pwm_driver.
 * Updated commit description
 * Updated Kconfig description
 * Added macros RZ_MTU3_16_BIT_MTU{1,2}_CH for MTU1 and MTU2 channels
 * Added RZ_MTU3_GET_HW_CH macro for getting channel ID.
 * replaced priv->ch[id]->priv->ch[0] in rz_mtu3_count_read()
 * Cached counter max values
 * replaced cnt->tsr in rz_mtu3_count_direction_read()
 * Added comments for RZ_MTU3_TCR_CCLR_NONE
 * Replaced if with switch in rz_mtu3_initialize_counter() and
   rz_mtu3_count_ceiling_write()
 * Added locks in initialize, terminate and enable_read to prevent races.
 * Updated rz_mtu3_action_read to take care of MTU2 signals.
 * Added separate distinct array for each group of Synapse.
 * Moved pm handling to parent.
v2->v3:
 * Dropped counter bindings and integrated with mfd as it has only one property.
 * Removed "#address-cells" and "#size-cells" as it do not have children with
   unit addresses.
 * Removed quotes from counter and pwm.
 * Provided full path for pwm bindings.
 * Updated the binding example.
 * removed unwanted header files
 * Added LUT for 32 bit registers as it needed for 32-bit cascade counting.
 * Exported 32 bit read/write functions.
 * Modelled as a counter device supporting 3 counters(2 16-bit and 
   32-bit)
 * Add kernel-doc comments to document struct rz_mtu3_cnt
 * Removed mmio variable from struct rz_mtu3_cnt
 * Removed cnt local variable from rz_mtu3_count_read()
 * Replaced -EINVAL->-ERANGE for out of range error conditions.
 * Removed explicit cast from write functions.
 * Removed local variable val from rz_mtu3_count_ceiling_read()
 * Added lock for RMW for counter/ceiling updates.
 * Added different synapses for counter0 and counter{1,2}
 * Used ARRAY for assigning num_counts.
 * Added PM runtime for managing clocks.
 * Add MODULE_IMPORT_NS(COUNTER) to import the COUNTER namespace.

RFC->v2:
 * replaced devm_reset_control_get->devm_reset_control_get_exclusive
 * Dropped 'bindings' from the binding title
 * Updated the binding example
 * Added additionalProperties: false for counter bindings
 * Squashed all the binding patches
 * Modelled as a single counter device providing both 16-bit
   and 32-bit phase counting modes
 * Modelled as a single pwm device for supporting different pwm modes.
 * Moved counter and pwm bindings to respective subsystems.

Biju Das (4):
  dt-bindings: mfd: Document RZ/G2L MTU3a bindings
  mfd: Add RZ/G2L MTU3 driver
  mfd: Add RZ/G2L MTU3 counter driver
  mfd: Add RZ/G2L MTU3 PWM driver

 .../bindings/mfd/renesas,rz-mtu3.yaml         | 305 ++++++++++
 drivers/mfd/Kconfig                           |  26 +
 drivers/mfd/Makefile                          |   5 +
 drivers/mfd/rz-mtu3-cnt.c                     | 554 ++++++++++++++++++
 drivers/mfd/rz-mtu3-core.c                    | 476 +++++++++++++++
 drivers/mfd/rz-mtu3-pwm.c                     | 405 +++++++++++++
 drivers/mfd/rz-mtu3.h                         | 221 +++++++
 7 files changed, 1992 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
 create mode 100644 drivers/mfd/rz-mtu3-cnt.c
 create mode 100644 drivers/mfd/rz-mtu3-core.c
 create mode 100644 drivers/mfd/rz-mtu3-pwm.c
 create mode 100644 drivers/mfd/rz-mtu3.h

-- 
2.25.1

[PATCH v4 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a bindings

[Biju Das]

The RZ/G2L multi-function timer pulse unit 3 (MTU3a) is embedded in
the Renesas RZ/G2L family SoC's. It consists of eight 16-bit timer
channels and one 32-bit timer channel. It supports the following
functions
 - Counter
 - Timer
 - PWM

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v3->v4:
 * Dropped counter and pwm compatibeles as they don't have any resources.
 * Made rz-mtu3 as pwm provider.
 * Updated the example and description.
v2->v3:
 * Dropped counter bindings and integrated with mfd as it has only one property.
 * Removed "#address-cells" and "#size-cells" as it do not have children with
   unit addresses.
 * Removed quotes from counter and pwm.
 * Provided full path for pwm bindings.
 * Updated the example.
v1->v2:
 * Modelled counter and pwm as a single device that handles
   multiple channels.
 * Moved counter and pwm bindings to respective subsystems
 * Dropped 'bindings' from MFD binding title.
 * Updated the example
 * Changed the compatible names.
---
 .../bindings/mfd/renesas,rz-mtu3.yaml         | 305 ++++++++++++++++++
 1 file changed, 305 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml

diff --git a/Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml b/Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
new file mode 100644
index 000000000000..1b0be9f5cd18
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
@@ -0,0 +1,305 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/renesas,rz-mtu3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L Multi-Function Timer Pulse Unit 3 (MTU3a)
+
+maintainers:
+  - Biju Das <biju.das.jz@bp.renesas.com>
+
+description: |
+  This hardware block pconsisting of eight 16-bit timer channels and one
+  32- bit timer channel. It supports the following specifications:
+    - Pulse input/output: 28 lines max.
+    - Pulse input 3 lines
+    - Count clock 11 clocks for each channel (14 clocks for MTU0, 12 clocks
+      for MTU2, and 10 clocks for MTU5, four clocks for MTU1-MTU2 combination
+      (when LWA = 1))
+    - Operating frequency Up to 100 MHz
+    - Available operations [MTU0 to MTU4, MTU6, MTU7, and MTU8]
+        - Waveform output on compare match
+        - Input capture function (noise filter setting available)
+        - Counter-clearing operation
+        - Simultaneous writing to multiple timer counters (TCNT)
+          (excluding MTU8).
+        - Simultaneous clearing on compare match or input capture
+          (excluding MTU8).
+        - Simultaneous input and output to registers in synchronization with
+          counter operations           (excluding MTU8).
+        - Up to 12-phase PWM output in combination with synchronous operation
+          (excluding MTU8)
+    - [MTU0 MTU3, MTU4, MTU6, MTU7, and MTU8]
+        - Buffer operation specifiable
+    - [MTU1, MTU2]
+        - Phase counting mode can be specified independently
+        - 32-bit phase counting mode can be specified for interlocked operation
+          of MTU1 and MTU2 (when TMDR3.LWA = 1)
+        - Cascade connection operation available
+    - [MTU3, MTU4, MTU6, and MTU7]
+        - Through interlocked operation of MTU3/4 and MTU6/7, the positive and
+          negative signals in six phases (12 phases in total) can be output in
+          complementary PWM and reset-synchronized PWM operation.
+        - In complementary PWM mode, values can be transferred from buffer
+          registers to temporary registers at crests and troughs of the timer-
+          counter values or when the buffer registers (TGRD registers in MTU4
+          and MTU7) are written to.
+        - Double-buffering selectable in complementary PWM mode.
+    - [MTU3 and MTU4]
+        - Through interlocking with MTU0, a mode for driving AC synchronous
+          motors (brushless DC motors) by using complementary PWM output and
+          reset-synchronized PWM output is settable and allows the selection
+          of two types of waveform output (chopping or level).
+    - [MTU5]
+        - Capable of operation as a dead-time compensation counter.
+    - [MTU0/MTU5, MTU1, MTU2, and MTU8]
+        - 32-bit phase counting mode specifiable by combining MTU1 and MTU2 and
+          through interlocked operation with MTU0/MTU5 and MTU8.
+    - Interrupt-skipping function
+        - In complementary PWM mode, interrupts on crests and troughs of counter
+          values and triggers to start conversion by the A/D converter can be
+          skipped.
+    - Interrupt sources: 43 sources.
+    - Buffer operation:
+        - Automatic transfer of register data (transfer from the buffer
+          register to the timer register).
+    - Trigger generation
+        - A/D converter start triggers can be generated
+        - A/D converter start request delaying function enables A/D converter
+          to be started with any desired timing and to be synchronized with
+          PWM output.
+    - Low power consumption function
+        - The MTU3a can be placed in the module-stop state.
+
+    There are two phase counting modes. 16-bit phase counting mode in which
+    MTU1 and MTU2 operate independently, and cascade connection 32-bit phase
+    counting mode in which MTU1 and MTU2 are cascaded.
+
+    In phase counting mode, the phase difference between two external input
+    clocks is detected and the corresponding TCNT is incremented or
+    decremented.
+    The below counters are supported
+      count0 - MTU1 16-bit phase counting
+      count1 - MTU2 16-bit phase counting
+      count2 - MTU1+ MTU2 32-bit phase counting
+
+    The module supports PWM mode{1,2}, Reset-synchronized PWM mode and
+    complementary PWM mode{1,2,3}.
+
+    In complementary PWM mode, six positive-phase and six negative-phase PWM
+    waveforms (12 phases in total) with dead time can be output by
+    combining MTU{3,4} and MTU{6,7}.
+
+    The below pwm channels are supported in pwm mode 1.
+      pwm0  - MTU0.MTIOC0A PWM mode 1
+      pwm1  - MTU0.MTIOC0C PWM mode 1
+      pwm2  - MTU1.MTIOC1A PWM mode 1
+      pwm3  - MTU2.MTIOC2A PWM mode 1
+      pwm4  - MTU3.MTIOC3A PWM mode 1
+      pwm5  - MTU3.MTIOC3C PWM mode 1
+      pwm6  - MTU4.MTIOC4A PWM mode 1
+      pwm7  - MTU4.MTIOC4C PWM mode 1
+      pwm8  - MTU6.MTIOC6A PWM mode 1
+      pwm9  - MTU6.MTIOC6C PWM mode 1
+      pwm10 - MTU7.MTIOC7A PWM mode 1
+      pwm11 - MTU7.MTIOC7C PWM mode 1
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - renesas,r9a07g044-mtu3  # RZ/G2{L,LC}
+          - renesas,r9a07g054-mtu3  # RZ/V2L
+      - const: renesas,rz-mtu3
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    items:
+      - description: MTU0.TGRA input capture/compare match
+      - description: MTU0.TGRB input capture/compare match
+      - description: MTU0.TGRC input capture/compare match
+      - description: MTU0.TGRD input capture/compare match
+      - description: MTU0.TCNT overflow
+      - description: MTU0.TGRE compare match
+      - description: MTU0.TGRF compare match
+      - description: MTU1.TGRA input capture/compare match
+      - description: MTU1.TGRB input capture/compare match
+      - description: MTU1.TCNT overflow
+      - description: MTU1.TCNT underflow
+      - description: MTU2.TGRA input capture/compare match
+      - description: MTU2.TGRB input capture/compare match
+      - description: MTU2.TCNT overflow
+      - description: MTU2.TCNT underflow
+      - description: MTU3.TGRA input capture/compare match
+      - description: MTU3.TGRB input capture/compare match
+      - description: MTU3.TGRC input capture/compare match
+      - description: MTU3.TGRD input capture/compare match
+      - description: MTU3.TCNT overflow
+      - description: MTU4.TGRA input capture/compare match
+      - description: MTU4.TGRB input capture/compare match
+      - description: MTU4.TGRC input capture/compare match
+      - description: MTU4.TGRD input capture/compare match
+      - description: MTU4.TCNT overflow/underflow
+      - description: MTU5.TGRU input capture/compare match
+      - description: MTU5.TGRV input capture/compare match
+      - description: MTU5.TGRW input capture/compare match
+      - description: MTU6.TGRA input capture/compare match
+      - description: MTU6.TGRB input capture/compare match
+      - description: MTU6.TGRC input capture/compare match
+      - description: MTU6.TGRD input capture/compare match
+      - description: MTU6.TCNT overflow
+      - description: MTU7.TGRA input capture/compare match
+      - description: MTU7.TGRB input capture/compare match
+      - description: MTU7.TGRC input capture/compare match
+      - description: MTU7.TGRD input capture/compare match
+      - description: MTU7.TCNT overflow/underflow
+      - description: MTU8.TGRA input capture/compare match
+      - description: MTU8.TGRB input capture/compare match
+      - description: MTU8.TGRC input capture/compare match
+      - description: MTU8.TGRD input capture/compare match
+      - description: MTU8.TCNT overflow
+      - description: MTU8.TCNT underflow
+
+  interrupt-names:
+    items:
+      - const: tgia0
+      - const: tgib0
+      - const: tgic0
+      - const: tgid0
+      - const: tgiv0
+      - const: tgie0
+      - const: tgif0
+      - const: tgia1
+      - const: tgib1
+      - const: tgiv1
+      - const: tgiu1
+      - const: tgia2
+      - const: tgib2
+      - const: tgiv2
+      - const: tgiu2
+      - const: tgia3
+      - const: tgib3
+      - const: tgic3
+      - const: tgid3
+      - const: tgiv3
+      - const: tgia4
+      - const: tgib4
+      - const: tgic4
+      - const: tgid4
+      - const: tgiv4
+      - const: tgiu5
+      - const: tgiv5
+      - const: tgiw5
+      - const: tgia6
+      - const: tgib6
+      - const: tgic6
+      - const: tgid6
+      - const: tgiv6
+      - const: tgia7
+      - const: tgib7
+      - const: tgic7
+      - const: tgid7
+      - const: tgiv7
+      - const: tgia8
+      - const: tgib8
+      - const: tgic8
+      - const: tgid8
+      - const: tgiv8
+      - const: tgiu8
+
+  clocks:
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  "#pwm-cells":
+    const: 2
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-names
+  - clocks
+  - power-domains
+  - resets
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/r9a07g044-cpg.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    mtu3: timer@10001200 {
+      compatible = "renesas,r9a07g044-mtu3",
+                   "renesas,rz-mtu3";
+      reg = <0x10001200 0xb00>;
+      interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 173 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 181 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 185 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 186 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 192 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 201 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 202 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 207 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
+      interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", "tgiv0", "tgie0",
+                        "tgif0",
+                        "tgia1", "tgib1", "tgiv1", "tgiu1",
+                        "tgia2", "tgib2", "tgiv2", "tgiu2",
+                        "tgia3", "tgib3", "tgic3", "tgid3", "tgiv3",
+                        "tgia4", "tgib4", "tgic4", "tgid4", "tgiv4",
+                        "tgiu5", "tgiv5", "tgiw5",
+                        "tgia6", "tgib6", "tgic6", "tgid6", "tgiv6",
+                        "tgia7", "tgib7", "tgic7", "tgid7", "tgiv7",
+                        "tgia8", "tgib8", "tgic8", "tgid8", "tgiv8", "tgiu8";
+      clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
+      power-domains = <&cpg>;
+      resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
+      #pwm-cells = <2>;
+    };
+
+...
-- 
2.25.1

[PATCH v4 4/4] mfd: Add RZ/G2L MTU3 PWM driver

[Biju Das]

Add support for RZ/G2L MTU3 PWM driver. The IP supports
following PWM modes

1) PWM mode{1,2}
2) Reset-synchronized PWM mode
3) Complementary PWM mode{1,2,3}

This patch adds basic pwm mode 1 support for RZ/G2L MTU3 driver
by creating separate logical channels for each IOs.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v3->v4:
 * There is no resource associated with "rz-mtu3-pwm" compatible
   and moved the code to mfd subsystem as it binds against "rz-mtu".
 * Removed struct platform_driver rz_mtu3_pwm_driver.
v2->v3:
 * No change.
v1->v2:
 * Modelled as a single PWM device handling multiple channles.
 * Used PM framework to manage the clocks.
---
 drivers/mfd/Kconfig       |   6 +
 drivers/mfd/Makefile      |   2 +
 drivers/mfd/rz-mtu3-pwm.c | 405 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 413 insertions(+)
 create mode 100644 drivers/mfd/rz-mtu3-pwm.c

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index fa88056224c9..1a0208236adc 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -1994,6 +1994,12 @@ config MFD_RZ_MTU3_CNT
 	  SoCs. This IP supports both 16-bit and 32-bit phase counting mode
 	  support.
 
+config MFD_RZ_MTU3_PWM
+	tristate "Renesas RZ/G2L MTU3 PWM Timer support"
+	depends on MFD_RZ_MTU3
+	help
+	  Enable support for RZ/G2L MTU3 PWM Timer controller.
+
 config MFD_STM32_LPTIMER
 	tristate "Support for STM32 Low-Power Timer"
 	depends on (ARCH_STM32 && OF) || COMPILE_TEST
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 9d0d1fd22f99..50c7467f7c79 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -253,7 +253,9 @@ obj-$(CONFIG_MFD_SUN4I_GPADC)	+= sun4i-gpadc.o
 
 rz-mtu3-objs			:= rz-mtu3-core.o
 rz-mtu3-$(CONFIG_MFD_RZ_MTU3_CNT)	+= rz-mtu3-cnt.o
+rz-mtu3-$(CONFIG_MFD_RZ_MTU3_PWM)	+= rz-mtu3-pwm.o
 obj-$(CONFIG_MFD_RZ_MTU3) 	+= rz-mtu3.o
+
 obj-$(CONFIG_MFD_STM32_LPTIMER)	+= stm32-lptimer.o
 obj-$(CONFIG_MFD_STM32_TIMERS) 	+= stm32-timers.o
 obj-$(CONFIG_MFD_MXS_LRADC)     += mxs-lradc.o
diff --git a/drivers/mfd/rz-mtu3-pwm.c b/drivers/mfd/rz-mtu3-pwm.c
new file mode 100644
index 000000000000..8aa67577e022
--- /dev/null
+++ b/drivers/mfd/rz-mtu3-pwm.c
@@ -0,0 +1,405 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/G2L MTU3 PWM Timer driver
+ *
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ *
+ * Hardware manual for this IP can be found here
+ * https://www.renesas.com/eu/en/document/mah/rzg2l-group-rzg2lc-group-users-manual-hardware-0?language=en
+ *
+ * Limitations:
+ * - When PWM is disabled, the output is driven to Hi-Z.
+ * - While the hardware supports both polarities, the driver (for now)
+ *   only handles normal polarity.
+ * - While the hardware supports pwm mode{1,2}, reset-synchronized pwm and
+ *   complementary pwm modes, the driver (for now) only handles pwm mode1.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/limits.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/pwm.h>
+#include <linux/time.h>
+
+#include "rz-mtu3.h"
+
+#define RZ_MTU3_TMDR1_MD_NORMAL		(0)
+#define RZ_MTU3_TMDR1_MD_PWM_MODE_1	(2)
+
+#define RZ_MTU3_TIOR_OC_RETAIN		(0)
+#define RZ_MTU3_TIOR_OC_0_H_COMP_MATCH	(2)
+#define RZ_MTU3_TIOR_OC_1_TOGGLE	(7)
+#define RZ_MTU3_TIOR_OC_IOA		GENMASK(3, 0)
+
+#define RZ_MTU3_TCR_CCLR_TGRC		(5 << 5)
+#define RZ_MTU3_TCR_CKEG_RISING		(0 << 3)
+
+#define RZ_MTU3_TCR_TPCS		GENMASK(2, 0)
+
+#define RZ_MTU3_MAX_PWM_MODE1_CHANNELS	(12)
+
+#define RZ_MTU3_MAX_HW_PWM_CHANNELS	(7)
+
+static const u8 rz_mtu3_pwm_mode1_num_ios[] = { 2, 1, 1, 2, 2, 2, 2 };
+
+/**
+ * struct rz_mtu3_pwm_chip - MTU3 pwm private data
+ *
+ * @chip: MTU3 pwm chip data
+ * @lock: Lock to prevent concurrent access for usage count
+ * @rate: MTU3 clock rate
+ * @user_count: MTU3 usage count
+ * @rz_mtu3_channel: HW channels for the PWM
+ */
+
+struct rz_mtu3_pwm_chip {
+	struct pwm_chip chip;
+	struct mutex lock;
+	unsigned long rate;
+	u32 user_count[RZ_MTU3_MAX_HW_PWM_CHANNELS];
+	struct rz_mtu3_channel *ch[RZ_MTU3_MAX_HW_PWM_CHANNELS];
+};
+
+static inline struct rz_mtu3_pwm_chip *to_rz_mtu3_pwm_chip(struct pwm_chip *chip)
+{
+	return container_of(chip, struct rz_mtu3_pwm_chip, chip);
+}
+
+static u8 rz_mtu3_pwm_calculate_prescale(struct rz_mtu3_pwm_chip *rz_mtu3,
+					 u64 period_cycles)
+{
+	u32 prescaled_period_cycles;
+	u8 prescale;
+
+	prescaled_period_cycles = period_cycles >> 16;
+	if (prescaled_period_cycles >= 16)
+		prescale = 3;
+	else
+		prescale = (fls(prescaled_period_cycles) + 1) / 2;
+
+	return prescale;
+}
+
+static struct rz_mtu3_channel *
+rz_mtu3_get_hw_channel(struct rz_mtu3_pwm_chip *rz_mtu3_pwm, u32 channel)
+{
+	unsigned int i, ch_index = 0;
+
+	for (i = 0; i < ARRAY_SIZE(rz_mtu3_pwm_mode1_num_ios); i++) {
+		ch_index += rz_mtu3_pwm_mode1_num_ios[i];
+
+		if (ch_index > channel)
+			break;
+	}
+
+	return rz_mtu3_pwm->ch[i];
+}
+
+static u32 rz_mtu3_get_hw_channel_index(struct rz_mtu3_pwm_chip *rz_mtu3_pwm,
+					struct rz_mtu3_channel *ch)
+{
+	u32 i;
+
+	for (i = 0; i < ARRAY_SIZE(rz_mtu3_pwm_mode1_num_ios); i++) {
+		if (ch == rz_mtu3_pwm->ch[i])
+			break;
+	}
+
+	return i;
+}
+
+static bool rz_mtu3_pwm_is_second_channel(u32 ch_index, u32 hwpwm)
+{
+	u32 i, pwm_ch_index = 0;
+
+	for (i = 0; i < ch_index; i++)
+		pwm_ch_index += rz_mtu3_pwm_mode1_num_ios[i];
+
+	return pwm_ch_index != hwpwm;
+}
+
+static bool rz_mtu3_pwm_is_ch_enabled(struct rz_mtu3_pwm_chip *rz_mtu3_pwm,
+				      u32 hwpwm)
+{
+	struct rz_mtu3_channel *ch;
+	bool is_channel_en;
+	u32 ch_index;
+	u8 val;
+
+	ch = rz_mtu3_get_hw_channel(rz_mtu3_pwm, hwpwm);
+	ch_index = rz_mtu3_get_hw_channel_index(rz_mtu3_pwm, ch);
+	is_channel_en = rz_mtu3_is_enabled(ch);
+
+	if (rz_mtu3_pwm_is_second_channel(ch_index, hwpwm))
+		val = rz_mtu3_8bit_ch_read(ch, RZ_MTU3_TIORL);
+	else
+		val = rz_mtu3_8bit_ch_read(ch, RZ_MTU3_TIORH);
+
+	return (is_channel_en && (val & RZ_MTU3_TIOR_OC_IOA));
+}
+
+static int rz_mtu3_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+	struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip);
+	struct rz_mtu3_channel *ch;
+	u32 ch_index;
+
+	ch = rz_mtu3_get_hw_channel(rz_mtu3_pwm, pwm->hwpwm);
+	ch_index = rz_mtu3_get_hw_channel_index(rz_mtu3_pwm, ch);
+
+	mutex_lock(&rz_mtu3_pwm->lock);
+	rz_mtu3_pwm->user_count[ch_index]++;
+	mutex_unlock(&rz_mtu3_pwm->lock);
+
+	ch->function = RZ_MTU3_PWM_MODE_1;
+
+	return 0;
+}
+
+static void rz_mtu3_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+	struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip);
+	struct rz_mtu3_channel *ch;
+	u32 ch_index;
+
+	ch = rz_mtu3_get_hw_channel(rz_mtu3_pwm, pwm->hwpwm);
+	ch_index = rz_mtu3_get_hw_channel_index(rz_mtu3_pwm, ch);
+
+	mutex_lock(&rz_mtu3_pwm->lock);
+	rz_mtu3_pwm->user_count[ch_index]--;
+	mutex_unlock(&rz_mtu3_pwm->lock);
+
+	if (!rz_mtu3_pwm->user_count[ch_index])
+		ch->function = RZ_MTU3_NORMAL;
+}
+
+static int rz_mtu3_pwm_enable(struct rz_mtu3_pwm_chip *rz_mtu3_pwm,
+			      struct pwm_device *pwm)
+{
+	struct rz_mtu3_channel *ch;
+	u32 ch_index;
+	u8 val;
+
+	ch = rz_mtu3_get_hw_channel(rz_mtu3_pwm, pwm->hwpwm);
+	ch_index = rz_mtu3_get_hw_channel_index(rz_mtu3_pwm, ch);
+	val = (RZ_MTU3_TIOR_OC_1_TOGGLE << 4) | RZ_MTU3_TIOR_OC_0_H_COMP_MATCH;
+
+	rz_mtu3_8bit_ch_write(ch, RZ_MTU3_TMDR1, RZ_MTU3_TMDR1_MD_PWM_MODE_1);
+	if (rz_mtu3_pwm_is_second_channel(ch_index, pwm->hwpwm))
+		rz_mtu3_8bit_ch_write(ch, RZ_MTU3_TIORL, val);
+	else
+		rz_mtu3_8bit_ch_write(ch, RZ_MTU3_TIORH, val);
+
+	if (rz_mtu3_pwm->user_count[ch_index] <= 1)
+		rz_mtu3_enable(ch);
+
+	return 0;
+}
+
+static void rz_mtu3_pwm_disable(struct rz_mtu3_pwm_chip *rz_mtu3_pwm,
+				struct pwm_device *pwm)
+{
+	struct rz_mtu3_channel *ch;
+	u32 ch_index;
+
+	ch = rz_mtu3_get_hw_channel(rz_mtu3_pwm, pwm->hwpwm);
+	ch_index = rz_mtu3_get_hw_channel_index(rz_mtu3_pwm, ch);
+
+	/* Return to normal mode and disable output pins of MTU3 channel */
+	if (rz_mtu3_pwm->user_count[ch_index] <= 1)
+		rz_mtu3_8bit_ch_write(ch, RZ_MTU3_TMDR1, RZ_MTU3_TMDR1_MD_NORMAL);
+
+	if (rz_mtu3_pwm_is_second_channel(ch_index, pwm->hwpwm))
+		rz_mtu3_8bit_ch_write(ch, RZ_MTU3_TIORL, RZ_MTU3_TIOR_OC_RETAIN);
+	else
+		rz_mtu3_8bit_ch_write(ch, RZ_MTU3_TIORH, RZ_MTU3_TIOR_OC_RETAIN);
+
+	if (rz_mtu3_pwm->user_count[ch_index] <= 1)
+		rz_mtu3_disable(ch);
+}
+
+static int rz_mtu3_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
+			      const struct pwm_state *state)
+{
+	struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip);
+	struct rz_mtu3_channel *ch;
+	unsigned long pv, dc;
+	u64 period_cycles;
+	u64 duty_cycles;
+	u32 ch_index;
+	u8 prescale;
+	u8 val;
+
+	/*
+	 * Refuse clk rates > 1 GHz to prevent overflowing the following
+	 * calculation.
+	 */
+	if (rz_mtu3_pwm->rate > NSEC_PER_SEC)
+		return -EINVAL;
+
+	ch = rz_mtu3_get_hw_channel(rz_mtu3_pwm, pwm->hwpwm);
+	ch_index = rz_mtu3_get_hw_channel_index(rz_mtu3_pwm, ch);
+	duty_cycles = state->duty_cycle;
+	if (!state->enabled)
+		duty_cycles = 0;
+
+	period_cycles = mul_u64_u32_div(state->period, rz_mtu3_pwm->rate,
+					NSEC_PER_SEC);
+	prescale = rz_mtu3_pwm_calculate_prescale(rz_mtu3_pwm, period_cycles);
+
+	if (period_cycles >> (2 * prescale) <= U16_MAX)
+		pv = period_cycles >> (2 * prescale);
+	else
+		pv = U16_MAX;
+
+	duty_cycles = mul_u64_u32_div(duty_cycles, rz_mtu3_pwm->rate,
+				      NSEC_PER_SEC);
+	if (duty_cycles >> (2 * prescale) <= U16_MAX)
+		dc = duty_cycles >> (2 * prescale);
+	else
+		dc = U16_MAX;
+
+	val = RZ_MTU3_TCR_CKEG_RISING | prescale;
+	if (rz_mtu3_pwm_is_second_channel(ch_index, pwm->hwpwm)) {
+		rz_mtu3_8bit_ch_write(ch, RZ_MTU3_TCR,
+				      RZ_MTU3_TCR_CCLR_TGRC | val);
+		rz_mtu3_16bit_ch_write(ch, RZ_MTU3_TGRD, dc);
+		rz_mtu3_16bit_ch_write(ch, RZ_MTU3_TGRC, pv);
+	} else {
+		rz_mtu3_8bit_ch_write(ch, RZ_MTU3_TCR,
+				      RZ_MTU3_TCR_CCLR_TGRA | val);
+		rz_mtu3_16bit_ch_write(ch, RZ_MTU3_TGRB, dc);
+		rz_mtu3_16bit_ch_write(ch, RZ_MTU3_TGRA, pv);
+	}
+
+	return 0;
+}
+
+static void rz_mtu3_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+				  struct pwm_state *state)
+{
+	struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip);
+	struct rz_mtu3_channel *ch;
+	u8 prescale, val;
+	u32 ch_index;
+	u16 dc, pv;
+	u64 tmp;
+
+	ch = rz_mtu3_get_hw_channel(rz_mtu3_pwm, pwm->hwpwm);
+	ch_index = rz_mtu3_get_hw_channel_index(rz_mtu3_pwm, ch);
+	pm_runtime_get_sync(chip->dev);
+	state->enabled = rz_mtu3_pwm_is_ch_enabled(rz_mtu3_pwm, pwm->hwpwm);
+	if (state->enabled) {
+		val = rz_mtu3_8bit_ch_read(ch, RZ_MTU3_TCR);
+		prescale = FIELD_GET(RZ_MTU3_TCR_TPCS, val);
+
+		if (rz_mtu3_pwm_is_second_channel(ch_index, pwm->hwpwm)) {
+			dc = rz_mtu3_16bit_ch_read(ch, RZ_MTU3_TGRD);
+			pv = rz_mtu3_16bit_ch_read(ch, RZ_MTU3_TGRC);
+		} else {
+			dc = rz_mtu3_16bit_ch_read(ch, RZ_MTU3_TGRB);
+			pv = rz_mtu3_16bit_ch_read(ch, RZ_MTU3_TGRA);
+		}
+
+		tmp = NSEC_PER_SEC * (u64)pv << (2 * prescale);
+		state->period = DIV_ROUND_UP_ULL(tmp, rz_mtu3_pwm->rate);
+
+		tmp = NSEC_PER_SEC * (u64)dc << (2 * prescale);
+		state->duty_cycle = DIV_ROUND_UP_ULL(tmp, rz_mtu3_pwm->rate);
+	}
+
+	state->polarity = PWM_POLARITY_NORMAL;
+	pm_runtime_put(chip->dev);
+}
+
+static int rz_mtu3_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+			     const struct pwm_state *state)
+{
+	struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip);
+	struct pwm_state cur_state;
+	bool enabled;
+	int ret;
+
+	cur_state = pwm->state;
+	enabled = cur_state.enabled;
+	if (state->polarity != PWM_POLARITY_NORMAL)
+		return -EINVAL;
+
+	if (!enabled && state->enabled)
+		pm_runtime_get_sync(chip->dev);
+
+	ret = rz_mtu3_pwm_config(chip, pwm, state);
+	if (ret && state->enabled)
+		goto done;
+
+	if (!state->enabled) {
+		if (enabled)
+			rz_mtu3_pwm_disable(rz_mtu3_pwm, pwm);
+		ret = 0;
+		goto done;
+	}
+
+	return rz_mtu3_pwm_enable(rz_mtu3_pwm, pwm);
+done:
+	if (enabled && !state->enabled)
+		pm_runtime_put(chip->dev);
+
+	return ret;
+}
+
+static const struct pwm_ops rz_mtu3_pwm_ops = {
+	.request = rz_mtu3_pwm_request,
+	.free = rz_mtu3_pwm_free,
+	.get_state = rz_mtu3_pwm_get_state,
+	.apply = rz_mtu3_pwm_apply,
+	.owner = THIS_MODULE,
+};
+
+int rz_mtu3_pwm_probe(struct platform_device *pdev)
+{
+	struct rz_mtu3 *ddata = dev_get_drvdata(&pdev->dev);
+	struct rz_mtu3_pwm_chip *rz_mtu3_pwm;
+	struct device *dev = &pdev->dev;
+	int num_pwm_hw_ch;
+	unsigned int i;
+	int ret;
+
+	rz_mtu3_pwm = devm_kzalloc(&pdev->dev, sizeof(*rz_mtu3_pwm), GFP_KERNEL);
+	if (!rz_mtu3_pwm)
+		return -ENOMEM;
+
+	ddata->pwm_priv = rz_mtu3_pwm;
+	num_pwm_hw_ch = 0;
+	for (i = 0; i < RZ_MTU_NUM_CHANNELS; i++) {
+		if (i == RZ_MTU5 || i == RZ_MTU8)
+			continue;
+
+		rz_mtu3_pwm->ch[num_pwm_hw_ch] = &ddata->channels[i];
+		rz_mtu3_pwm->ch[num_pwm_hw_ch]->dev = dev;
+		num_pwm_hw_ch++;
+	}
+
+	rz_mtu3_pwm->rate = clk_get_rate(ddata->clk);
+
+	mutex_init(&rz_mtu3_pwm->lock);
+
+	rz_mtu3_pwm->chip.dev = &pdev->dev;
+	rz_mtu3_pwm->chip.ops = &rz_mtu3_pwm_ops;
+	rz_mtu3_pwm->chip.npwm = RZ_MTU3_MAX_PWM_MODE1_CHANNELS;
+
+	ret = devm_pwmchip_add(&pdev->dev, &rz_mtu3_pwm->chip);
+	if (ret)
+		dev_err_probe(&pdev->dev, ret, "failed to add PWM chip\n");
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(rz_mtu3_pwm_probe);
+
+MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
+MODULE_DESCRIPTION("Renesas RZ/G2L MTU3 PWM Timer Driver");
+MODULE_LICENSE("GPL");
-- 
2.25.1

Re: [PATCH v4 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a bindings

[Krzysztof Kozlowski]

On 10/10/2022 10:52, Biju Das wrote:
> The RZ/G2L multi-function timer pulse unit 3 (MTU3a) is embedded in
> the Renesas RZ/G2L family SoC's. It consists of eight 16-bit timer
> channels and one 32-bit timer channel. It supports the following
> functions
>  - Counter
>  - Timer
>  - PWM
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v3->v4:
>  * Dropped counter and pwm compatibeles as they don't have any resources.
>  * Made rz-mtu3 as pwm provider.
>  * Updated the example and description.
> v2->v3:
>  * Dropped counter bindings and integrated with mfd as it has only one property.
>  * Removed "#address-cells" and "#size-cells" as it do not have children with
>    unit addresses.
>  * Removed quotes from counter and pwm.
>  * Provided full path for pwm bindings.
>  * Updated the example.
> v1->v2:
>  * Modelled counter and pwm as a single device that handles
>    multiple channels.
>  * Moved counter and pwm bindings to respective subsystems
>  * Dropped 'bindings' from MFD binding title.
>  * Updated the example
>  * Changed the compatible names.
> ---
>  .../bindings/mfd/renesas,rz-mtu3.yaml         | 305 ++++++++++++++++++
>  1 file changed, 305 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml

This should not be in MFD. Just because some device has few features,
does not mean it should go to MFD... Choose either timer or pwm.


> 
> diff --git a/Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml b/Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
> new file mode 100644
> index 000000000000..1b0be9f5cd18
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
> @@ -0,0 +1,305 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mfd/renesas,rz-mtu3.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/G2L Multi-Function Timer Pulse Unit 3 (MTU3a)
> +
> +maintainers:
> +  - Biju Das <biju.das.jz@bp.renesas.com>
> +
> +description: |
> +  This hardware block pconsisting of eight 16-bit timer channels and one

"This hardware block consists of..."

> +  32- bit timer channel. It supports the following specifications:
> +    - Pulse input/output: 28 lines max.
> +    - Pulse input 3 lines
> +    - Count clock 11 clocks for each channel (14 clocks for MTU0, 12 clocks
> +      for MTU2, and 10 clocks for MTU5, four clocks for MTU1-MTU2 combination
> +      (when LWA = 1))
> +    - Operating frequency Up to 100 MHz

Best regards,
Krzysztof

RE: [PATCH v4 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a bindings

[Biju Das]

Hi Krzysztof Kozlowski,

> Subject: Re: [PATCH v4 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a
> bindings
> 
> On 10/10/2022 10:52, Biju Das wrote:
> > The RZ/G2L multi-function timer pulse unit 3 (MTU3a) is embedded in
> > the Renesas RZ/G2L family SoC's. It consists of eight 16-bit timer
> > channels and one 32-bit timer channel. It supports the following
> > functions
> >  - Counter
> >  - Timer
> >  - PWM
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v3->v4:
> >  * Dropped counter and pwm compatibeles as they don't have any
> resources.
> >  * Made rz-mtu3 as pwm provider.
> >  * Updated the example and description.
> > v2->v3:
> >  * Dropped counter bindings and integrated with mfd as it has only
> one property.
> >  * Removed "#address-cells" and "#size-cells" as it do not have
> children with
> >    unit addresses.
> >  * Removed quotes from counter and pwm.
> >  * Provided full path for pwm bindings.
> >  * Updated the example.
> > v1->v2:
> >  * Modelled counter and pwm as a single device that handles
> >    multiple channels.
> >  * Moved counter and pwm bindings to respective subsystems
> >  * Dropped 'bindings' from MFD binding title.
> >  * Updated the example
> >  * Changed the compatible names.
> > ---
> >  .../bindings/mfd/renesas,rz-mtu3.yaml         | 305
> ++++++++++++++++++
> >  1 file changed, 305 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
> 
> This should not be in MFD. Just because some device has few features,
> does not mean it should go to MFD... Choose either timer or pwm.

MFD is for multifunction device. This IP supports multiple functions
like timer, pwm, clock source/events. That is the reason I have added 
here. MFD is core which provides register access for client devices.

For me moving it to pwm or counter is not a big problem.
Why do you think it cannot be MFD?

Cheers,
Biju

> 
> 
> >
> > diff --git
> > a/Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
> > b/Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
> > new file mode 100644
> > index 000000000000..1b0be9f5cd18
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
> > @@ -0,0 +1,305 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> >
> > +title: Renesas RZ/G2L Multi-Function Timer Pulse Unit 3 (MTU3a)
> > +
> > +maintainers:
> > +  - Biju Das <biju.das.jz@bp.renesas.com>
> > +
> > +description: |
> > +  This hardware block pconsisting of eight 16-bit timer channels
> and
> > +one
> 
> "This hardware block consists of..."

OK, will fix this in next version.

Cheers,
Biju

Re: [PATCH v4 4/4] mfd: Add RZ/G2L MTU3 PWM driver

[Krzysztof Kozlowski]

On 10/10/2022 10:52, Biju Das wrote:
> Add support for RZ/G2L MTU3 PWM driver. The IP supports
> following PWM modes
> 
> 1) PWM mode{1,2}
> 2) Reset-synchronized PWM mode
> 3) Complementary PWM mode{1,2,3}
> 
> This patch adds basic pwm mode 1 support for RZ/G2L MTU3 driver
> by creating separate logical channels for each IOs.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v3->v4:
>  * There is no resource associated with "rz-mtu3-pwm" compatible
>    and moved the code to mfd subsystem as it binds against "rz-mtu".
>  * Removed struct platform_driver rz_mtu3_pwm_driver.
> v2->v3:
>  * No change.
> v1->v2:
>  * Modelled as a single PWM device handling multiple channles.
>  * Used PM framework to manage the clocks.
> ---
>  drivers/mfd/Kconfig       |   6 +
>  drivers/mfd/Makefile      |   2 +
>  drivers/mfd/rz-mtu3-pwm.c | 405 ++++++++++++++++++++++++++++++++++++++

That's not a MFD driver. That's a PWM. Use proper subsystem and email
prefix.

The same applies to your other patches.

Best regards,
Krzysztof

Re: [PATCH v4 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a bindings

[Krzysztof Kozlowski]

On 11/10/2022 10:55, Biju Das wrote:
> 
>>>  .../bindings/mfd/renesas,rz-mtu3.yaml         | 305
>> ++++++++++++++++++
>>>  1 file changed, 305 insertions(+)
>>>  create mode 100644
>>> Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
>>
>> This should not be in MFD. Just because some device has few features,
>> does not mean it should go to MFD... Choose either timer or pwm.
> 
> MFD is for multifunction device. This IP supports multiple functions
> like timer, pwm, clock source/events. That is the reason I have added 
> here. MFD is core which provides register access for client devices.
> 
> For me moving it to pwm or counter is not a big problem.
> Why do you think it cannot be MFD?


Because it makes MFD a dump for everything where author did not want to
think about real device aspects, but instead represented driver design
(MFD driver).

MFDs are pretty often combining unrelated features, e.g. PMICs which
have wakeup and system power control, regulator, 32 kHz clocks, RTC and
some USB connector.

Just because you will have clocksource driver, PWM driver and timer
driver does not make it a MFD.

Best regards,
Krzysztof

RE: [PATCH v4 4/4] mfd: Add RZ/G2L MTU3 PWM driver

[Biju Das]

> Subject: Re: [PATCH v4 4/4] mfd: Add RZ/G2L MTU3 PWM driver
> 
> On 10/10/2022 10:52, Biju Das wrote:
> > Add support for RZ/G2L MTU3 PWM driver. The IP supports following
> PWM
> > modes
> >
> > 1) PWM mode{1,2}
> > 2) Reset-synchronized PWM mode
> > 3) Complementary PWM mode{1,2,3}
> >
> > This patch adds basic pwm mode 1 support for RZ/G2L MTU3 driver by
> > creating separate logical channels for each IOs.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v3->v4:
> >  * There is no resource associated with "rz-mtu3-pwm" compatible
> >    and moved the code to mfd subsystem as it binds against "rz-mtu".
> >  * Removed struct platform_driver rz_mtu3_pwm_driver.
> > v2->v3:
> >  * No change.
> > v1->v2:
> >  * Modelled as a single PWM device handling multiple channles.
> >  * Used PM framework to manage the clocks.
> > ---
> >  drivers/mfd/Kconfig       |   6 +
> >  drivers/mfd/Makefile      |   2 +
> >  drivers/mfd/rz-mtu3-pwm.c | 405
> > ++++++++++++++++++++++++++++++++++++++
> 
> That's not a MFD driver. That's a PWM. Use proper subsystem and email
> prefix.

See [1]
[1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20221006135717.1748560-2-biju.das.jz@bp.renesas.com/

It is a single driver that binds against "renesas,rz-mtu3", and registers both the counter and the pwm
functionalities. Just like the clock driver, which registers clock, reset, and PM Domain functionalities.

It is same here, a single MFD driver which binds against ""renesas,rz-mtu3" and registers counter 
And pwm functionalities.

rz-mtu-core is core driver which provides resources to child devices like counter and pwm.

I already copied PWM subsystem in the loop. Am I missing anything related to [1]

Cheers,
Biju

 

RE: [PATCH v4 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a bindings

[Biju Das]

> Subject: Re: [PATCH v4 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a
> bindings
> 
> On 11/10/2022 10:55, Biju Das wrote:
> >
> >>>  .../bindings/mfd/renesas,rz-mtu3.yaml         | 305
> >> ++++++++++++++++++
> >>>  1 file changed, 305 insertions(+)
> >>>  create mode 100644
> >>> Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
> >>
> >> This should not be in MFD. Just because some device has few
> features,
> >> does not mean it should go to MFD... Choose either timer or pwm.
> >
> > MFD is for multifunction device. This IP supports multiple functions
> > like timer, pwm, clock source/events. That is the reason I have
> added
> > here. MFD is core which provides register access for client devices.
> >
> > For me moving it to pwm or counter is not a big problem.
> > Why do you think it cannot be MFD?
> 
> 
> Because it makes MFD a dump for everything where author did not want
> to think about real device aspects, but instead represented driver
> design (MFD driver).

Core driver is MFD, just provides resources to child devices
and is not aware of any real device aspects.

> 
> MFDs are pretty often combining unrelated features, e.g. PMICs which
> have wakeup and system power control, regulator, 32 kHz clocks, RTC
> and some USB connector.

Here also same right? pwm, counter and clock are 3 unrelated features.
That is the reason we have separate subsystems for these features.

> 
> Just because you will have clocksource driver, PWM driver and timer
> driver does not make it a MFD.

MFD is multi function device. So are are you agreeing Clock source, PWM and
timer are different functionalities or not? If not, why do we have 3 subsystems,
if it is same?

Where do keep these bindings as there is only single "rz_mtu" bindings for these 3 different functionalities?

pwm or counter or mfd?

Please let me know.

Cheers,
Biju

Re: [PATCH v4 4/4] mfd: Add RZ/G2L MTU3 PWM driver

[Krzysztof Kozlowski]

On 11/10/2022 15:13, Biju Das wrote:
>> Subject: Re: [PATCH v4 4/4] mfd: Add RZ/G2L MTU3 PWM driver
>>
>> On 10/10/2022 10:52, Biju Das wrote:
>>> Add support for RZ/G2L MTU3 PWM driver. The IP supports following
>> PWM
>>> modes
>>>
>>> 1) PWM mode{1,2}
>>> 2) Reset-synchronized PWM mode
>>> 3) Complementary PWM mode{1,2,3}
>>>
>>> This patch adds basic pwm mode 1 support for RZ/G2L MTU3 driver by
>>> creating separate logical channels for each IOs.
>>>
>>> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
>>> ---
>>> v3->v4:
>>>  * There is no resource associated with "rz-mtu3-pwm" compatible
>>>    and moved the code to mfd subsystem as it binds against "rz-mtu".
>>>  * Removed struct platform_driver rz_mtu3_pwm_driver.
>>> v2->v3:
>>>  * No change.
>>> v1->v2:
>>>  * Modelled as a single PWM device handling multiple channles.
>>>  * Used PM framework to manage the clocks.
>>> ---
>>>  drivers/mfd/Kconfig       |   6 +
>>>  drivers/mfd/Makefile      |   2 +
>>>  drivers/mfd/rz-mtu3-pwm.c | 405
>>> ++++++++++++++++++++++++++++++++++++++
>>
>> That's not a MFD driver. That's a PWM. Use proper subsystem and email
>> prefix.
> 
> See [1]
> [1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20221006135717.1748560-2-biju.das.jz@bp.renesas.com/
> 
> It is a single driver that binds against "renesas,rz-mtu3", and registers both the counter and the pwm
> functionalities. Just like the clock driver, which registers clock, reset, and PM Domain functionalities.

No, it is not a single driver. You just added a new file - PWM.

> 
> It is same here, a single MFD driver which binds against ""renesas,rz-mtu3" and registers counter 
> And pwm functionalities.
> 
> rz-mtu-core is core driver which provides resources to child devices like counter and pwm.
> 
> I already copied PWM subsystem in the loop. Am I missing anything related to [1]

MFD subsystem is only a wrapper/parent over actual drivers. It's not
meant to hold the subsystem-specific code, because relevant maintainers
will not look here.

So no, here and in other files - don't put subsystem specific code like
PWM or timer into MFD.

Best regards,
Krzysztof

Re: [PATCH v4 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a bindings

[Krzysztof Kozlowski]

On 11/10/2022 15:23, Biju Das wrote:
>> Subject: Re: [PATCH v4 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a
>> bindings
>>
>> On 11/10/2022 10:55, Biju Das wrote:
>>>
>>>>>  .../bindings/mfd/renesas,rz-mtu3.yaml         | 305
>>>> ++++++++++++++++++
>>>>>  1 file changed, 305 insertions(+)
>>>>>  create mode 100644
>>>>> Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
>>>>
>>>> This should not be in MFD. Just because some device has few
>> features,
>>>> does not mean it should go to MFD... Choose either timer or pwm.
>>>
>>> MFD is for multifunction device. This IP supports multiple functions
>>> like timer, pwm, clock source/events. That is the reason I have
>> added
>>> here. MFD is core which provides register access for client devices.
>>>
>>> For me moving it to pwm or counter is not a big problem.
>>> Why do you think it cannot be MFD?
>>
>>
>> Because it makes MFD a dump for everything where author did not want
>> to think about real device aspects, but instead represented driver
>> design (MFD driver).
> 
> Core driver is MFD, just provides resources to child devices
> and is not aware of any real device aspects.
> 
>>
>> MFDs are pretty often combining unrelated features, e.g. PMICs which
>> have wakeup and system power control, regulator, 32 kHz clocks, RTC
>> and some USB connector.
> 
> Here also same right? pwm, counter and clock are 3 unrelated features.
> That is the reason we have separate subsystems for these features.

These are quite similar features of a similar piece of hardware.
Sometimes called timer.

> 
>>
>> Just because you will have clocksource driver, PWM driver and timer
>> driver does not make it a MFD.
> 
> MFD is multi function device.

No. MFD is a Linux subsystem name. Not a device type. The bindings are
located in respective type.

> So are are you agreeing Clock source, PWM and
> timer are different functionalities or not? If not, why do we have 3 subsystems,
> if it is same?

Linux subsystems? We can have millions of them and it is not related to
bindings.


> Where do keep these bindings as there is only single "rz_mtu" bindings for these 3 different functionalities?

Again, focus on hardware not on Linux drivers. Hardware is called MTU -
Multi-Function TIMER Unit. Timer.

> pwm or counter or mfd?

Not MFD. I already proposed where to put it. Other Timer/PWM/Counter
units are also in timer.

Renesas is not special to get some exceptions.

Best regards,
Krzysztof

RE: [PATCH v4 4/4] mfd: Add RZ/G2L MTU3 PWM driver

[Biju Das]

> Subject: Re: [PATCH v4 4/4] mfd: Add RZ/G2L MTU3 PWM driver
> 
> On 11/10/2022 15:13, Biju Das wrote:
> >> Subject: Re: [PATCH v4 4/4] mfd: Add RZ/G2L MTU3 PWM driver
> >>
> >> On 10/10/2022 10:52, Biju Das wrote:
> >>> Add support for RZ/G2L MTU3 PWM driver. The IP supports following
> >> PWM
> >>> modes
> >>>
> >>> 1) PWM mode{1,2}
> >>> 2) Reset-synchronized PWM mode
> >>> 3) Complementary PWM mode{1,2,3}
> >>>
> >>> This patch adds basic pwm mode 1 support for RZ/G2L MTU3 driver by
> >>> creating separate logical channels for each IOs.
> >>>
> >>> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> >>> ---
> >>> v3->v4:
> >>>  * There is no resource associated with "rz-mtu3-pwm" compatible
> >>>    and moved the code to mfd subsystem as it binds against "rz-
> mtu".
> >>>  * Removed struct platform_driver rz_mtu3_pwm_driver.
> >>> v2->v3:
> >>>  * No change.
> >>> v1->v2:
> >>>  * Modelled as a single PWM device handling multiple channles.
> >>>  * Used PM framework to manage the clocks.
> >>> ---
> >>>  drivers/mfd/Kconfig       |   6 +
> >>>  drivers/mfd/Makefile      |   2 +
> >>>  drivers/mfd/rz-mtu3-pwm.c | 405
> >>> ++++++++++++++++++++++++++++++++++++++
> >>
> >> That's not a MFD driver. That's a PWM. Use proper subsystem and
> email
> >> prefix.
> >
> > See [1]
> > [1]
=03qSqax5tr5tAuDHBytn7xH%2BS6oU2xguui9mrshI
> > tCI%3D&amp;reserved=0
> >
> > It is a single driver that binds against "renesas,rz-mtu3", and
> > registers both the counter and the pwm functionalities. Just like
> the clock driver, which registers clock, reset, and PM Domain
> functionalities.
> 
> No, it is not a single driver. You just added a new file - PWM.

It is a single driver rz-mtu.ko binds with "renesas,rz-mtu3"

> 
> >
> > It is same here, a single MFD driver which binds against
> > ""renesas,rz-mtu3" and registers counter And pwm functionalities.
> >
> > rz-mtu-core is core driver which provides resources to child devices
> like counter and pwm.
> >
> > I already copied PWM subsystem in the loop. Am I missing anything
> > related to [1]
> 
> MFD subsystem is only a wrapper/parent over actual drivers. It's not
> meant to hold the subsystem-specific code, because relevant
> maintainers will not look here.
> 
> So no, here and in other files - don't put subsystem specific code
> like PWM or timer into MFD.

Where should do we put, if there is single driver to be bind against 
"renesas,rz-mtu3" and register functionalities for pwm and counter??

Please suggest.

Cheers,
Biju

Re: [PATCH v4 4/4] mfd: Add RZ/G2L MTU3 PWM driver

[Krzysztof Kozlowski]

On 11/10/2022 16:18, Biju Das wrote:
>> Subject: Re: [PATCH v4 4/4] mfd: Add RZ/G2L MTU3 PWM driver
>>
>> On 11/10/2022 15:13, Biju Das wrote:
>>>> Subject: Re: [PATCH v4 4/4] mfd: Add RZ/G2L MTU3 PWM driver
>>>>
>>>> On 10/10/2022 10:52, Biju Das wrote:
>>>>> Add support for RZ/G2L MTU3 PWM driver. The IP supports following
>>>> PWM
>>>>> modes
>>>>>
>>>>> 1) PWM mode{1,2}
>>>>> 2) Reset-synchronized PWM mode
>>>>> 3) Complementary PWM mode{1,2,3}
>>>>>
>>>>> This patch adds basic pwm mode 1 support for RZ/G2L MTU3 driver by
>>>>> creating separate logical channels for each IOs.
>>>>>
>>>>> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
>>>>> ---
>>>>> v3->v4:
>>>>>  * There is no resource associated with "rz-mtu3-pwm" compatible
>>>>>    and moved the code to mfd subsystem as it binds against "rz-
>> mtu".
>>>>>  * Removed struct platform_driver rz_mtu3_pwm_driver.
>>>>> v2->v3:
>>>>>  * No change.
>>>>> v1->v2:
>>>>>  * Modelled as a single PWM device handling multiple channles.
>>>>>  * Used PM framework to manage the clocks.
>>>>> ---
>>>>>  drivers/mfd/Kconfig       |   6 +
>>>>>  drivers/mfd/Makefile      |   2 +
>>>>>  drivers/mfd/rz-mtu3-pwm.c | 405
>>>>> ++++++++++++++++++++++++++++++++++++++
>>>>
>>>> That's not a MFD driver. That's a PWM. Use proper subsystem and
>> email
>>>> prefix.
>>>
>>> See [1]
>>> [1]
> =03qSqax5tr5tAuDHBytn7xH%2BS6oU2xguui9mrshI
>>> tCI%3D&amp;reserved=0
>>>
>>> It is a single driver that binds against "renesas,rz-mtu3", and
>>> registers both the counter and the pwm functionalities. Just like
>> the clock driver, which registers clock, reset, and PM Domain
>> functionalities.
>>
>> No, it is not a single driver. You just added a new file - PWM.
> 
> It is a single driver rz-mtu.ko binds with "renesas,rz-mtu3"

Binding to compatible is not really related.

> 
>>
>>>
>>> It is same here, a single MFD driver which binds against
>>> ""renesas,rz-mtu3" and registers counter And pwm functionalities.
>>>
>>> rz-mtu-core is core driver which provides resources to child devices
>> like counter and pwm.
>>>
>>> I already copied PWM subsystem in the loop. Am I missing anything
>>> related to [1]
>>
>> MFD subsystem is only a wrapper/parent over actual drivers. It's not
>> meant to hold the subsystem-specific code, because relevant
>> maintainers will not look here.
>>
>> So no, here and in other files - don't put subsystem specific code
>> like PWM or timer into MFD.
> 
> Where should do we put, if there is single driver to be bind against 
> "renesas,rz-mtu3" and register functionalities for pwm and counter??

Again - how binding is related to this problem? If you have separate
drivers, e.g. counter, timer and PWM, all go to their respective
subsystems. Counter goes to counter, timer to timer, PWM to pwm.

MFD is only the glue/parent/wrapper to instantiate them.


Best regards,
Krzysztof

RE: [PATCH v4 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a bindings

[Biju Das]

> Subject: Re: [PATCH v4 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a
> bindings
> 
> On 11/10/2022 15:23, Biju Das wrote:
> >> Subject: Re: [PATCH v4 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a
> >> bindings
> >>
> >> On 11/10/2022 10:55, Biju Das wrote:
> >>>
> >>>>>  .../bindings/mfd/renesas,rz-mtu3.yaml         | 305
> >>>> ++++++++++++++++++
> >>>>>  1 file changed, 305 insertions(+)  create mode 100644
> >>>>> Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
> >>>>
> >>>> This should not be in MFD. Just because some device has few
> >> features,
> >>>> does not mean it should go to MFD... Choose either timer or pwm.
> >>>
> >>> MFD is for multifunction device. This IP supports multiple
> functions
> >>> like timer, pwm, clock source/events. That is the reason I have
> >> added
> >>> here. MFD is core which provides register access for client
> devices.
> >>>
> >>> For me moving it to pwm or counter is not a big problem.
> >>> Why do you think it cannot be MFD?
> >>
> >>
> >> Because it makes MFD a dump for everything where author did not
> want
> >> to think about real device aspects, but instead represented driver
> >> design (MFD driver).
> >
> > Core driver is MFD, just provides resources to child devices and is
> > not aware of any real device aspects.
> >
> >>
> >> MFDs are pretty often combining unrelated features, e.g. PMICs
> which
> >> have wakeup and system power control, regulator, 32 kHz clocks, RTC
> >> and some USB connector.
> >
> > Here also same right? pwm, counter and clock are 3 unrelated
> features.
> > That is the reason we have separate subsystems for these features.
> 
> These are quite similar features of a similar piece of hardware.
> Sometimes called timer.
> 
> >
> >>
> >> Just because you will have clocksource driver, PWM driver and timer
> >> driver does not make it a MFD.
> >
> > MFD is multi function device.
> 
> No. MFD is a Linux subsystem name. Not a device type. The bindings are
> located in respective type.
> 
> > So are are you agreeing Clock source, PWM and timer are different
> > functionalities or not? If not, why do we have 3 subsystems, if it
> is
> > same?
> 
> Linux subsystems? We can have millions of them and it is not related
> to bindings.

OK.

> 
> 
> > Where do keep these bindings as there is only single "rz_mtu"
> bindings for these 3 different functionalities?
> 
> Again, focus on hardware not on Linux drivers. Hardware is called MTU
> - Multi-Function TIMER Unit. Timer.

OK
> 
> > pwm or counter or mfd?
> 
> Not MFD. I already proposed where to put it. Other Timer/PWM/Counter
> units are also in timer.
> 

I guess for counter/pwm maintainers, it is ok to model MTU3 as a single 
binding "rz-mtu3" in timer that binds against counter and pwm 
functionalities as well??

Cheers,
Biju

RE: [PATCH v4 4/4] mfd: Add RZ/G2L MTU3 PWM driver

[Biju Das]

> Subject: Re: [PATCH v4 4/4] mfd: Add RZ/G2L MTU3 PWM driver
> 
> On 11/10/2022 16:18, Biju Das wrote:
> >> Subject: Re: [PATCH v4 4/4] mfd: Add RZ/G2L MTU3 PWM driver
> >>
> >> On 11/10/2022 15:13, Biju Das wrote:
> >>>> Subject: Re: [PATCH v4 4/4] mfd: Add RZ/G2L MTU3 PWM driver
> >>>>
> >>>> On 10/10/2022 10:52, Biju Das wrote:
> >>>>> Add support for RZ/G2L MTU3 PWM driver. The IP supports
> following
> >>>> PWM
> >>>>> modes
> >>>>>
> >>>>> 1) PWM mode{1,2}
> >>>>> 2) Reset-synchronized PWM mode
> >>>>> 3) Complementary PWM mode{1,2,3}
> >>>>>
> >>>>> This patch adds basic pwm mode 1 support for RZ/G2L MTU3 driver
> by
> >>>>> creating separate logical channels for each IOs.
> >>>>>
> >>>>> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> >>>>> ---
> >>>>> v3->v4:
> >>>>>  * There is no resource associated with "rz-mtu3-pwm" compatible
> >>>>>    and moved the code to mfd subsystem as it binds against "rz-
> >> mtu".
> >>>>>  * Removed struct platform_driver rz_mtu3_pwm_driver.
> >>>>> v2->v3:
> >>>>>  * No change.
> >>>>> v1->v2:
> >>>>>  * Modelled as a single PWM device handling multiple channles.
> >>>>>  * Used PM framework to manage the clocks.
> >>>>> ---
> >>>>>  drivers/mfd/Kconfig       |   6 +
> >>>>>  drivers/mfd/Makefile      |   2 +
> >>>>>  drivers/mfd/rz-mtu3-pwm.c | 405
> >>>>> ++++++++++++++++++++++++++++++++++++++
> >>>>
> >>>> That's not a MFD driver. That's a PWM. Use proper subsystem and
> >> email
> >>>> prefix.
> >>>
> >>> See [1]
> >>> [1]
> > =03qSqax5tr5tAuDHBytn7xH%2BS6oU2xguui9mrshI
> >>> tCI%3D&amp;reserved=0
> >>>
> >>> It is a single driver that binds against "renesas,rz-mtu3", and
> >>> registers both the counter and the pwm functionalities. Just like
> >> the clock driver, which registers clock, reset, and PM Domain
> >> functionalities.
> >>
> >> No, it is not a single driver. You just added a new file - PWM.
> >
> > It is a single driver rz-mtu.ko binds with "renesas,rz-mtu3"
> 
> Binding to compatible is not really related.
> 
> >
> >>
> >>>
> >>> It is same here, a single MFD driver which binds against
> >>> ""renesas,rz-mtu3" and registers counter And pwm functionalities.
> >>>
> >>> rz-mtu-core is core driver which provides resources to child
> devices
> >> like counter and pwm.
> >>>
> >>> I already copied PWM subsystem in the loop. Am I missing anything
> >>> related to [1]
> >>
> >> MFD subsystem is only a wrapper/parent over actual drivers. It's
> not
> >> meant to hold the subsystem-specific code, because relevant
> >> maintainers will not look here.
> >>
> >> So no, here and in other files - don't put subsystem specific code
> >> like PWM or timer into MFD.
> >
> > Where should do we put, if there is single driver to be bind against
> > "renesas,rz-mtu3" and register functionalities for pwm and counter??
> 
> Again - how binding is related to this problem? If you have separate
> drivers, e.g. counter, timer and PWM, all go to their respective
> subsystems. Counter goes to counter, timer to timer, PWM to pwm.

How do you instantiate these drivers with a single compatible "renesas,rz-mtu3"?
If it is separate drivers.

Please let me know.

Cheers,
Biju

Re: [PATCH v4 4/4] mfd: Add RZ/G2L MTU3 PWM driver

[Krzysztof Kozlowski]

On 11/10/2022 16:35, Biju Das wrote:
>>>>
>>>> So no, here and in other files - don't put subsystem specific code
>>>> like PWM or timer into MFD.
>>>
>>> Where should do we put, if there is single driver to be bind against
>>> "renesas,rz-mtu3" and register functionalities for pwm and counter??
>>
>> Again - how binding is related to this problem? If you have separate
>> drivers, e.g. counter, timer and PWM, all go to their respective
>> subsystems. Counter goes to counter, timer to timer, PWM to pwm.
> 
> How do you instantiate these drivers with a single compatible "renesas,rz-mtu3"?
> If it is separate drivers.
> 

With MFD framework and mfd_cell, just like many, many other drivers.

Best regards,
Krzysztof

RE: [PATCH v4 4/4] mfd: Add RZ/G2L MTU3 PWM driver

[Biju Das]

> Subject: Re: [PATCH v4 4/4] mfd: Add RZ/G2L MTU3 PWM driver
> 
> On 11/10/2022 16:35, Biju Das wrote:
> >>>>
> >>>> So no, here and in other files - don't put subsystem specific
> code
> >>>> like PWM or timer into MFD.
> >>>
> >>> Where should do we put, if there is single driver to be bind
> against
> >>> "renesas,rz-mtu3" and register functionalities for pwm and
> counter??
> >>
> >> Again - how binding is related to this problem? If you have
> separate
> >> drivers, e.g. counter, timer and PWM, all go to their respective
> >> subsystems. Counter goes to counter, timer to timer, PWM to pwm.
> >
> > How do you instantiate these drivers with a single compatible
> "renesas,rz-mtu3"?
> > If it is separate drivers.
> >
> 
> With MFD framework and mfd_cell, just like many, many other drivers.

They all have compatibles for child devices, right??

Can you please Provide an MFD example which has a single compatible and 
Multiple child devices in different subsystems??

Cheers,
Biju

Re: [PATCH v4 4/4] mfd: Add RZ/G2L MTU3 PWM driver

[Krzysztof Kozlowski]

On 11/10/2022 16:43, Biju Das wrote:
>> Subject: Re: [PATCH v4 4/4] mfd: Add RZ/G2L MTU3 PWM driver
>>
>> On 11/10/2022 16:35, Biju Das wrote:
>>>>>>
>>>>>> So no, here and in other files - don't put subsystem specific
>> code
>>>>>> like PWM or timer into MFD.
>>>>>
>>>>> Where should do we put, if there is single driver to be bind
>> against
>>>>> "renesas,rz-mtu3" and register functionalities for pwm and
>> counter??
>>>>
>>>> Again - how binding is related to this problem? If you have
>> separate
>>>> drivers, e.g. counter, timer and PWM, all go to their respective
>>>> subsystems. Counter goes to counter, timer to timer, PWM to pwm.
>>>
>>> How do you instantiate these drivers with a single compatible
>> "renesas,rz-mtu3"?
>>> If it is separate drivers.
>>>
>>
>> With MFD framework and mfd_cell, just like many, many other drivers.
> 
> They all have compatibles for child devices, right??

No

> Can you please Provide an MFD example which has a single compatible and 
> Multiple child devices in different subsystems??

There is plenty of examples:
git grep -C 4 'struct mfd_cell'

Even the first search result in MFD directory fits your needs, doesn't it?

Best regards,
Krzysztof

RE: [PATCH v4 4/4] mfd: Add RZ/G2L MTU3 PWM driver

[Biju Das]

Hi Krzysztof Kozlowski,

> Subject: Re: [PATCH v4 4/4] mfd: Add RZ/G2L MTU3 PWM driver
> 
> On 11/10/2022 16:43, Biju Das wrote:
> >> Subject: Re: [PATCH v4 4/4] mfd: Add RZ/G2L MTU3 PWM driver
> >>
> >> On 11/10/2022 16:35, Biju Das wrote:
> >>>>>>
> >>>>>> So no, here and in other files - don't put subsystem specific
> >> code
> >>>>>> like PWM or timer into MFD.
> >>>>>
> >>>>> Where should do we put, if there is single driver to be bind
> >> against
> >>>>> "renesas,rz-mtu3" and register functionalities for pwm and
> >> counter??
> >>>>
> >>>> Again - how binding is related to this problem? If you have
> >> separate
> >>>> drivers, e.g. counter, timer and PWM, all go to their respective
> >>>> subsystems. Counter goes to counter, timer to timer, PWM to pwm.
> >>>
> >>> How do you instantiate these drivers with a single compatible
> >> "renesas,rz-mtu3"?
> >>> If it is separate drivers.
> >>>
> >>
> >> With MFD framework and mfd_cell, just like many, many other
> drivers.
> >
> > They all have compatibles for child devices, right??
> 
> No
> 
> > Can you please Provide an MFD example which has a single compatible
> > and Multiple child devices in different subsystems??
> 
> There is plenty of examples:
> git grep -C 4 'struct mfd_cell'
> 
> Even the first search result in MFD directory fits your needs, doesn't
> it?

Thanks for the pointer. Will send next version based on this.

Cheers,
Biju

Re: [PATCH v4 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a bindings

[William Breathitt Gray]

[-- Attachment #1: Type: text/plain, Size: 4568 bytes --]

On Tue, Oct 11, 2022 at 08:31:48PM +0000, Biju Das wrote:
> > Subject: Re: [PATCH v4 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a
> > bindings
> > 
> > On 11/10/2022 15:23, Biju Das wrote:
> > >> Subject: Re: [PATCH v4 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a
> > >> bindings
> > >>
> > >> On 11/10/2022 10:55, Biju Das wrote:
> > >>>
> > >>>>>  .../bindings/mfd/renesas,rz-mtu3.yaml         | 305
> > >>>> ++++++++++++++++++
> > >>>>>  1 file changed, 305 insertions(+)  create mode 100644
> > >>>>> Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
> > >>>>
> > >>>> This should not be in MFD. Just because some device has few
> > >> features,
> > >>>> does not mean it should go to MFD... Choose either timer or pwm.
> > >>>
> > >>> MFD is for multifunction device. This IP supports multiple
> > functions
> > >>> like timer, pwm, clock source/events. That is the reason I have
> > >> added
> > >>> here. MFD is core which provides register access for client
> > devices.
> > >>>
> > >>> For me moving it to pwm or counter is not a big problem.
> > >>> Why do you think it cannot be MFD?
> > >>
> > >>
> > >> Because it makes MFD a dump for everything where author did not
> > want
> > >> to think about real device aspects, but instead represented driver
> > >> design (MFD driver).
> > >
> > > Core driver is MFD, just provides resources to child devices and is
> > > not aware of any real device aspects.
> > >
> > >>
> > >> MFDs are pretty often combining unrelated features, e.g. PMICs
> > which
> > >> have wakeup and system power control, regulator, 32 kHz clocks, RTC
> > >> and some USB connector.
> > >
> > > Here also same right? pwm, counter and clock are 3 unrelated
> > features.
> > > That is the reason we have separate subsystems for these features.
> > 
> > These are quite similar features of a similar piece of hardware.
> > Sometimes called timer.
> > 
> > >
> > >>
> > >> Just because you will have clocksource driver, PWM driver and timer
> > >> driver does not make it a MFD.
> > >
> > > MFD is multi function device.
> > 
> > No. MFD is a Linux subsystem name. Not a device type. The bindings are
> > located in respective type.
> > 
> > > So are are you agreeing Clock source, PWM and timer are different
> > > functionalities or not? If not, why do we have 3 subsystems, if it
> > is
> > > same?
> > 
> > Linux subsystems? We can have millions of them and it is not related
> > to bindings.
> 
> OK.
> 
> > 
> > 
> > > Where do keep these bindings as there is only single "rz_mtu"
> > bindings for these 3 different functionalities?
> > 
> > Again, focus on hardware not on Linux drivers. Hardware is called MTU
> > - Multi-Function TIMER Unit. Timer.
> 
> OK
> > 
> > > pwm or counter or mfd?
> > 
> > Not MFD. I already proposed where to put it. Other Timer/PWM/Counter
> > units are also in timer.
> > 
> 
> I guess for counter/pwm maintainers, it is ok to model MTU3 as a single 
> binding "rz-mtu3" in timer that binds against counter and pwm 
> functionalities as well??
> 
> Cheers,
> Biju

I'm okay with putting the MTU3 binding under timer; we already have
Documentation/devicetree/bindings/timer/renesas,mtu2.yaml there so
adding a new renesas,mtu3.yaml next to it seems reasonable.

Just to reiterate Krzysztof's point, the subsystems in Linux serve as a
way to group drivers together that utilize the same ABIs, whereas the
devicetree is a structure for organizing physical hardware. The
structure of physical hardware types don't necessarily match the
organization of the ABIs we use to support them. This is why you may end
up with differing heirarchies between the devicetree and driver
subsystems.

To illustrate the point, take for example a hypothetical
digital-to-analog (DAC) device with a few GPIO lines. Those GPIO
input signals could be tied to buttons used to indicate to the system
that a user wants to reset or adjust the DAC output, while the GPIO
output signals could be status lights or triggers indicating that the
DAC is operating. The respective driver for this device may utilize the
IIO subsystem to support the DAC and the GPIO subsystem to support those
GPIO lines, but it would be incorrect to put this under MFD because the
purpose of the GPIO lines is to assist in the operation of the DAC; in
other words, this is primarily a DAC device with some auxiliary
convenience functionalities, not a MFD with distinct unrelated separate
components.

William Breathitt Gray

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RE: [PATCH v4 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a bindings

[Biju Das]

Hi William Breathitt Gray,

> Subject: Re: [PATCH v4 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a
> bindings
> 
> On Tue, Oct 11, 2022 at 08:31:48PM +0000, Biju Das wrote:
> > > Subject: Re: [PATCH v4 1/4] dt-bindings: mfd: Document RZ/G2L
> MTU3a
> > > bindings
> > >
> > > On 11/10/2022 15:23, Biju Das wrote:
> > > >> Subject: Re: [PATCH v4 1/4] dt-bindings: mfd: Document RZ/G2L
> > > >> MTU3a bindings
> > > >>
> > > >> On 11/10/2022 10:55, Biju Das wrote:
> > > >>>
> > > >>>>>  .../bindings/mfd/renesas,rz-mtu3.yaml         | 305
> > > >>>> ++++++++++++++++++
> > > >>>>>  1 file changed, 305 insertions(+)  create mode 100644
> > > >>>>> Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
> > > >>>>
> > > >>>> This should not be in MFD. Just because some device has few
> > > >> features,
> > > >>>> does not mean it should go to MFD... Choose either timer or
> pwm.
> > > >>>
> > > >>> MFD is for multifunction device. This IP supports multiple
> > > functions
> > > >>> like timer, pwm, clock source/events. That is the reason I
> have
> > > >> added
> > > >>> here. MFD is core which provides register access for client
> > > devices.
> > > >>>
> > > >>> For me moving it to pwm or counter is not a big problem.
> > > >>> Why do you think it cannot be MFD?
> > > >>
> > > >>
> > > >> Because it makes MFD a dump for everything where author did not
> > > want
> > > >> to think about real device aspects, but instead represented
> > > >> driver design (MFD driver).
> > > >
> > > > Core driver is MFD, just provides resources to child devices and
> > > > is not aware of any real device aspects.
> > > >
> > > >>
> > > >> MFDs are pretty often combining unrelated features, e.g. PMICs
> > > which
> > > >> have wakeup and system power control, regulator, 32 kHz clocks,
> > > >> RTC and some USB connector.
> > > >
> > > > Here also same right? pwm, counter and clock are 3 unrelated
> > > features.
> > > > That is the reason we have separate subsystems for these
> features.
> > >
> > > These are quite similar features of a similar piece of hardware.
> > > Sometimes called timer.
> > >
> > > >
> > > >>
> > > >> Just because you will have clocksource driver, PWM driver and
> > > >> timer driver does not make it a MFD.
> > > >
> > > > MFD is multi function device.
> > >
> > > No. MFD is a Linux subsystem name. Not a device type. The bindings
> > > are located in respective type.
> > >
> > > > So are are you agreeing Clock source, PWM and timer are
> different
> > > > functionalities or not? If not, why do we have 3 subsystems, if
> it
> > > is
> > > > same?
> > >
> > > Linux subsystems? We can have millions of them and it is not
> related
> > > to bindings.
> >
> > OK.
> >
> > >
> > >
> > > > Where do keep these bindings as there is only single "rz_mtu"
> > > bindings for these 3 different functionalities?
> > >
> > > Again, focus on hardware not on Linux drivers. Hardware is called
> > > MTU
> > > - Multi-Function TIMER Unit. Timer.
> >
> > OK
> > >
> > > > pwm or counter or mfd?
> > >
> > > Not MFD. I already proposed where to put it. Other
> Timer/PWM/Counter
> > > units are also in timer.
> > >
> >
> > I guess for counter/pwm maintainers, it is ok to model MTU3 as a
> > single binding "rz-mtu3" in timer that binds against counter and pwm
> > functionalities as well??
> >
> > Cheers,
> > Biju
> 
> I'm okay with putting the MTU3 binding under timer; we already have
> Documentation/devicetree/bindings/timer/renesas,mtu2.yaml there so
> adding a new renesas,mtu3.yaml next to it seems reasonable.

OK.

> 
> Just to reiterate Krzysztof's point, the subsystems in Linux serve as
> a way to group drivers together that utilize the same ABIs, whereas
> the devicetree is a structure for organizing physical hardware. The
> structure of physical hardware types don't necessarily match the
> organization of the ABIs we use to support them. This is why you may
> end up with differing heirarchies between the devicetree and driver
> subsystems.
> 
> To illustrate the point, take for example a hypothetical digital-to-
> analog (DAC) device with a few GPIO lines. Those GPIO input signals
> could be tied to buttons used to indicate to the system that a user
> wants to reset or adjust the DAC output, while the GPIO output signals
> could be status lights or triggers indicating that the DAC is
> operating. The respective driver for this device may utilize the IIO
> subsystem to support the DAC and the GPIO subsystem to support those
> GPIO lines, but it would be incorrect to put this under MFD because
> the purpose of the GPIO lines is to assist in the operation of the
> DAC; in other words, this is primarily a DAC device with some
> auxiliary convenience functionalities, not a MFD with distinct
> unrelated separate components.

OK agreed. Thanks for the explanation.

Cheers,
Biju

Re: [PATCH v4 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a bindings

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 5776 bytes --]

On Sat, Oct 15, 2022 at 10:28:53AM -0400, William Breathitt Gray wrote:
> On Tue, Oct 11, 2022 at 08:31:48PM +0000, Biju Das wrote:
> > > Subject: Re: [PATCH v4 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a
> > > bindings
> > > 
> > > On 11/10/2022 15:23, Biju Das wrote:
> > > >> Subject: Re: [PATCH v4 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a
> > > >> bindings
> > > >>
> > > >> On 11/10/2022 10:55, Biju Das wrote:
> > > >>>
> > > >>>>>  .../bindings/mfd/renesas,rz-mtu3.yaml         | 305
> > > >>>> ++++++++++++++++++
> > > >>>>>  1 file changed, 305 insertions(+)  create mode 100644
> > > >>>>> Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
> > > >>>>
> > > >>>> This should not be in MFD. Just because some device has few
> > > >> features,
> > > >>>> does not mean it should go to MFD... Choose either timer or pwm.
> > > >>>
> > > >>> MFD is for multifunction device. This IP supports multiple
> > > functions
> > > >>> like timer, pwm, clock source/events. That is the reason I have
> > > >> added
> > > >>> here. MFD is core which provides register access for client
> > > devices.
> > > >>>
> > > >>> For me moving it to pwm or counter is not a big problem.
> > > >>> Why do you think it cannot be MFD?
> > > >>
> > > >>
> > > >> Because it makes MFD a dump for everything where author did not
> > > want
> > > >> to think about real device aspects, but instead represented driver
> > > >> design (MFD driver).
> > > >
> > > > Core driver is MFD, just provides resources to child devices and is
> > > > not aware of any real device aspects.
> > > >
> > > >>
> > > >> MFDs are pretty often combining unrelated features, e.g. PMICs
> > > which
> > > >> have wakeup and system power control, regulator, 32 kHz clocks, RTC
> > > >> and some USB connector.
> > > >
> > > > Here also same right? pwm, counter and clock are 3 unrelated
> > > features.
> > > > That is the reason we have separate subsystems for these features.
> > > 
> > > These are quite similar features of a similar piece of hardware.
> > > Sometimes called timer.
> > > 
> > > >
> > > >>
> > > >> Just because you will have clocksource driver, PWM driver and timer
> > > >> driver does not make it a MFD.
> > > >
> > > > MFD is multi function device.
> > > 
> > > No. MFD is a Linux subsystem name. Not a device type. The bindings are
> > > located in respective type.
> > > 
> > > > So are are you agreeing Clock source, PWM and timer are different
> > > > functionalities or not? If not, why do we have 3 subsystems, if it
> > > is
> > > > same?
> > > 
> > > Linux subsystems? We can have millions of them and it is not related
> > > to bindings.
> > 
> > OK.
> > 
> > > 
> > > 
> > > > Where do keep these bindings as there is only single "rz_mtu"
> > > bindings for these 3 different functionalities?
> > > 
> > > Again, focus on hardware not on Linux drivers. Hardware is called MTU
> > > - Multi-Function TIMER Unit. Timer.
> > 
> > OK
> > > 
> > > > pwm or counter or mfd?
> > > 
> > > Not MFD. I already proposed where to put it. Other Timer/PWM/Counter
> > > units are also in timer.
> > > 
> > 
> > I guess for counter/pwm maintainers, it is ok to model MTU3 as a single 
> > binding "rz-mtu3" in timer that binds against counter and pwm 
> > functionalities as well??
> > 
> > Cheers,
> > Biju
> 
> I'm okay with putting the MTU3 binding under timer; we already have
> Documentation/devicetree/bindings/timer/renesas,mtu2.yaml there so
> adding a new renesas,mtu3.yaml next to it seems reasonable.
> 
> Just to reiterate Krzysztof's point, the subsystems in Linux serve as a
> way to group drivers together that utilize the same ABIs, whereas the
> devicetree is a structure for organizing physical hardware. The
> structure of physical hardware types don't necessarily match the
> organization of the ABIs we use to support them. This is why you may end
> up with differing heirarchies between the devicetree and driver
> subsystems.
> 
> To illustrate the point, take for example a hypothetical
> digital-to-analog (DAC) device with a few GPIO lines. Those GPIO
> input signals could be tied to buttons used to indicate to the system
> that a user wants to reset or adjust the DAC output, while the GPIO
> output signals could be status lights or triggers indicating that the
> DAC is operating. The respective driver for this device may utilize the
> IIO subsystem to support the DAC and the GPIO subsystem to support those
> GPIO lines, but it would be incorrect to put this under MFD because the
> purpose of the GPIO lines is to assist in the operation of the DAC; in
> other words, this is primarily a DAC device with some auxiliary
> convenience functionalities, not a MFD with distinct unrelated separate
> components.

Exactly. In addition to the DT aspect, another misconception is that a
driver for a multi-function device needs to be somehow split up to match
the Linux subsystem structure. In most cases that's not true. Pick the
subsystem that most closely fits the main function of a device and
implement the driver. If you can expose further functions using other
subsystems, that's absolutely fine. Drivers can register with multiple
subsystems at the same time.

Yes, that's not quite as neat as having individual drivers for each
subsystem, but it's a much better approximation of the hardware and
therefore will lead to more compact and stable drivers. Trying to split
things up arbitrarily often makes for wonky constructs.

We've gained powerful tools over the years to easily deal with cross-
subsystem drivers, so there's seldom a reason to strictly split things
across subsystem boundaries anymore.

Thierry

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Re: [PATCH v4 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a bindings

[Lee Jones]

On Tue, 11 Oct 2022, Biju Das wrote:

> 
> Hi Krzysztof Kozlowski,
> 
> > Subject: Re: [PATCH v4 1/4] dt-bindings: mfd: Document RZ/G2L MTU3a
> > bindings
> > 
> > On 10/10/2022 10:52, Biju Das wrote:
> > > The RZ/G2L multi-function timer pulse unit 3 (MTU3a) is embedded in
> > > the Renesas RZ/G2L family SoC's. It consists of eight 16-bit timer
> > > channels and one 32-bit timer channel. It supports the following
> > > functions
> > >  - Counter
> > >  - Timer
> > >  - PWM
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > ---
> > > v3->v4:
> > >  * Dropped counter and pwm compatibeles as they don't have any
> > resources.
> > >  * Made rz-mtu3 as pwm provider.
> > >  * Updated the example and description.
> > > v2->v3:
> > >  * Dropped counter bindings and integrated with mfd as it has only
> > one property.
> > >  * Removed "#address-cells" and "#size-cells" as it do not have
> > children with
> > >    unit addresses.
> > >  * Removed quotes from counter and pwm.
> > >  * Provided full path for pwm bindings.
> > >  * Updated the example.
> > > v1->v2:
> > >  * Modelled counter and pwm as a single device that handles
> > >    multiple channels.
> > >  * Moved counter and pwm bindings to respective subsystems
> > >  * Dropped 'bindings' from MFD binding title.
> > >  * Updated the example
> > >  * Changed the compatible names.
> > > ---
> > >  .../bindings/mfd/renesas,rz-mtu3.yaml         | 305
> > ++++++++++++++++++
> > >  1 file changed, 305 insertions(+)
> > >  create mode 100644
> > > Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml
> > 
> > This should not be in MFD. Just because some device has few features,
> > does not mean it should go to MFD... Choose either timer or pwm.
> 
> MFD is for multifunction device. This IP supports multiple functions
> like timer, pwm, clock source/events. That is the reason I have added 
> here. MFD is core which provides register access for client devices.
> 
> For me moving it to pwm or counter is not a big problem.
> Why do you think it cannot be MFD?

Sorry for jumping in late here.  I see this has been resolved.

The TL;DR is: if you're not using the MFD Core (and including
mfd/core.h), it's not an MFD.  You *could* split this up into its
component parts, place them into their own subsystems and use an MFD
core driver to register them all, but as Thierry says, this is not a
hard requirement either.

-- 
Lee Jones [李琼斯]

Re: [PATCH v4 4/4] mfd: Add RZ/G2L MTU3 PWM driver

[Geert Uytterhoeven]

Hi Biju,

On Mon, Oct 10, 2022 at 4:52 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add support for RZ/G2L MTU3 PWM driver. The IP supports
> following PWM modes
>
> 1) PWM mode{1,2}
> 2) Reset-synchronized PWM mode
> 3) Complementary PWM mode{1,2,3}
>
> This patch adds basic pwm mode 1 support for RZ/G2L MTU3 driver
> by creating separate logical channels for each IOs.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Thanks for your patch!

> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -1994,6 +1994,12 @@ config MFD_RZ_MTU3_CNT
>           SoCs. This IP supports both 16-bit and 32-bit phase counting mode
>           support.
>
> +config MFD_RZ_MTU3_PWM
> +       tristate "Renesas RZ/G2L MTU3 PWM Timer support"
> +       depends on MFD_RZ_MTU3

depends on PWM || COMPILE_TEST

Note that currently the build fails if CONFIG_PWM=n.
I have sent a patch to fix that
"[PATCH] pwm: Add missing dummy for devm_pwmchip_add()".
https://lore.kernel.org/r/12f2142991690d2b1d6890821f6e7779a4d4bdc0.1666706435.git.geert+renesas@glider.be

> +       help
> +         Enable support for RZ/G2L MTU3 PWM Timer controller.
> +
>  config MFD_STM32_LPTIMER
>         tristate "Support for STM32 Low-Power Timer"
>         depends on (ARCH_STM32 && OF) || COMPILE_TEST

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v4 4/4] mfd: Add RZ/G2L MTU3 PWM driver

[Biju Das]

Hi Geert,

Thanks for the feedback.

> Subject: Re: [PATCH v4 4/4] mfd: Add RZ/G2L MTU3 PWM driver
> 
> Hi Biju,
> 
> On Mon, Oct 10, 2022 at 4:52 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > Add support for RZ/G2L MTU3 PWM driver. The IP supports following
> PWM
> > modes
> >
> > 1) PWM mode{1,2}
> > 2) Reset-synchronized PWM mode
> > 3) Complementary PWM mode{1,2,3}
> >
> > This patch adds basic pwm mode 1 support for RZ/G2L MTU3 driver by
> > creating separate logical channels for each IOs.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Thanks for your patch!
> 
> > --- a/drivers/mfd/Kconfig
> > +++ b/drivers/mfd/Kconfig
> > @@ -1994,6 +1994,12 @@ config MFD_RZ_MTU3_CNT
> >           SoCs. This IP supports both 16-bit and 32-bit phase
> counting mode
> >           support.
> >
> > +config MFD_RZ_MTU3_PWM
> > +       tristate "Renesas RZ/G2L MTU3 PWM Timer support"
> > +       depends on MFD_RZ_MTU3
> 
> depends on PWM || COMPILE_TEST

OK, this will move to PWM as the core is going to be part of timer bindings
And pwm device is instantiated using mfd_add_device()


> 
> Note that currently the build fails if CONFIG_PWM=n.

> I have sent a patch to fix that
> "[PATCH] pwm: Add missing dummy for devm_pwmchip_add()".

OK, looks currently no one outside pwm subsystem is accessing this function.

Cheers,
Biju

> 
> > +       help
> > +         Enable support for RZ/G2L MTU3 PWM Timer controller.
> > +
> >  config MFD_STM32_LPTIMER
> >         tristate "Support for STM32 Low-Power Timer"
> >         depends on (ARCH_STM32 && OF) || COMPILE_TEST
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 --
> geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a
> hacker. But when I'm talking to journalists I just say "programmer" or
> something like that.
>                                 -- Linus Torvalds