From: Wenpeng Liang <liangwenpeng@huawei.com>
To: <jgg@nvidia.com>, <leon@kernel.org>
Cc: <linux-rdma@vger.kernel.org>, <linuxarm@huawei.com>,
<liangwenpeng@huawei.com>
Subject: [PATCH v3 for-next 1/5] RDMA/hns: Remove unused abnormal interrupt of type RAS
Date: Thu, 14 Jul 2022 21:43:49 +0800 [thread overview]
Message-ID: <20220714134353.16700-2-liangwenpeng@huawei.com> (raw)
In-Reply-To: <20220714134353.16700-1-liangwenpeng@huawei.com>
From: Haoyue Xu <xuhaoyue1@hisilicon.com>
The HNS NIC driver receives and handles the abnormal interrupt of the RAS
type generated by ROCEE, and the HNS RDMA driver does not need to handle
this type of interrupt. Therefore, delete unused codes in the HNS RDMA
driver.
Signed-off-by: Haoyue Xu <xuhaoyue1@hisilicon.com>
Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com>
---
drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 10 ----------
drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 1 -
2 files changed, 11 deletions(-)
diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
index ba3c742258ef..617713084383 100644
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
@@ -6013,16 +6013,6 @@ static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id)
int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S;
roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
- int_work = 1;
- } else if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_RAS_INT_S)) {
- dev_err(dev, "RAS interrupt!\n");
-
- int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_RAS_INT_S;
- roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
-
- int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S;
- roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
-
int_work = 1;
} else {
dev_err(dev, "There is no abnormal irq found!\n");
diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
index 7ffb7824d268..e6186149ef19 100644
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
@@ -1382,7 +1382,6 @@ struct hns_roce_dip {
#define HNS_ROCE_V2_ASYNC_EQE_NUM 0x1000
#define HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S 0
-#define HNS_ROCE_V2_VF_INT_ST_RAS_INT_S 1
#define HNS_ROCE_EQ_DB_CMD_AEQ 0x0
#define HNS_ROCE_EQ_DB_CMD_AEQ_ARMED 0x1
--
2.33.0
next prev parent reply other threads:[~2022-07-14 13:45 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-14 13:43 [PATCH v3 for-next 0/5] RDMA/hns: Supports recovery of on-chip RAM 1bit ECC errors Wenpeng Liang
2022-07-14 13:43 ` Wenpeng Liang [this message]
2022-07-14 13:43 ` [PATCH v3 for-next 2/5] RDMA/hns: Fix the wrong type of return value of the interrupt handler Wenpeng Liang
2022-07-14 13:43 ` [PATCH v3 for-next 3/5] RDMA/hns: Fix incorrect clearing of interrupt status register Wenpeng Liang
2022-07-14 13:43 ` [PATCH v3 for-next 4/5] RDMA/hns: Refactor the abnormal interrupt handler function Wenpeng Liang
2022-07-14 13:43 ` [PATCH v3 for-next 5/5] RDMA/hns: Recover 1bit-ECC error of RAM on chip Wenpeng Liang
2022-07-18 11:17 ` [PATCH v3 for-next 0/5] RDMA/hns: Supports recovery of on-chip RAM 1bit ECC errors Leon Romanovsky
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