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From: Matthew W Carlis <mattc@purestorage.com>
To: macro@orcam.me.uk
Cc: alex.williamson@redhat.com, bhelgaas@google.com,
	davem@davemloft.net, david.abdurachmanov@gmail.com,
	edumazet@google.com, helgaas@kernel.org, kuba@kernel.org,
	leon@kernel.org, linux-kernel@vger.kernel.org,
	linux-pci@vger.kernel.org, linux-rdma@vger.kernel.org,
	linuxppc-dev@lists.ozlabs.org, lukas@wunner.de,
	mahesh@linux.ibm.com, mattc@purestorage.com,
	mika.westerberg@linux.intel.com, netdev@vger.kernel.org,
	npiggin@gmail.com, oohall@gmail.com, pabeni@redhat.com,
	pali@kernel.org, saeedm@nvidia.com, sr@denx.de,
	wilson@tuliptree.org
Subject: PCI: Work around PCIe link training failures
Date: Tue, 10 Jun 2025 00:00:44 -0700	[thread overview]
Message-ID: <20250610070044.92057-1-mattc@purestorage.com> (raw)
In-Reply-To: <alpine.DEB.2.21.2410031135250.45128@angie.orcam.me.uk>

Hello again.. It looks like there are specific system configurations that are
extremely likely to have issues with this patch & result in undesirable
system behavior..

  Specifically hot-plug systems with side-band presence detection & without
Power Controls (i.e PwrCtrl-) given to config space. It may also be related
to presence on U.2 connectors being first-to-mate/last-to-break, but
I don't have much experience with the different connectors. The main
issue is that the quirk is invoked in at least two common cases when
it is not expected that the link would train. 
  For example, if I power off the slot via an out-of-band vendor specific
mechanism we see the kernel decide that the link should be training,
presumable because it will see PresDet+ in Slot Status. In this case it
decides the link failed to train, writes the Gen1 speed value into TLS
(target link speed) & returns after waiting for the link one more time.
The next time the slot is powered on the link will train to Gen1 due to TLS.
  Another problematic case is when we physically insert a device. In my case
I am using nvme drives with U.2 connectors from several different vendors.
The presence event is often generated before the device is fully powered on
due to U.2 assigning presence as a first-to-mate & power being last-to-mate.
I believe in this case that the kernel is expecting the link to train too
soon & therefore we find that the quirk often applies the Gen1 TLS speed.
Later, when the link comes up it is frequently observed at Gen1. I tried
to unset bit 3 in Slot Control (Presence Detect Changed Enable), but we
still hit the first case I described with powering off slots.
  I should be clear and say that we are able to see devices forced to Gen1
extremely often in the side-band presence configuration. We would really like
to see this "quirk" removed or put behind an opt-in config since it causes
significant regression in common configurations of pcie-hotplug. I have tried
to come up with ideas to modify/improve the quirk, but I am not very
confident that there is a good solution if the kernel cannot know for certain
whether the link is expected to train.

Thanks,
-Matt

      reply	other threads:[~2025-06-10  7:00 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-11 17:19 [PATCH v9 00/14] pci: Work around ASMedia ASM2824 PCIe link training failures Maciej W. Rozycki
2023-06-11 17:19 ` [PATCH v9 01/14] PCI: pciehp: Rely on `link_active_reporting' Maciej W. Rozycki
2023-06-11 17:19 ` [PATCH v9 02/14] PCI: Export PCIe link retrain timeout Maciej W. Rozycki
2023-06-11 17:19 ` [PATCH v9 03/14] PCI: Execute `quirk_enable_clear_retrain_link' earlier Maciej W. Rozycki
2023-06-11 17:19 ` [PATCH v9 04/14] PCI: Initialize `link_active_reporting' earlier Maciej W. Rozycki
2023-06-11 17:19 ` [PATCH v9 05/14] powerpc/eeh: Rely on `link_active_reporting' Maciej W. Rozycki
2023-06-11 17:19 ` [PATCH v9 06/14] net/mlx5: " Maciej W. Rozycki
2023-06-11 17:19 ` [PATCH v9 07/14] PCI: Export `pcie_retrain_link' for use outside ASPM Maciej W. Rozycki
2023-06-11 17:19 ` [PATCH v9 08/14] PCI: Use distinct local vars in `pcie_retrain_link' Maciej W. Rozycki
2023-06-11 17:19 ` [PATCH v9 09/14] PCI: Factor our waiting for link training end Maciej W. Rozycki
2023-06-11 17:19 ` [PATCH v9 10/14] PCI: Add support for polling DLLLA to `pcie_retrain_link' Maciej W. Rozycki
2023-06-11 17:19 ` [PATCH v9 11/14] PCI: Use `pcie_wait_for_link_status' in `pcie_wait_for_link_delay' Maciej W. Rozycki
2023-06-11 17:20 ` [PATCH v9 12/14] PCI: Provide stub failed link recovery for device probing and hot plug Maciej W. Rozycki
2024-07-22 19:34   ` PCI: Work around PCIe link training failures Matthew W Carlis
2024-07-22 20:40     ` Maciej W. Rozycki
2024-07-24 19:18       ` Matthew W Carlis
2024-07-26  8:04         ` Matthew W Carlis
2024-07-29 10:27           ` Ilpo Järvinen
2024-07-29 14:51             ` Maciej W. Rozycki
2024-07-29 18:56               ` Matthew W Carlis
2023-06-11 17:20 ` [PATCH v9 13/14] PCI: Add failed link recovery for device reset events Maciej W. Rozycki
2023-06-11 17:20 ` [PATCH v9 14/14] PCI: Work around PCIe link training failures Maciej W. Rozycki
2023-06-14 23:12 ` [PATCH v9 00/14] pci: Work around ASMedia ASM2824 " Bjorn Helgaas
2023-06-15  0:41   ` Maciej W. Rozycki
2023-06-15 18:37     ` Bjorn Helgaas
2023-06-16 12:27       ` Maciej W. Rozycki
2023-06-16 20:29         ` Bjorn Helgaas
2023-06-20  9:54           ` Maciej W. Rozycki
2024-08-06  0:06             ` PCI: Work around " Matthew W Carlis
2024-08-06 19:36               ` Bjorn Helgaas
2024-08-07  8:43                 ` Matthew W Carlis
2024-08-07 11:14                   ` Maciej W. Rozycki
2024-08-07 12:29                     ` Oliver O'Halloran
2024-08-07 11:49               ` Maciej W. Rozycki
2024-08-08  2:07                 ` Matthew W Carlis
2024-08-08 23:13                   ` Oliver O'Halloran
2024-08-09 13:34                   ` Maciej W. Rozycki
2024-08-15 19:40                     ` Matthew W Carlis
2024-08-16 13:57                       ` Maciej W. Rozycki
2024-10-01 21:04                         ` Matthew W Carlis
2024-10-02 12:58                           ` Maciej W. Rozycki
2024-10-02 20:55                             ` Bjorn Helgaas
2024-10-03 10:39                               ` Maciej W. Rozycki
2025-06-10  7:00                                 ` Matthew W Carlis [this message]

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