[PATCH 0/3] Least attached vector support

[PATCH 0/3] Least attached vector support

[Yevgeny Petrilin]

Hello Roland,

Those patches where submitted a while ago, I cleaned them up a little and generated against your latest git.
They allow to hw driver to choose to which EQ a CQ would be attached, considering the load on its eqs.

Thanks,
Yevgeny
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Re: [PATCH 0/3] Least attached vector support

[Bart Van Assche]

Yevgeny Petrilin <yevgenyp@...> writes:

> Hello Roland,
> 
> Those patches where submitted a while ago, I cleaned them up a little and
generated against your latest git.
> They allow to hw driver to choose to which EQ a CQ would be attached,
considering the load on its eqs.

(replying to an e-mail from three years ago)

Hello,

Can anyone tell me what happened with this patch series ? To me this looks like
a useful patch series to make the mlx4_en driver faster. However, I haven't seen
anyone posting any review comments to this series and apparently this
functionality isn't upstream either.

Thanks,

Bart.

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Re: [PATCH 0/3] Least attached vector support

[Roland Dreier]

On Tue, Apr 2, 2013 at 7:20 AM, Bart Van Assche <bvanassche-HInyCGIudOg@public.gmane.org> wrote:
> Can anyone tell me what happened with this patch series ? To me this looks like
> a useful patch series to make the mlx4_en driver faster. However, I haven't seen
> anyone posting any review comments to this series and apparently this
> functionality isn't upstream either.

It was never clear to me that "number of CQs attached" is a
particularly good way to choose an interrupt vector.  It would seem to
me that we would want something that takes into account CPU affinity,
possibly NUMA effects, etc.  Also I don't think there were any
performance numbers posted for these changes, were there?

(BTW It would be interesting to know how much improvement one could
get on modern 2/4 socket systems by allocating EQ, CQ, QP, etc. memory
on the "right" NUMA node -- where I don't know if "right" means on the
node closest to the adapter or the node where the CPU will access the
queue)
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