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From: liweihang <liweihang@huawei.com>
To: Leon Romanovsky <leon@kernel.org>
Cc: "dledford@redhat.com" <dledford@redhat.com>,
	"jgg@ziepe.ca" <jgg@ziepe.ca>,
	"linux-rdma@vger.kernel.org" <linux-rdma@vger.kernel.org>,
	Linuxarm <linuxarm@huawei.com>
Subject: Re: [PATCH v2 for-next 1/2] RDMA/hns: Add support for CQ stash
Date: Tue, 17 Nov 2020 08:35:55 +0000	[thread overview]
Message-ID: <f688022a7cce488a82ce0d8427a1054e@huawei.com> (raw)
In-Reply-To: 20201117072034.GO47002@unreal

On 2020/11/17 15:21, Leon Romanovsky wrote:
> On Tue, Nov 17, 2020 at 06:37:58AM +0000, liweihang wrote:
>> On 2020/11/16 21:47, Leon Romanovsky wrote:
>>> On Mon, Nov 16, 2020 at 07:58:38PM +0800, Weihang Li wrote:
>>>> From: Lang Cheng <chenglang@huawei.com>
>>>>
>>>> Stash is a mechanism that uses the core information carried by the ARM AXI
>>>> bus to access the L3 cache. It can be used to improve the performance by
>>>> increasing the hit ratio of L3 cache. CQs need to enable stash by default.
>>>>
>>>> Signed-off-by: Lang Cheng <chenglang@huawei.com>
>>>> Signed-off-by: Weihang Li <liweihang@huawei.com>
>>>> ---
>>>>  drivers/infiniband/hw/hns/hns_roce_common.h | 12 +++++++++
>>>>  drivers/infiniband/hw/hns/hns_roce_device.h |  1 +
>>>>  drivers/infiniband/hw/hns/hns_roce_hw_v2.c  |  3 +++
>>>>  drivers/infiniband/hw/hns/hns_roce_hw_v2.h  | 39 +++++++++++++++++------------
>>>>  4 files changed, 39 insertions(+), 16 deletions(-)
>>>>
>>>> diff --git a/drivers/infiniband/hw/hns/hns_roce_common.h b/drivers/infiniband/hw/hns/hns_roce_common.h
>>>> index f5669ff..8d96c4e 100644
>>>> --- a/drivers/infiniband/hw/hns/hns_roce_common.h
>>>> +++ b/drivers/infiniband/hw/hns/hns_roce_common.h
>>>> @@ -53,6 +53,18 @@
>>>>  #define roce_set_bit(origin, shift, val) \
>>>>  	roce_set_field((origin), (1ul << (shift)), (shift), (val))
>>>>
>>>> +#define FIELD_LOC(field_h, field_l) field_h, field_l
>>>> +
>>>> +#define _hr_reg_set(arr, field_h, field_l)                                     \
>>>> +	do {                                                                   \
>>>> +		BUILD_BUG_ON(((field_h) / 32) != ((field_l) / 32));            \
>>>> +		BUILD_BUG_ON((field_h) / 32 >= ARRAY_SIZE(arr));               \
>>>> +		(arr)[(field_h) / 32] |=                                       \
>>>> +			cpu_to_le32(GENMASK((field_h) % 32, (field_l) % 32));  \
>>>> +	} while (0)
>>>> +
>>>> +#define hr_reg_set(arr, field) _hr_reg_set(arr, field)
>>>
>>> I afraid that it is too much.
>>
>> Hi Leon,
>>
>> Thanks for the comments.
>>
>>> 1. FIELD_LOC() macro to hide two fields.
>>
>> Jason has suggested us to simplify the function of setting/getting bit/field in
>> hns driver like IBA_SET and IBA_GET.
>>
>> https://patchwork.kernel.org/project/linux-rdma/patch/1589982799-28728-3-git-send-email-liweihang@huawei.com/
>>
>> So we try to make it easier and clearer to define a bitfield for developers.
> 
> Jason asked to use genmask and FIELD_PREP, but you invented something else.
> 
> Thanks
> 

We use them in another interface 'hr_reg_write(arr, field, val)' which hasn't been
used in this series.

Does it make any unacceptable mistake? We would appreciate any suggestions :)

Thanks
Weihang



  reply	other threads:[~2020-11-17  8:36 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-16 11:58 [PATCH v2 for-next 0/2] RDMA/hns: Add supports for stash Weihang Li
2020-11-16 11:58 ` [PATCH v2 for-next 1/2] RDMA/hns: Add support for CQ stash Weihang Li
2020-11-16 13:46   ` Leon Romanovsky
2020-11-17  6:37     ` liweihang
2020-11-17  7:20       ` Leon Romanovsky
2020-11-17  8:35         ` liweihang [this message]
2020-11-17  8:50           ` Leon Romanovsky
2020-11-18 10:49             ` liweihang
2020-11-18 20:07               ` Jason Gunthorpe
2020-11-20  9:01                 ` liweihang
2020-11-16 11:58 ` [PATCH v2 for-next 2/2] RDMA/hns: Add support for QP stash Weihang Li

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