diff for duplicates of <20160525010150.GD7292@verge.net.au> diff --git a/a/1.txt b/N1/1.txt index 03c10c2..9cd205c 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,3 +1,13 @@ +From: Haishuang Yan <yanhaishuang@cmss.chinamobile.com> +Date: Sat, 21 May 2016 18:17:35 +0800 + +> In gre6 xmit path, we are sending a GRE packet, so set fl6 proto +> to IPPROTO_GRE properly. +> +> Signed-off-by: Haishuang Yan <yanhaishuang@cmss.chinamobile.com> + +Applied. + On Tue, May 17, 2016 at 05:15:33PM +0200, Geert Uytterhoeven wrote: > Currently the different SoCs in the R-Car Gen2 family use different > types of on-chip RAM for the jump stub: @@ -18,3 +28,76 @@ On Tue, May 17, 2016 at 05:15:33PM +0200, Geert Uytterhoeven wrote: > 1 file changed, 4 insertions(+), 9 deletions(-) Thanks, I have queued this up. + +Add the initial device tree for the R8A7792 SoC based Blanche board. +The board has 2 debug serial ports: SCIF0 and SCIF3; include support for +them, so that the serial console can work. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> + +--- + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/r8a7792-blanche.dts | 44 ++++++++++++++++++++++++++++++++++ + 2 files changed, 45 insertions(+) + +Index: renesas/arch/arm/boot/dts/Makefile +=================================================================== +--- renesas.orig/arch/arm/boot/dts/Makefile ++++ renesas/arch/arm/boot/dts/Makefile +@@ -638,6 +638,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ + r8a7790-lager.dtb \ + r8a7791-koelsch.dtb \ + r8a7791-porter.dtb \ ++ r8a7792-blanche.dtb \ + r8a7793-gose.dtb \ + r8a7794-alt.dtb \ + r8a7794-silk.dtb \ +Index: renesas/arch/arm/boot/dts/r8a7792-blanche.dts +=================================================================== +--- /dev/null ++++ renesas/arch/arm/boot/dts/r8a7792-blanche.dts +@@ -0,0 +1,44 @@ ++/* ++ * Device Tree Source for the Blanche board ++ * ++ * Copyright (C) 2016 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++/dts-v1/; ++#include "r8a7792.dtsi" ++ ++/ { ++ model = "Blanche"; ++ compatible = "renesas,blanche", "renesas,r8a7792"; ++ ++ aliases { ++ serial0 = &scif0; ++ serial1 = &scif3; ++ }; ++ ++ chosen { ++ bootargs = "ignore_loglevel"; ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0 0x40000000 0 0x40000000>; ++ }; ++}; ++ ++&extal_clk { ++ clock-frequency = <20000000>; ++}; ++ ++&scif0 { ++ status = "okay"; ++}; ++ ++&scif3 { ++ status = "okay"; ++}; diff --git a/a/content_digest b/N1/content_digest index d7072dd..97e6e40 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,13 +1,49 @@ + "ref\01463825855-7363-1-git-send-email-yanhaishuang@cmss.chinamobile.com\0" + "ref\01463825855-7363-2-git-send-email-yanhaishuang@cmss.chinamobile.com\0" "ref\01463498133-23918-1-git-send-email-geert+renesas@glider.be\0" + "ref\013205049.n7pM8utpHF@wasted.cogentembedded.com\0" + "From\0David Miller <davem@davemloft.net>\0" "From\0Simon Horman <horms@verge.net.au>\0" + "From\0Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>\0" + "Subject\0Re: [PATCH v2 2/2] ip6_gre: Set flowi6_proto as IPPROTO_GRE in xmit path.\0" "Subject\0Re: [PATCH] ARM: shmobile: rcar-gen2: Use ICRAM1 for jump stub on all SoCs\0" + "Subject\0[PATCH 12/13] ARM: dts: blanche: initial device tree\0" + "Date\0Tue, 24 May 2016 14:34:22 -0700 (PDT)\0" "Date\0Wed, 25 May 2016 10:01:51 +0900\0" + "Date\0Wed, 01 Jun 2016 01:32:35 +0300\0" + "To\0yanhaishuang@cmss.chinamobile.com\0" "To\0Geert Uytterhoeven <geert+renesas@glider.be>\0" + "To\0horms@verge.net.au" + linux-renesas-soc@vger.kernel.org + robh+dt@kernel.org + pawel.moll@arm.com + mark.rutland@arm.com + ijc+devicetree@hellion.org.uk + galak@codeaurora.org + " devicetree@vger.kernel.org\0" + "Cc\0kuznet@ms2.inr.ac.ru" + jmorris@namei.org + yoshfuji@linux-ipv6.org + netdev@vger.kernel.org + " linux-kernel@vger.kernel.org\0" "Cc\0Magnus Damm <magnus.damm@gmail.com>" linux-renesas-soc@vger.kernel.org " linux-arm-kernel@lists.infradead.org\0" + "Cc\0magnus.damm@gmail.com" + linux@arm.linux.org.uk + " linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" + "From: Haishuang Yan <yanhaishuang@cmss.chinamobile.com>\n" + "Date: Sat, 21 May 2016 18:17:35 +0800\n" + "\n" + "> In gre6 xmit path, we are sending a GRE packet, so set fl6 proto\n" + "> to IPPROTO_GRE properly.\n" + "> \n" + "> Signed-off-by: Haishuang Yan <yanhaishuang@cmss.chinamobile.com>\n" + "\n" + "Applied.\n" + "\n" "On Tue, May 17, 2016 at 05:15:33PM +0200, Geert Uytterhoeven wrote:\n" "> Currently the different SoCs in the R-Car Gen2 family use different\n" "> types of on-chip RAM for the jump stub:\n" @@ -27,6 +63,79 @@ "> arch/arm/mach-shmobile/pm-rcar-gen2.c | 13 ++++---------\n" "> 1 file changed, 4 insertions(+), 9 deletions(-)\n" "\n" - Thanks, I have queued this up. + "Thanks, I have queued this up.\n" + "\n" + "Add the initial device tree for the R8A7792 SoC based Blanche board.\n" + "The board has 2 debug serial ports: SCIF0 and SCIF3; include support for\n" + "them, so that the serial console can work.\n" + "\n" + "Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>\n" + "\n" + "---\n" + " arch/arm/boot/dts/Makefile | 1 \n" + " arch/arm/boot/dts/r8a7792-blanche.dts | 44 ++++++++++++++++++++++++++++++++++\n" + " 2 files changed, 45 insertions(+)\n" + "\n" + "Index: renesas/arch/arm/boot/dts/Makefile\n" + "===================================================================\n" + "--- renesas.orig/arch/arm/boot/dts/Makefile\n" + "+++ renesas/arch/arm/boot/dts/Makefile\n" + "@@ -638,6 +638,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \\\n" + " \tr8a7790-lager.dtb \\\n" + " \tr8a7791-koelsch.dtb \\\n" + " \tr8a7791-porter.dtb \\\n" + "+\tr8a7792-blanche.dtb \\\n" + " \tr8a7793-gose.dtb \\\n" + " \tr8a7794-alt.dtb \\\n" + " \tr8a7794-silk.dtb \\\n" + "Index: renesas/arch/arm/boot/dts/r8a7792-blanche.dts\n" + "===================================================================\n" + "--- /dev/null\n" + "+++ renesas/arch/arm/boot/dts/r8a7792-blanche.dts\n" + "@@ -0,0 +1,44 @@\n" + "+/*\n" + "+ * Device Tree Source for the Blanche board\n" + "+ *\n" + "+ * Copyright (C) 2016 Cogent Embedded, Inc.\n" + "+ *\n" + "+ * This file is licensed under the terms of the GNU General Public License\n" + "+ * version 2. This program is licensed \"as is\" without any warranty of any\n" + "+ * kind, whether express or implied.\n" + "+ */\n" + "+\n" + "+/dts-v1/;\n" + "+#include \"r8a7792.dtsi\"\n" + "+\n" + "+/ {\n" + "+\tmodel = \"Blanche\";\n" + "+\tcompatible = \"renesas,blanche\", \"renesas,r8a7792\";\n" + "+\n" + "+\taliases {\n" + "+\t\tserial0 = &scif0;\n" + "+\t\tserial1 = &scif3;\n" + "+\t};\n" + "+\n" + "+\tchosen {\n" + "+\t\tbootargs = \"ignore_loglevel\";\n" + "+\t\tstdout-path = \"serial0:115200n8\";\n" + "+\t};\n" + "+\n" + "+\tmemory@40000000 {\n" + "+\t\tdevice_type = \"memory\";\n" + "+\t\treg = <0 0x40000000 0 0x40000000>;\n" + "+\t};\n" + "+};\n" + "+\n" + "+&extal_clk {\n" + "+\tclock-frequency = <20000000>;\n" + "+};\n" + "+\n" + "+&scif0 {\n" + "+\tstatus = \"okay\";\n" + "+};\n" + "+\n" + "+&scif3 {\n" + "+\tstatus = \"okay\";\n" + +}; -13c472f48c6d07fb862a615f557e6de09742db0acba3a4266b338230305709a2 +262303bf153783a846c2725b39967e2ecdf710349f19a085ca74907a67851483
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